Voltage clamping circuit and bidirectional level converter comprising same

Abstract

The invention provides a voltage clamping circuit and a bidirectional level shifter comprising the same, and relates to the field of integrated circuit design. The circuit comprises a first phase inverter, a first transistor and a first diode, the first transistor is an NMOS, the input end of the first phase inverter is connected with an enable end, the power supply end is connected with a first power supply, the output end is connected with the grid electrode and the drain electrode of the first transistor, the source electrode of the first transistor is connected with a second power supply, and the drain electrode is used for outputting low level when the enable end outputs low level. And the anode of the first diode is connected with the substrate of the first transistor, and the cathode of the first diode is connected with a second power supply. By using the circuit of the NMOS transistor and the phase inverter, the stable grid bias voltage can be provided for the NMOS transmission tube, and the bias voltage change caused by power supply fluctuation, temperature change or process deviation can be reduced, so that the stability and the reliability of the circuit are improved; the first diode can avoid current consumption when the enable is turned off.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit design, and in particular to a voltage clamping circuit and a bidirectional level converter comprising the same. Background Art

[0002] In the traditional bidirectional level converter design, the N-type Metal-Oxide-Semiconductor (NMOS) transmission tube usually adopts a voltage clamping structure combining an inverter (M1-M5) and a P-type Metal-Oxide-Semiconductor (PMOS) transistor (M6) to provide a stable gate bias voltage (Vbias) for the transmission tube in the converter. Figure 1 It is a voltage clamping structure based on an inverter and POMS in the prior art, such as Figure 1 As shown. The working principle of this design is as follows: When the chip receives the enable signal (ENN) as a low level, this causes the NMOS transistor M1 that constitutes the inverter to turn off, and the PMOS transistors M2 to M5 are turned on accordingly. At this time, the DC power supply voltage (VCCB) begins to charge the source of the PMOS transistor M6, causing its source voltage to gradually rise. When the source voltage of M6 reaches the DC power supply voltage VCCA plus the threshold voltage (Vthp) of the PMOS transistor, that is, VCCA+Vthp, M6 begins to turn on, thereby significantly increasing the current in this branch, and then stabilizing the voltage at this point at a level close to VCCA+Vthp, achieving voltage clamping. Although this structure can effectively provide the required gate bias voltage for the transmission tube in the bidirectional level converter, its performance is easily affected by the deviation of the manufacturing process and the change of ambient temperature, which may have an adverse effect on the stability and reliability of the bidirectional level converter. Summary of the invention

[0003] The technical problem to be solved by the present disclosure is to overcome the defect that in the design of a bidirectional level converter in the prior art, the gate of an NMOS transmission tube usually adopts a voltage clamping structure combining an inverter and a PMOS transistor to realize the supply of a bias voltage, and the performance of this structure may be affected by manufacturing process deviations and ambient temperature changes. A voltage clamping circuit and a bidirectional level converter including the same are provided.

[0004] The present invention solves the above technical problems through the following technical solutions:

[0005] The present disclosure provides a voltage clamping circuit, the voltage clamping circuit comprising: a first inverter, a first transistor and a first diode, the first transistor being an NMOS transistor;

[0006] The input terminal of the first inverter is connected to the enable terminal, the power terminal of the first inverter is connected to the first power supply, and the output terminal of the first inverter is respectively connected to the gate and the drain of the first transistor;

[0007] The source of the first transistor is connected to the second power supply, and the drain of the first transistor is used to provide a gate bias voltage for the NMOS transmission tube connected to the first transistor when the enable signal output from the enable terminal is at a low level;

[0008] An anode of the first diode is connected to the substrate of the first transistor, and a cathode of the first diode is connected to the second power supply.

[0009] In this solution, a circuit consisting of an NMOS transistor and an inverter is set to provide a gate bias voltage for the NMOS transmission tube, which helps to reduce the bias voltage changes caused by power supply fluctuations, temperature changes or process deviations, thereby improving the stability and reliability of the circuit; the presence of the first diode can prevent the current of the second power supply from flowing directly to the ground through the body diode of the first transistor when the chip is enabled and turned off, thereby avoiding unnecessary current consumption.

[0010] Preferably, the first inverter comprises an NMOS transistor and a PMOS transistor;

[0011] The enable terminal is connected to the gate of the NMOS transistor and the gate of the PMOS transistor respectively;

[0012] The drain of the NMOS transistor is connected to the drain of the PMOS transistor and the gate of the first transistor respectively;

[0013] The source of the PMOS transistor is connected to the first power supply;

[0014] The NMOS transistor is used to be turned off when the enable signal is at a low level, and the PMOS transistor is used to be turned on when the enable signal is at a low level, so that the first power source charges the drain of the first transistor.

[0015] Preferably, the first inverter comprises an NMOS transistor and a plurality of PMOS transistors;

[0016] The enable terminal is respectively connected to the gate of the NMOS transistor and the gate of each of the PMOS transistors;

[0017] A plurality of the PMOS transistors are sequentially connected in series to form a PMOS transistor group, a source at one end of the PMOS transistor group is connected to the first power supply, and a drain at the other end of the PMOS transistor group is connected to the drain of the NMOS transistor;

[0018] The drain of the NMOS transistor is also connected to the gate of the first transistor;

[0019] The NMOS transistor is used to be turned off when the enable signal is at a low level, and the PMOS transistor group is used to be turned on when the enable signal is at a low level, so that the first power supply charges the drain of the first transistor.

[0020] In this solution, by providing a plurality of PMOS transistors connected in series, power consumption can be reduced, and when the enable signal is at a low level, the voltage of the first power supply can be more effectively converted into the drain voltage of the first transistor, thereby improving the efficiency of level conversion.

[0021] Preferably, the voltage clamping circuit further comprises a first current branch, the first current branch comprises a branch transistor; the branch transistor is a PMOS transistor;

[0022] The gate of the branch transistor is connected to the enable terminal, the source of the branch transistor is connected to the gate of the NMOS transmission tube, and the drain of the branch transistor is connected to the second power supply;

[0023] The branch transistor is used to turn on when the enable signal changes from a high level to a low level and the gate bias voltage is less than a preset voltage, so that the second power supply provides a voltage for the gate of the NMOS transmission tube;

[0024] The branch transistor is further configured to be turned off when the gate bias voltage is greater than or equal to the preset voltage.

[0025] In this solution, by setting a branch transistor, the circuit can provide a stable voltage for the gate of the NMOS transmission tube when the enable signal changes from a high level to a low level. When the enable signal is at a low level, the branch transistor is turned on, allowing the second power supply to charge the gate of the NMOS transmission tube. At this time, the first power supply and the second power supply charge the gate bias voltage at the same time, which can shorten the establishment time of the gate bias voltage, help optimize power management and reduce unnecessary energy consumption.

[0026] Preferably, the first current branch further includes a second diode;

[0027] The second diode is arranged between the second power supply and the branch transistor, and the cathode of the second diode is connected to the drain of the branch transistor, and the anode of the second diode is connected to the second power supply.

[0028] In this solution, when the branch transistor is turned on, the second power supply is allowed to charge the gate of the NMOS transmission tube. At this time, the forward conduction voltage drop characteristic of the second diode provides a fixed voltage drop.

[0029] Preferably, the voltage clamping circuit further comprises a second current branch, wherein the second current branch comprises a second NMOS transistor;

[0030] The gate of the second NMOS transistor is connected to the enable terminal, the drain of the second NMOS transistor is connected to the first power supply, and the source of the second NMOS transistor is connected to the gate of the NMOS transmission tube;

[0031] The second NMOS transistor is used to be turned on at the moment when the enable signal changes from a high level to a low level, and to enable the first power supply to provide a voltage to the gate of the NMOS transmission tube within a preset time period.

[0032] In this solution, the second NMOS transistor is turned on at the moment the enable signal changes from a high level to a low level, so that the first power supply can provide voltage to the gate of the NMOS transmission tube, which can effectively shorten the establishment time of the gate bias voltage, help optimize power management and reduce unnecessary energy consumption.

[0033] Preferably, the second current branch further includes a monostable pulse circuit;

[0034] The input end of the monostable pulse circuit is connected to the enable end, the power supply end of the monostable pulse circuit is connected to the first power supply, and the output end of the monostable pulse circuit is connected to the gate of the second NMOS transistor;

[0035] The monostable pulse circuit is used to generate a pulse signal corresponding to the preset time period at the moment when the enable signal changes from a high level to a low level; the pulse signal is used to instruct the second NMOS transistor to turn on.

[0036] In this solution, by setting a monostable pulse circuit, a precise pulse signal can be generated when the enable signal changes from a high level to a low level. The duration of this pulse signal can be preset, thereby accurately controlling the turn-on time of the second NMOS transistor; the monostable pulse circuit quickly responds to changes in the enable signal, ensuring that the second NMOS transistor is turned on in time, and providing the necessary voltage for the gate of the NMOS transmission tube.

[0037] Preferably, after the preset time period ends, the state of the second NMOS transistor is turned off.

[0038] In this solution, after the preset time period ends, the second NMOS transistor is automatically turned off, which reduces power consumption when not needed and improves the energy efficiency of the circuit.

[0039] Preferably, the monostable pulse circuit comprises: a second inverter, a delay circuit component, a NAND gate and a third inverter;

[0040] The input end of the second inverter is connected to the enable end, and the output end of the second inverter is respectively connected to the input end of the delay circuit component and the input end of the NAND gate;

[0041] The output end of the delay circuit component is connected to the input end of the NAND gate;

[0042] The output end of the NAND gate is connected to the input end of the third inverter, and the output end of the third inverter is connected to the gate of the second NMOS transistor.

[0043] The present disclosure also provides a bidirectional level converter, which includes the voltage clamping circuit as described above.

[0044] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0045] The positive and progressive effects of this disclosure are:

[0046] The present invention provides a gate bias voltage for the NMOS transmission tube by setting a circuit composed of an NMOS transistor and an inverter, which helps to reduce the bias voltage changes caused by power supply fluctuations, temperature changes or process deviations, thereby improving the stability and reliability of the circuit; the presence of the first diode can prevent the current of the second power supply from flowing directly to the ground through the body diode of the first transistor when the chip is enabled and turned off, thereby avoiding unnecessary current consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a voltage clamping structure based on an inverter and POMS in the prior art;

[0048] Figure 2 A schematic diagram of a voltage clamping circuit structure provided for an exemplary embodiment of the present disclosure;

[0049] Figure 3 A voltage clamping circuit provided for an exemplary embodiment of the present disclosure includes a structural schematic diagram of a first current branch;

[0050] Figure 4 A voltage clamping circuit provided for an exemplary embodiment of the present disclosure includes a structural schematic diagram of a first current branch and a second current branch;

[0051] Figure 5 A structural schematic diagram of a monostable pulse circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0053] It should be noted that if this embodiment involves directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0054] In addition, if there are descriptions involving "first", "second", etc. in this embodiment, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0055] Example 1

[0056] See also Figures 2 to 5 , this embodiment provides a voltage clamping circuit, Figure 2A schematic diagram of a voltage clamping circuit structure is provided for an exemplary embodiment of the present disclosure. The voltage clamping circuit comprises: a first inverter (M1-M5), a first transistor (M6) and a first diode (D1). The first transistor (M6) is an NMOS transistor. The input end of the first inverter (M1-M5) is connected to an enable end (ENN), the power end of the first inverter (M1-M5) is connected to a first power supply (VCCB), the output end of the first inverter (M1-M5) is respectively connected to a gate and a drain of the first transistor (M6), the source of the first transistor (M6) is connected to a second power supply (VCCA), the drain of the first transistor (M6) is used to provide a gate bias voltage (Vbias) for an NMOS transmission tube (not shown in the figure) connected to the first transistor (M6) when an enable signal output from the enable end (ENN) is at a low level, the anode of the first diode (D1) is connected to a substrate of the first transistor (M6), and the cathode of the first diode (D1) is connected to the second power supply (VCCA). The present invention provides a gate bias voltage for the NMOS transmission tube by setting a circuit composed of an NMOS transistor and an inverter, which helps to reduce the bias voltage changes caused by power supply fluctuations, temperature changes or process deviations, thereby improving the stability and reliability of the circuit; the presence of the first diode can prevent the current of the second power supply from flowing directly to the ground through the body diode of the first transistor when the chip is enabled and turned off, thereby avoiding unnecessary current consumption.

[0057] Specifically, the present disclosure uses a first inverter (M1-M5) and a first transistor (i.e., an NMOS transistor M6) to implement voltage clamping, wherein the first transistor is connected in a diode manner. The working principle of the voltage clamping circuit is as follows: when the chip is enabled and the enable signal output by the enable terminal (ENN) is at a low level, the first power supply (VCCB) charges the drain of the first transistor (M6), and when the drain voltage of the first transistor (M6) rises to the second power supply voltage (VCCA) + the threshold voltage (Vthn) of the first transistor (M6), i.e., VCCA+Vthn, the first transistor (M6) is turned on, the current in the branch where the first transistor (M6) is located increases, and the voltage is clamped near VCCA+Vthn. Since the gate bias voltage (Vbias) is determined by the turn-on voltage of the first transistor (M6), the circuit composed of the NMOS transistor (i.e., the first transistor M6) and the inverter (M1-M5) can provide a stable gate bias voltage for the NMOS transmission tube.

[0058] The anode of the first diode (D1) is connected to the substrate of the first transistor (M6), and the cathode of the first diode (D1) is connected to the second power supply (VCCA). The function of the first diode (D1) is that when the chip is enabled and turned off, the gate bias voltage (Vbias) is 0. At this time, the voltage of the second power supply (VCCA) is higher than the gate bias voltage (Vbias). The first diode (D1) can prevent the second power supply (VCCA) voltage from generating a ground current through the body diode of the first transistor (M6). The body diode of the first transistor (M6) refers to the body diode of the NMOS transistor, which is a PN junction diode formed by the drain (D) and the substrate (B) of the NMOS transistor. When the gate (G) of the NMOS transistor carries a negative voltage relative to the source (S), the body diode is reverse biased and does not conduct. However, if the gate (G) voltage is low, that is, in the off state, the body diode may be forward-conducted due to the voltage between the drain (D) and the substrate (B), thereby generating a current to the ground. In this case, the function of the first diode (D1) is to act as a protection element to prevent such unexpected current flow. When the enable signal is at a low level, the first diode (D1) is turned on, thereby providing a low impedance path to direct the current that may flow to the ground through the body diode to the first diode (D1) instead of flowing to the body diode. In this way, the first diode (D1) effectively clamps the voltage, preventing unnecessary power consumption and possible damage, thereby protecting the safety and stability of the circuit.

[0059] Combination Figure 2 To further explain, in this embodiment, the first inverter (M1-M5) includes an NMOS transistor (M1) and a plurality of PMOS transistors (M2-M5). In this embodiment, four PMOS transistors (M2-M5) are used. In other embodiments, other numbers of PMOS transistors may be used, and the number of PMOS transistors may be selected according to actual conditions.

[0060] The enable terminal (ENN) in this embodiment is respectively connected to the gate of the NMOS transistor (M1) and the gate of each PMOS transistor (M2-M5), and a plurality of PMOS transistors (M2-M5) are sequentially connected in series (i.e., the drain of M5 is connected to the source of M4, the drain of M4 is connected to the source of M3, and the drain of M3 is connected to the source of M2) to form a PMOS transistor group, wherein the source of one end of the PMOS transistor group (i.e., the source of M5) is connected to the first power supply (VCCB), the drain of the other end of the PMOS transistor group (i.e., the drain of M2) is connected to the drain of the NMOS transistor (M1), the drain of the NMOS transistor (M1) is also connected to the gate of the first transistor (M6), and the source of the NMOS transistor (M1) is grounded. The NMOS transistor (M1) is used to be turned off when the enable signal is at a low level, and the PMOS transistor group (M2-M5) is used to be turned on when the enable signal is at a low level, so that the first power supply (VCCB) charges the drain of the first transistor (M6). By providing a plurality of PMOS transistors (M2-M5) connected in series, power consumption can be reduced, and at the same time, when the enable signal is at a low level, the voltage of the first power supply (VCCB) can be more effectively converted into the drain voltage of the first transistor (M6), thereby improving the efficiency of level conversion.

[0061] In other embodiments, the first inverter may also include an NMOS transistor and a PMOS transistor, the enable end is respectively connected to the gate of the NMOS transistor and the gate of the PMOS transistor, the drain of the NMOS transistor is respectively connected to the drain of the PMOS transistor and the gate of the first transistor, the source of the PMOS transistor is connected to the first power supply, the source of the NMOS transistor is grounded, the NMOS transistor is used to turn off when the enable signal is at a low level, and the PMOS transistor is used to turn on when the enable signal is at a low level, so that the first power supply charges the drain of the first transistor.

[0062] In this embodiment, Figure 3 A voltage clamping circuit provided by an exemplary embodiment of the present disclosure includes a schematic diagram of a structure of a first current branch, such as Figure 3As shown, the voltage clamping circuit also includes a first current branch, the first current branch includes a branch transistor (M7) and a second diode (D2), the branch transistor (M7) is a PMOS transistor, the gate of the branch transistor (M7) is connected to the enable terminal (ENN), the source of the branch transistor (M7) is connected to the gate of the NMOS transmission tube, the second diode (D2) is arranged between the second power supply (VCCA) and the branch transistor (M7), the cathode of the second diode (D2) is connected to the drain of the branch transistor (M7), and the anode of the second diode (D2) is connected to the second power supply (VCCA). The branch transistor (M7) is used to turn on when the enable signal changes from a high level to a low level and the gate bias voltage (Vbias) is less than a preset voltage, so that the second power supply (VCCA) provides a voltage for the gate of the NMOS transmission tube. The preset voltage here is the difference between the second power supply (VCCA) voltage and the forward conduction voltage drop of the second diode (D2), that is, VCCA-0.7V. The forward conduction voltage drop of the second diode (D2) means that when the second diode (D2) is in a forward conduction state, a fixed voltage drop will be generated across it. For a silicon diode, this voltage drop is approximately 0.7V. The branch transistor (M7) is also used to turn off when the gate bias voltage (Vbias) is greater than or equal to the preset voltage.

[0063] By using the branch transistor (M7) and the second diode (D2) in cooperation, the circuit can provide a stable voltage for the gate of the NMOS transmission tube when the enable signal changes from a high level to a low level, and the forward conduction voltage reduction characteristic of the second diode (D2) provides a fixed voltage drop; when the enable signal is at a low level, the branch transistor (M7) is turned on, allowing the second power supply (VCCA) to charge the gate of the NMOS transmission tube. At this time, the first power supply (VCCB) and the second power supply (VCCA) charge the gate bias voltage (Vbias) at the same time, which can shorten the establishment time of the gate bias voltage, help optimize power management and reduce unnecessary energy consumption.

[0064] Specifically, when the chip is enabled and the enable signal output by the enable terminal (ENN) is at a low level, the NMOS transistor (M1) in the first inverter (M1-M5) is turned off, and when the multiple PMOS transistors (M2-M5) are turned on, the on-resistance of the multiple PMOS transistors (M2-M5) is very large, generally at the megaohm (MΩ) level. If the voltage is established only through the multiple PMOS transistors (M2-M5), it will take a very long time. Therefore, for the sake of low power consumption, an additional first current branch can be added to shorten the establishment time of the gate bias voltage (Vbias). The process of establishing the gate bias voltage (Vbias) is as follows, combined with Figure 3 To elaborate:

[0065] First stage: The enable signal changes from high level to low level, the NMOS transistor (M1) is turned off, multiple PMOS transistors (M2 - M5) are turned on, and the gate bias voltage (Vbias) is less than the preset voltage (i.e., VCCA - 0.7V). The path of the branch transistor (M7) is turned on, and the impedance of the path of the branch transistor (M7) is very low. The second power supply (VCCA) provides voltage for the gate of the NMOS transfer transistor, and the gate bias voltage (Vbias) rises.

[0066] Second stage: If the gate bias voltage (Vbias) does not rise to the preset voltage (i.e., VCCA - 0.7V), the path of the branch transistor (M7) remains on.

[0067] Third stage: The gate bias voltage (Vbias) is greater than or equal to the preset voltage (i.e., VCCA - 0.7V), the path of the branch transistor (M7) is turned off. At this time, the gate bias voltage (Vbias) has approached the final required voltage (i.e., VCCA + Vthn), and it is charged only through the paths of multiple PMOS transistors (M2 - M5). At this time, the voltage rise speed becomes slow.

[0068] Fourth stage: The gate bias voltage (Vbias) rises to VCCA + Vthn (when VCCB < VCCA + Vthn, it rises to VCCB). Multiple PMOS transistors (M2 - M5) are turned on, the first transistor (M6) is turned on, and the gate bias voltage (Vbias) is clamped at VCCA + Vthn and no longer changes. At this time, the NMOS transfer transistor enters the normal working state.

[0069] In this embodiment, Figure 4 is a schematic structural diagram of a voltage clamping circuit provided by an exemplary embodiment of the present disclosure, including a first current branch and a second current branch, as Figure 4As shown, the voltage clamp circuit also includes a second current branch, the second current branch includes a second NMOS transistor (M8), the gate of the second NMOS transistor (M8) is connected to the enable terminal (ENN), the drain of the second NMOS transistor (M8) is connected to the first power supply (VCCB), a first resistor (R1) is further provided between the drain of the second NMOS transistor (M8) and the first power supply (VCCB), the source of the second NMOS transistor (M8) is connected to the gate of the NMOS transmission tube, and the second NMOS transistor (M8) is used to turn on at the moment when the enable signal changes from a high level to a low level, and to enable the first power supply (VCCB) to provide a voltage to the gate of the NMOS transmission tube within a preset time period. Through the cooperation of the first resistor (R1) and the second NMOS transistor (M8), a stable voltage can be provided to the gate of the NMOS transmission tube within a preset time period, which helps to maintain the stable operation of the circuit; the first resistor (R1) can limit the current passing through the second NMOS transistor (M8), thereby reducing the power consumption when the enable signal is at a low level. The second NMOS transistor (M8) is turned on at the moment when the enable signal changes from a high level to a low level, so that the first power supply (VCCB) can provide a voltage for the gate of the NMOS transmission tube, which can effectively shorten the establishment time of the gate bias voltage, help optimize power management and reduce unnecessary energy consumption.

[0070] Combination Figure 4 To continue to explain, in this embodiment, the second current branch also includes a monostable pulse circuit, the input end of the monostable pulse circuit is connected to the enable end (ENN), the power end of the monostable pulse circuit is connected to the first power supply (VCCB), and the output end of the monostable pulse circuit is connected to the gate of the second NMOS transistor (M8). The monostable pulse circuit is used to generate a pulse signal corresponding to a preset time period at the moment when the enable signal changes from a high level to a low level, and the pulse signal is used to indicate that the second NMOS transistor (M8) is turned on. After the preset time period ends, the state of the second NMOS transistor (M8) is an off state. By setting the monostable pulse circuit, an accurate pulse signal can be generated when the enable signal changes from a high level to a low level, and the duration of this pulse signal can be preset, thereby accurately controlling the turn-on time of the second NMOS transistor (M8); the monostable pulse circuit quickly responds to the change of the enable signal, ensuring that the second NMOS transistor (M8) is turned on in time, and providing the necessary voltage for the gate of the NMOS transmission tube; after the preset time period ends, the second NMOS transistor (M8) is automatically turned off, reducing power consumption when not needed, and improving the energy efficiency of the circuit.

[0071] Specifically, on the basis of setting the first current branch, setting the second current branch can further shorten the establishment time of the gate bias voltage (Vbias). Figure 4Further describe the process of establishing the gate bias voltage (Vbias):

[0072] The first stage: The enable signal changes from high level to low level, the NMOS transistor (M1) is turned off, multiple PMOS transistors (M2 - M5) are turned on, and the gate bias voltage (Vbias) is much less than the preset voltage (i.e., VCCA - 0.7V). The path of the branch transistor (M7) is turned on, the monostable pulse circuit generates a pulse signal, and the second NMOS transistor (M8) is turned on. In this stage, both the first current branch and the second current branch are turned on, and the impedances of the path of the branch transistor (M7) and the path of the second NMOS transistor (M8) are both very low, so the gate bias voltage (Vbias) rises sharply.

[0073] The second stage: After the pulse signal ends within the preset time period, the paths of multiple PMOS transistors (M2 - M5) are still turned on. If the gate bias voltage (Vbias) has not risen to the preset voltage (i.e., VCCA - 0.7V), the path of the branch transistor (M7) is still turned on, and the path of the second NMOS transistor (M8) is turned off. In this stage, in order to avoid overshoot of the gate bias voltage (Vbias), the path of the second NMOS transistor (M8) is turned off to slow down the rising speed of the gate bias voltage (Vbias).

[0074] The third stage: The gate bias voltage (Vbias) is greater than or equal to the preset voltage (i.e., VCCA - 0.7V), the paths of multiple PMOS transistors (M2 - M5) are still turned on, the path of the branch transistor (M7) is turned off, and the path of the second NMOS transistor (M8) is turned off. In this stage, the gate bias voltage (Vbias) has approached the final required voltage (i.e., VCCA + Vthn), and it is charged only through the paths of multiple PMOS transistors (M2 - M5). At this time, the voltage rising speed is the slowest.

[0075] The fourth stage: The gate bias voltage (Vbias) rises to VCCA + Vthn (when VCCB < VCCA + Vthn, it rises to VCCB). Multiple PMOS transistors (M2 - M5) are turned on, the first transistor (M6) is turned on, the path of the branch transistor (M7) is in the off state, and the path of the second NMOS transistor (M8) is in the off state. The gate bias voltage (Vbias) is clamped at VCCA + Vthn and no longer changes. At this time, the NMOS transmission tube enters the normal working state.

[0076] In this embodiment, Figure 5 is a schematic structural diagram of a monostable pulse circuit provided by an exemplary embodiment of the present disclosure, as Figure 5As shown, the monostable pulse circuit includes: a second inverter (INV1), a delay circuit component, a NAND gate (NAND) and a third inverter (INV4). The delay circuit component includes a fourth inverter (INV2), a fifth inverter and a sixth inverter (INV3), the fifth inverter includes an NMOS transistor (M9) and a PMOS transistor (M10), the source of the PMOS transistor (M10) is connected to the first power supply (VCCB), the drain of the PMOS transistor (M10) is connected to the drain of the NMOS transistor (M9) through the second resistor (R2), and the source of the NMOS transistor (M9) is grounded.

[0077] The input end of the second inverter (INV1) is connected to the enable end (ENN), the output end of the second inverter (INV1) is respectively connected to the input end of the fourth inverter (INV2) and the input end of the NAND gate (NAND), the output end of the fourth inverter (INV2) is respectively connected to the gate of the NMOS transistor (M9) and the gate of the PMOS transistor (M10), the drain of the NMOS transistor (M9) is respectively connected to a capacitor (C1) and the input end of the sixth inverter (INV3), the other end of the capacitor (C1) is grounded, the output end of the sixth inverter (INV3) is connected to the input end of the NAND gate (NAND), the output end of the NAND gate (NAND) is connected to the input end of the third inverter (INV4), and the output end of the third inverter (INV4) is connected to the gate of the second NMOS transistor (M8). The above-mentioned monostable pulse circuit performs inversion processing and delay processing on the enable signal, and then inputs it into the NAND gate (NAND) for logic processing. Thus, when the enable signal changes from high level to low level, the two signals will have a window period in which they are both high, making the output of the NAND gate high, thus realizing the generation of a pulse signal. At the same time, the pulse width of the pulse signal is controlled by the size of the second resistor (R2) and the capacitor (C1).

[0078] Example 2

[0079] An embodiment of the present application further provides a bidirectional level converter, and the bidirectional level converter includes the voltage clamping circuit as described above.

[0080] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A voltage clamping circuit, characterized in that: The voltage clamping circuit comprises: a first inverter, a first transistor and a first diode, wherein the first transistor is an NMOS transistor; The input terminal of the first inverter is connected to the enable terminal, the power terminal of the first inverter is connected to the first power supply, and the output terminal of the first inverter is respectively connected to the gate and the drain of the first transistor; The source of the first transistor is connected to the second power supply, and the drain of the first transistor is used to provide a gate bias voltage for the NMOS transmission tube connected to the first transistor when the enable signal output from the enable terminal is at a low level; An anode of the first diode is connected to the substrate of the first transistor, and a cathode of the first diode is connected to the second power supply.

2. The voltage clamping circuit according to claim 1, characterized in that: The first inverter includes an NMOS transistor and a PMOS transistor; The enable terminal is connected to the gate of the NMOS transistor and the gate of the PMOS transistor respectively; The drain of the NMOS transistor is connected to the drain of the PMOS transistor and the gate of the first transistor respectively; The source of the PMOS transistor is connected to the first power supply; The NMOS transistor is used to be turned off when the enable signal is at a low level, and the PMOS transistor is used to be turned on when the enable signal is at a low level, so that the first power source charges the drain of the first transistor.

3. The voltage clamping circuit according to claim 1, wherein: The first inverter includes an NMOS transistor and a plurality of PMOS transistors; The enable terminal is respectively connected to the gate of the NMOS transistor and the gate of each of the PMOS transistors; A plurality of the PMOS transistors are sequentially connected in series to form a PMOS transistor group, a source at one end of the PMOS transistor group is connected to the first power supply, and a drain at the other end of the PMOS transistor group is connected to the drain of the NMOS transistor; The drain of the NMOS transistor is also connected to the gate of the first transistor; The NMOS transistor is used to be turned off when the enable signal is at a low level, and the PMOS transistor group is used to be turned on when the enable signal is at a low level, so that the first power supply charges the drain of the first transistor.

4. The voltage clamping circuit according to claim 1, wherein: The voltage clamping circuit further includes a first current branch, the first current branch includes a branch transistor; the branch transistor is a PMOS transistor; The gate of the branch transistor is connected to the enable terminal, the source of the branch transistor is connected to the gate of the NMOS transmission tube, and the drain of the branch transistor is connected to the second power supply; The branch transistor is used to turn on when the enable signal changes from a high level to a low level and the gate bias voltage is less than a preset voltage, so that the second power supply provides a voltage for the gate of the NMOS transmission tube; The branch transistor is further configured to be turned off when the gate bias voltage is greater than or equal to the preset voltage.

5. The voltage clamping circuit according to claim 4, characterized in that: The first current branch also includes a second diode; The second diode is arranged between the second power supply and the branch transistor, and the cathode of the second diode is connected to the drain of the branch transistor, and the anode of the second diode is connected to the second power supply.

6. The voltage clamping circuit according to claim 1, wherein: The voltage clamp circuit further includes a second current branch, wherein the second current branch includes a second NMOS transistor; The gate of the second NMOS transistor is connected to the enable terminal, the drain of the second NMOS transistor is connected to the first power supply, and the source of the second NMOS transistor is connected to the gate of the NMOS transmission tube; The second NMOS transistor is used to be turned on at the moment when the enable signal changes from a high level to a low level, and to enable the first power supply to provide a voltage to the gate of the NMOS transmission tube within a preset time period.

7. The voltage clamping circuit according to claim 6, characterized in that: The second current branch also includes a monostable pulse circuit; The input end of the monostable pulse circuit is connected to the enable end, the power supply end of the monostable pulse circuit is connected to the first power supply, and the output end of the monostable pulse circuit is connected to the gate of the second NMOS transistor; The monostable pulse circuit is used to generate a pulse signal corresponding to the preset time period at the moment when the enable signal changes from a high level to a low level; the pulse signal is used to instruct the second NMOS transistor to turn on.

8. The voltage clamping circuit according to claim 7, characterized in that: After the preset time period ends, the state of the second NMOS transistor is turned off.

9. The voltage clamping circuit according to claim 8, characterized in that: The monostable pulse circuit comprises: a second inverter, a delay circuit component, a NAND gate and a third inverter; The input end of the second inverter is connected to the enable end, and the output end of the second inverter is respectively connected to the input end of the delay circuit component and the input end of the NAND gate; The output end of the delay circuit component is connected to the input end of the NAND gate; The output end of the NAND gate is connected to the input end of the third inverter, and the output end of the third inverter is connected to the gate of the second NMOS transistor.

10. A bidirectional level converter, characterized in that: The bidirectional level converter comprises a voltage clamping circuit as claimed in any one of claims 1 to 9.

Images