NMOS (N-channel metal oxide semiconductor) tube parallel drive circuit, battery management system and battery pack

Abstract

The invention relates to the technical field of battery management, in particular to an NMOS tube parallel drive circuit, a battery management system and a battery pack, the NMOS tube parallel drive circuit comprises a level control circuit, a voltage stabilization and current expansion drive circuit and a discharge circuit, and the level control circuit is used for controlling connection or disconnection of a BMS battery end and the voltage stabilization and current expansion drive circuit; the voltage-stabilizing and current-expanding driving circuit is used for acquiring a stable driving power supply from a BMS battery end, amplifying an output current of the BMS battery end and then transmitting the amplified output current to the NMOS transistor parallel switching circuit, so that each NMOS transistor is quickly conducted; and the discharge circuit is used for quickly discharging charges between the grid electrode and the source electrode of each NMOS tube in the NMOS tube parallel switching circuit, so that each NMOS tube is quickly closed. In this way, the functions of driving voltage stabilization, current expansion and the like can be achieved so as to prevent NMOS tube explosion, and the circuit can be compatible with BMS systems of different voltage levels.

Description

Technical Field

[0001] The present application relates to the field of battery management technology, and in particular to an NMOS tube parallel drive circuit, a battery management system and a battery pack. Background Art

[0002] In the battery management system (BMS), MOS tubes are often used as electronic switches in series in the charging and discharging circuits of the circuit to achieve protection functions such as overcharging, overvoltage, overtemperature and short circuit of the battery pack, and prevent the battery pack from catching fire and other problems. Therefore, the application of MOS tubes is a key point in the design of the BMS system. When the operating voltage of the BMS system is higher than the driving voltage of the MOS tube, the problem of voltage regulation of the driving circuit power supply needs to be considered when designing the MOS tube driver. At the same time, due to the Miller effect of the MOS tube, there is switching loss during the opening and closing process of the MOS tube, which causes the MOS junction temperature to be too high and the tube to explode. It is also necessary to consider the driving current and shutdown current capabilities. Summary of the invention

[0003] In view of this, the purpose of this application is to provide an NMOS tube parallel drive circuit, a battery management system and a battery pack, which can realize drive voltage stabilization, current expansion and other functions to prevent NMOS tube explosion, and can be compatible with BMS systems of different voltage levels.

[0004] In a first aspect, an embodiment of the present application provides an NMOS tube parallel drive circuit, wherein the NMOS tube parallel drive circuit includes a level control circuit, a voltage stabilizing current expansion drive circuit, and a discharge and bleeding circuit; the level control circuit is electrically connected to the BMS battery terminal and the voltage stabilizing current expansion drive circuit, respectively, and the discharge and bleeding circuit is electrically connected to the voltage stabilizing current expansion drive circuit and the NMOS tube parallel switch circuit, respectively; wherein,

[0005] The level control circuit is used to control the connection between the BMS battery terminal and the voltage stabilizing and current expanding driving circuit by receiving a level signal;

[0006] The voltage-stabilizing and current-expanding driving circuit is used to obtain a stable driving power supply from the BMS battery terminal, and transmit the output current of the BMS battery terminal to each NMOS tube in the NMOS tube parallel switch circuit through the discharge circuit after amplification, so that each NMOS tube is quickly turned on;

[0007] The discharge circuit is used to quickly discharge the charge between the gate and the source of each NMOS tube in the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned off.

[0008] In a second aspect, an embodiment of the present application provides a battery management system, which includes an NMOS tube parallel switch circuit and the NMOS tube parallel drive circuit described in the first aspect, and the NMOS tube parallel drive circuit is electrically connected to the NMOS tube parallel switch circuit, the BMS battery terminal, and the microcontroller, respectively.

[0009] In a third aspect, an embodiment of the present application provides a battery pack, which includes a battery cell module and the battery management system described in the second aspect.

[0010] The embodiment of the present application provides an NMOS tube parallel drive circuit, a battery management system and a battery pack, wherein the NMOS tube parallel drive circuit includes a level control circuit, a voltage stabilization and current expansion drive circuit and a discharge and discharge circuit, wherein the level control circuit is used to control the connection or disconnection between the BMS battery terminal and the voltage stabilization and current expansion drive circuit; the voltage stabilization and current expansion drive circuit is used to obtain a stable driving power supply from the BMS battery terminal, and amplify the output current of the BMS battery terminal and transmit it to the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned on; the discharge and discharge circuit is used to quickly discharge the charge between the gate and the source of each NMOS tube in the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned off. In this way, the present application can realize the functions of driving voltage stabilization, current expansion, etc. to prevent NMOS tube explosion, and can be compatible with BMS systems of different voltage levels.

[0011] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 One of the structural schematic diagrams of an NMOS tube parallel drive circuit provided in an embodiment of the present application;

[0014] Figure 2 A schematic diagram of the structure of a level control circuit provided in an embodiment of the present application;

[0015] Figure 3 A schematic diagram of the structure of a voltage-stabilizing and current-expanding driving circuit provided in an embodiment of the present application;

[0016] Figure 4 A schematic diagram of the structure of a discharge circuit provided in an embodiment of the present application;

[0017] Figure 5 The second structural diagram of an NMOS tube parallel drive circuit provided in an embodiment of the present application;

[0018] Figure 6 A schematic diagram of the structure of a battery management system provided in an embodiment of the present application.

[0019] Explanation of the main component symbols: 1-battery management system; 10-NMOS tube parallel drive circuit; 20-NMOS tube parallel switch circuit; 100-level control circuit; 200-voltage stabilizing and current expanding drive circuit; 300-discharge circuit; 110-low-end control circuit; 120-high-end switch circuit; R7-seventh resistor; R8-eighth resistor; Q3-third transistor; R2-second resistor; R4-fourth resistor; Q2-second transistor; Q1-first transistor; R1-first resistor; Z1-voltage zener diode; R3-third resistor; R11-eleventh resistor; D1-first diode; Q4-fourth transistor; Q5-fifth transistor; R5-fifth resistor; R9-ninth resistor. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0022] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0023] It is worth noting that before the present application was proposed, there were two common BMS driving solutions in the prior art, namely, the analog front-end (Analog Front-End, AFE) sampling chip driving solution and the MOS tube driving chip solution.

[0024] Among them, for the AFE sampling chip driving solution, that is, using the port of the analog front-end sampling chip to directly connect to the G pole of the MOS tube, the driving voltage, current and driving logic are all determined by the chip. The chip of this solution has its own driving output, which is simple and cost-saving, and there is no driving voltage compatibility problem. However, due to the limited driving capability of the AFE chip, there are requirements and restrictions on the external load. If the AFE chip is used at this time, because the driving current is too small, the MOS tube will slow down when opening and closing and stay on the Miller platform for a longer time, which will produce greater losses and cause the MOS junction temperature to be too high and burn out. At the same time, the AFE chip's own drive is its own hardware control, and its control logic is determined by the chip. For some systems that require the addition of a microcontroller (Micro-Controller Unit, MCU) as a secondary judgment strategy BMS, this function cannot be realized. In general, this solution has the defects of small current driving ability and incompatibility with unified strategies, and cannot meet the application of large current and multi-strategy BMS systems.

[0025] For the MOS tube driver chip solution, although high current drive can be achieved, when the BMS system is within the chip range, it can be powered directly from the system voltage. However, when the BMS system voltage is higher than the maximum supported voltage of the chip, a separate power supply needs to be designed. Therefore, it cannot be directly applied to higher BMS systems. Adding a power supply may also bring electromagnetic compatibility (EMC) problems. In addition, the cost of the driver chip and low dropout linear regulator (LowDrop-Out, LDO) is relatively high, which is not conducive to cost control.

[0026] In response to the above problems, the embodiments of the present application relate to an NMOS tube parallel drive circuit, a battery management system and a battery pack. The NMOS tube parallel drive circuit includes a level control circuit, a voltage stabilizing and current expanding drive circuit and a discharge and bleed circuit. The level control circuit is used to control the connection or disconnection between the BMS battery terminal and the voltage stabilizing and current expanding drive circuit; the voltage stabilizing and current expanding drive circuit is used to obtain a stable driving power supply from the BMS battery terminal, and amplify the output current of the BMS battery terminal and transmit it to the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned on; the discharge and bleed circuit is used to quickly discharge the charge between the gate and source of each NMOS tube in the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned off. In this way, the present application can realize the functions of driving voltage stabilization, current expansion, etc. to prevent NMOS tube explosion, and can be compatible with BMS systems of different voltage levels.

[0027] To facilitate the understanding of the present application, the technical solution provided by the present application is described in detail below in conjunction with specific embodiments.

[0028] Figure 1 This is one of the structural diagrams of an NMOS tube parallel drive circuit 10 provided in an embodiment of the present application. Figure 1 As shown, the NMOS tube parallel drive circuit 10 includes a level control circuit 100, a voltage-stabilizing and current-expanding drive circuit 200, and a bleed-discharge circuit 300; the level control circuit 100 is electrically connected to the BMS battery terminal and the voltage-stabilizing and current-expanding drive circuit 200, respectively, and the bleed-discharge circuit 300 is electrically connected to the voltage-stabilizing and current-expanding drive circuit 200 and the NMOS tube parallel switch circuit, respectively; wherein,

[0029] The level control circuit 100 is used to control the connection or disconnection between the BMS battery terminal and the voltage stabilizing and current expanding driving circuit 200 by receiving a level signal;

[0030] The voltage-stabilizing and current-expanding driving circuit 200 is used to obtain a stable driving power supply from the BMS battery terminal, and transmit the output current of the BMS battery terminal to each NMOS tube in the NMOS tube parallel switch circuit through the discharge circuit 300 after amplification, so that each NMOS tube is quickly turned on;

[0031] The discharge circuit 300 is used to quickly discharge the charge between the gate and the source of each NMOS tube in the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned off.

[0032] It should be noted that the BMS system is mainly responsible for monitoring the status of the battery, including battery voltage, current, temperature and other parameters to ensure the safe and efficient operation of the battery. In different battery application scenarios, you may encounter a variety of different voltage levels. For example, in electric vehicles, the voltage of the power battery pack may reach several hundred volts, while in some small energy storage devices, the battery pack voltage may only be a dozen volts.

[0033] Here, the BMS battery end mainly refers to the part where the BMS system is directly connected to the battery. It acts as a bridge connecting the BMS system and the battery, and can realize many functions such as monitoring various battery states and transmitting control signals.

[0034] It should also be noted that the level control circuit 100 provided in the embodiment of the present application is a circuit capable of adjusting, converting or controlling a level signal. The level control circuit 100 may be, for example, a transistor-transistor logic circuit (TTL). The TTL control circuit mainly uses TTL level signals to control the working state of other electronic components (such as transistors, MOS tubes, relays, etc.), thereby realizing various logical functions and practical applications.

[0035] In addition, the voltage-stabilizing and current-expanding driving circuit 200 provided in the embodiment of the present application mainly adjusts the input voltage through a voltage-stabilizing element (such as a voltage-stabilizing diode, a linear voltage regulator, a switching voltage regulator, etc.) to output a stable DC voltage. When the input voltage fluctuates or the load current changes, the voltage-stabilizing element can automatically adjust its internal working state to maintain the stability of the output voltage. Moreover, by adding a current-expanding element (such as a power transistor, a MOS tube, etc.) to expand the output current capacity of the circuit, the current-expanding function of the voltage-stabilizing and current-expanding driving circuit 200 is realized.

[0036] Furthermore, the discharge circuit 300 provided in the embodiment of the present application is a circuit for ensuring that the charge between the gate (G) and the source (S) of the NMOS tube can be quickly released when the NMOS tube is turned off.

[0037] In a specific implementation, the NMOS tube parallel drive circuit 10 provided in the embodiment of the present application is designed with current paths in two states. One path is that the level control circuit 100 first receives a high-level signal, and then the level control circuit 100 controls the BMS battery end to provide power for the voltage-stabilizing and current-expanding drive circuit 200, and amplifies the output current of the BMS battery end through the voltage-stabilizing and current-expanding drive circuit 200 and transmits it to the gate and source ends of each NMOS tube in the NMOS tube parallel switch circuit for charging, so that the NMOS tube is quickly turned on; the other path is that the level control circuit 100 receives a low-level signal, and then the level control circuit 100 controls the BMS battery end to be disconnected from the voltage-stabilizing and current-expanding drive circuit 200, and the discharge circuit 300 quickly discharges the charge between the gate and source of each NMOS tube in the NMOS tube parallel switch circuit, so that the NMOS tube is quickly turned off. Here, the embodiment of the present application can realize the rapid opening and closing of each NMOS tube in the NMOS tube parallel switch circuit through the voltage stabilizing and current expanding driving circuit 200 and the discharge circuit 300, which can prevent the NMOS tube explosion problem from occurring and improve the stability of the BMS system.

[0038] In addition, the voltage-stabilizing and current-expanding driving circuit 200 provided in the embodiment of the present application also has a voltage-stabilizing function, which can provide a power supply with strong voltage-stabilizing, load-carrying and anti-interference capabilities for NMOS tube driving, and can be compatible with BMS systems of different voltage levels through the voltage-stabilizing function.

[0039] In a possible implementation, the following provides for the implementation of this application: Figure 1 A possible circuit structure of the level control circuit 100 is illustrated by way of example. Figure 2 1 is a schematic diagram of a level control circuit 100 provided in an embodiment of the present application. Figure 2 As shown, the level control circuit 100 includes a low-end control circuit 110 and a high-end switch circuit 120, wherein a first end of the low-end control circuit 110 is electrically connected to a microcontroller, a second end of the low-end control circuit 110 is electrically connected to a first end of the high-end switch circuit 120, and a third end of the low-end control circuit 110 is grounded; a second end of the high-end switch circuit 120 is electrically connected to a BMS battery terminal; and a third end of the high-end switch circuit 120 is electrically connected to a voltage-stabilizing and current-expanding drive circuit 200;

[0040] Among them, when the microcontroller outputs a high-level signal, the low-end control circuit 110 controls the high-end switch circuit 120 to transmit the BMS battery end to the voltage-stabilizing and current-expanding drive circuit 200; when the microcontroller outputs a low-level signal, the low-end control circuit 110 controls the high-end switch circuit 120 to cut off the connection between the BMS battery end and the voltage-stabilizing and current-expanding drive circuit 200. Figure 2 "B+" is the positive electrode of the BMS battery terminal.

[0041] In a specific implementation, the level control circuit 100 in the embodiment of the present application is connected to the microcontroller, the BMS battery terminal and the voltage-stabilizing and current-expanding driving circuit 200 to control whether the battery energy is delivered to the voltage-stabilizing and current-expanding driving circuit 200. The high / low level signal output by the MCU determines the on / off between the BMS battery terminal and the voltage-stabilizing and current-expanding driving circuit 200 through the low-end control circuit 110 and the high-end switch circuit 120 in the level control circuit 100.

[0042] Here, the level control circuit 100 in the embodiment of the present application is connected to the MCU. Since the level signal is output by the MCU, the MCU can make a decision to control whether the NMOS tube is turned on and off. In this way, even when the BMS system is connected to other devices, such as when it is connected to an inverter or EMS system, it is necessary to read the feedback information of the external device before making a decision to decide whether to turn on or off the MOS tube. The MCU can also make an execution action according to the actual working conditions to control the NMOS tube parallel drive circuit 10. In this way, the embodiment of the present application realizes the participation of the MCU in the control logic of the BMS system, avoids misjudgment, and enhances the safety of the BMS system.

[0043] Among them, the low-end control circuit 110 is responsible for receiving the level signal output by the MCU. When the MCU outputs a high-level signal, the low-end control circuit 110 is activated, and it will generate a control signal to drive the high-end switch circuit 120 to turn on; when the MCU outputs a low-level signal, the low-end control circuit 110 will turn off the high-end switch circuit 120. The high-end switch circuit 120 is used to control the connection between the BMS battery terminal and the voltage-stabilizing and current-expanding drive circuit 200. When activated by the low-end control circuit 110 (MCU outputs a high level), the high-end switch circuit 120 is turned on, and the electric energy at the battery terminal can be smoothly transmitted to the voltage-stabilizing and current-expanding drive circuit 200; when not activated by the low-end control circuit 110 (MCU outputs a low level), the high-end switch circuit 120 is in the off state. This off state effectively prevents the battery energy from being transmitted to the voltage-stabilizing and current-expanding drive circuit 200 when it is not needed, and plays a role in isolation and protection.

[0044] In a possible implementation, the following Figure 2 A possible circuit structure of the low-end control circuit 110 is illustrated as follows: Figure 2 As shown, the low-end control circuit 110 includes a seventh resistor R7, an eighth resistor R8 and a third transistor Q3; the first end of the seventh resistor R7 is electrically connected to the microcontroller, the second end of the seventh resistor R7 is electrically connected to the first end of the eighth resistor R8 and the base of the third transistor Q3 respectively, the second end of the eighth resistor R8 and the emitter of the third transistor Q3 are both grounded, and the collector of the third transistor Q3 is electrically connected to the first end of the high-end switch circuit 120; wherein the third transistor Q3 is of NPN type.

[0045] In a specific implementation, the low-end control circuit 110 includes a seventh resistor R7, an eighth resistor R8 and a third transistor Q3. When the MCU outputs a high-level signal, the base of the third transistor Q3 obtains sufficient forward bias current, and the third transistor Q3 is turned on, thereby outputting a suitable level to control the high-end switch circuit 120; when the MCU outputs a low-level signal, when the third transistor Q3 is used as a low-end control element, the low-level signal causes the third transistor Q3 to be cut off, and no driving signal is output to the high-end switch circuit 120, thereby achieving shutdown.

[0046] In a possible implementation, the following Figure 2 A possible circuit structure of the high-end switch circuit 120 is illustrated as an example. Figure 2 As shown, the high-end switch circuit 120 includes a second resistor R2, a fourth resistor R4 and a second transistor Q2, the first end of the fourth resistor R4 is electrically connected to the second end of the low-end control circuit 110, the second end of the fourth resistor R4 is electrically connected to the first end of the second resistor R2 and the base of the second transistor Q2, respectively, the second end of the second resistor R2 is electrically connected to the BMS battery end and the emitter of the second transistor Q2, and the collector of the second transistor Q2 is electrically connected to the voltage stabilizing and current expanding driving circuit 200; wherein, the second transistor Q2 is a PNP type.

[0047] In a specific implementation, the high-end switch circuit 120 includes a second resistor R2, a fourth resistor R4, and a second transistor Q2. When the MCU outputs a high-level signal, when the NPN transistor in the low-end control circuit 110 is turned on, the base voltage of the PNP transistor in the high-end switch circuit 120 drops. Since the characteristic of the PNP second transistor Q2 is that it is turned on when the base voltage is lower than the emitter voltage, at this time, the base voltage of the PNP second transistor Q2 in the high-end switch circuit 120 drops to meet the turn-on condition, so the second transistor Q2 is turned on. In this way, the connection between the BMS battery terminal and the voltage-stabilizing and current-expanding driving circuit 200 is connected, and the current at the battery terminal can flow to the voltage-stabilizing and current-expanding driving circuit 200 through the turned-on second transistor Q2.

[0048] In addition, when the MCU outputs a low-level signal, since the third transistor Q3 in the low-end control circuit 110 is turned off, there is no voltage drop on the fourth resistor R4 connected to the high-end switch circuit 120, and the base voltage of the second transistor Q2 in the high-end switch circuit 120 is maintained at a high level (close to the BMS battery terminal voltage). At this time, the second transistor Q2 does not meet the conduction condition and is in a cut-off state. In this way, the connection between the BMS battery terminal and the voltage-stabilizing and current-expanding driving circuit 200 is cut off, and the battery current cannot flow to the voltage-stabilizing and current-expanding driving circuit 200 through the high-end switch circuit 120.

[0049] Here, if Figure 2 As shown, the level control circuit 100 includes a low-end control circuit 110 and a high-end switch circuit 120, the low-end control circuit 110 includes a seventh resistor R7, an eighth resistor R8 and a third transistor Q3, the high-end switch circuit 120 includes a second resistor R2, a fourth resistor R4 and a second transistor Q2, wherein the collector of the third transistor Q3 in the low-end control circuit 110 is electrically connected to the first end of the fourth resistor R4 in the high-end switch circuit 120. Here, in order to prevent the second transistor Q2 and the third transistor Q3 from being broken down due to the high voltage level of the BMS system, the selection of the second transistor Q2 and the third transistor Q3 in the embodiment of the present application needs to be determined according to the voltage level of the BMS system.

[0050] Figure 2 The level control circuit 100 in the circuit is a TTL control circuit. The level control circuit 100 adopts a combination of NPN and PNP transistors to realize the function of low-voltage control of high-end switches. In addition, the level control circuit 100 can be compatible with a variety of low-voltage control end system voltages, such as 3.3V, 5V, and other MCU system voltages; on the other hand, it can directly obtain power from the BMS battery end, and can also be compatible with BMS systems of different voltages at the power supply end, such as 12V, 25V, 48V, 72V, and other BMS system voltages, and can be applied to energy storage BMS, automotive BMS, outdoor portable BMS, and other occasions.

[0051] Below Figure 2 The working process of the medium level control circuit 100 is described. Specifically, when the MCU outputs a high level signal, the third transistor Q3 is turned on, and the base of the second transistor Q2 is connected to a low voltage V between the base and the emitter through the fourth resistor R4. be , so that the second transistor Q2 is turned on to send the power of the BMS battery end to the rear-end voltage stabilizing and current expanding driving circuit 200; when the MCU outputs a low-level signal, the third transistor Q3 is turned off, and due to the pull-up effect of the second resistor R2, the voltage V between the base and the emitter of the second transistor Q2 be is 0, the second transistor Q2 is turned off, and this process realizes switch control.

[0052] In a possible implementation, the following provides for the implementation of this application: Figure 1 A possible circuit structure of the voltage-stabilizing and current-expanding driving circuit 200 is illustrated by way of example. Figure 3 A schematic diagram of a voltage-stabilizing and current-expanding driving circuit 200 provided in an embodiment of the present application is shown in FIG. Figure 3As shown, the voltage-stabilizing and current-expanding driving circuit 200 includes a voltage-stabilizing circuit and a first transistor Q1. The voltage-stabilizing circuit includes a first resistor R1 and a voltage-stabilizing diode Z1. The first end of the first resistor R1 is electrically connected to the level control circuit 100, and the second end of the first resistor R1 is electrically connected to the cathode of the voltage-stabilizing diode Z1 and the base of the first transistor Q1, respectively. The anode of the voltage-stabilizing diode Z1 is grounded, the emitter of the first transistor Q1 is electrically connected to the discharge circuit 300, and the collector of the first transistor Q1 is electrically connected to the BMS battery terminal, wherein the first transistor Q1 is of NPN type.

[0053] It should be noted that the voltage-stabilizing and current-expanding driving circuit 200 provided in the embodiment of the present application includes a voltage-stabilizing circuit, which is composed of a first resistor R1 and a voltage-stabilizing diode Z1. A voltage-stabilizing power supply can be obtained by connecting the first resistor R1 and the voltage-stabilizing diode Z1 in series. Moreover, by changing the resistance value of the first resistor R1, a stable driving power supply can be obtained under a BMS system of different voltage levels, that is, by changing the resistance value, a driving voltage of any voltage level can be achieved.

[0054] In addition, the voltage-stabilizing and current-expanding driving circuit 200 of the embodiment of the present application also uses the voltage-stabilizing diode Z1 and the first transistor Q1 to form a voltage follower as a driving power supply. Due to the voltage-stabilizing characteristics of the voltage-stabilizing diode Z1 and the following characteristics of the voltage follower, the circuit has the ability to stabilize voltage, amplify current, and resist interference. It can provide a driving power supply with voltage-stabilizing, load-carrying and anti-interference capabilities for the NMOS tube driver, which can realize the rapid opening of the NMOS tube and reduce the opening loss.

[0055] In a specific implementation, when the MCU outputs a high-level signal, the level control circuit 100 controls the voltage-stabilizing and current-expanding driving circuit 200 to be in a working state, and the voltage-stabilizing and current-expanding driving circuit 200 supplies power to the subsequent-stage discharge and leakage circuit 300. The voltage-stabilizing and current-expanding driving circuit 200 supplies the amplified current to each NMOS tube in the NMOS tube parallel switch circuit through the discharge and leakage circuit 300, so that the GS voltage of each NMOS tube rises rapidly, and the NMOS tube Miller platform is transitioned in the shortest possible time, so that the NMOS tube is turned on in a shorter us level time.

[0056] Below Figure 3 The working process of the voltage-stabilizing and current-expanding driving circuit 200 in the embodiment is described by way of example. Specifically, if a 12V voltage is generated across the voltage-stabilizing diode Z1, the first transistor Q1 and the voltage-stabilizing diode Z1 form a voltage follower, which plays a role in voltage following and current amplification. When the second transistor Q2 in the level control circuit 100 is turned off, the first transistor Q1 is triggered to be turned off. Since the voltage follower generates a voltage of V0=12V-V be, the first transistor Q1 is about 0.6V, so the final driving voltage of the NMOS tube is 11.4V, which has met the NMOS driving voltage condition and can make the NMOS turn on normally and quickly. In addition, the output current of the first transistor Q1 is I c ≈β×I b , realizing the current amplification function, the resistance value of the first resistor R1 is adjusted according to the BMS system voltage, and the voltage zener diode Z1 should be guaranteed to obtain a normal working current of 1mA. When selecting the first transistor Q1, try to choose a larger β multiple to obtain a larger driving current.

[0057] In a possible implementation, the following provides for the implementation of this application: Figure 1 A possible circuit structure of the discharge circuit 300 is illustrated by way of example. Figure 4 FIG. 3 is a schematic diagram of a discharge circuit 300 provided in an embodiment of the present application. Figure 4 As shown, the bleeding and discharging circuit 300 includes an eleventh resistor R11, a first diode D1 and a fourth transistor Q4; wherein, the anode of the first diode D1 is electrically connected to the voltage stabilizing and current expanding driving circuit 200, the first end of the eleventh resistor R11, and the base of the fourth transistor Q4, respectively, the cathode of the first diode D1 is electrically connected to the emitter of the fourth transistor Q4 and the NMOS tube parallel switch circuit, the collector of the fourth transistor Q4 and the second end of the eleventh resistor R11 are both grounded, and the fourth transistor Q4 is a PNP type.

[0058] In a specific implementation, when the voltage-stabilizing and current-expanding driving circuit 200 is in a working state, the voltage across the first diode D1 in the discharge and bleeding circuit 300 is positive on the left and negative on the right, the circuit formed by the eleventh resistor R11 and the fourth transistor Q4 does not work, and the current output by the voltage-stabilizing and current-expanding driving circuit 200 flows into the NMOS tube parallel switch circuit through the first diode D1, so that the NMOS tube is quickly turned on. When the voltage-stabilizing and current-expanding driving circuit 200 is turned off, due to the reverse cutoff characteristic of the first diode D1 in the discharge and bleeding circuit 300, the charge stored in the NMOS tube has no path to be released. At the same time, because the first diode D1 loses the power supply, the anode of the first diode D1 and the base of the fourth transistor Q4 are pulled down by the first resistor R1, generating I b Current, V of the fourth transistor Q4 E >V B , the fourth transistor Q4 meets the transistor conduction condition, so that the circuit composed of the eleventh resistor R11 and the fourth transistor Q4 works, so that the charge of the NMOS tube GS flows quickly through the fourth transistor Q4 and is discharged quickly.

[0059] It should be noted that the discharge and bleeding circuit 300 provided in the embodiment of the present application utilizes the reverse characteristics of the diode to cleverly avoid the charging and discharging loops without generating conflicts, and utilizes the amplification circuit to realize the amplification capability to quickly discharge the GS charge of the NMOS tube to realize the rapid shutdown of the NMOS tube. In this way, the switching loss can be effectively reduced to prevent the NMOS tube from burning due to excessive junction temperature.

[0060] In a possible embodiment, a possible specific circuit structure of the NMOS tube parallel driving circuit 10 provided in the implementation of the present application is illustrated below. Figure 5 This is a second structural diagram of an NMOS tube parallel drive circuit 10 provided in an embodiment of the present application. Figure 5 As shown, the NMOS tube parallel driving circuit 10 includes a level control circuit 100, a voltage stabilizing and current expanding driving circuit 200 and a discharge circuit 300, and the NMOS tube parallel driving circuit 10 is connected to the NMOS tube parallel switch circuit. Here, Figure 5 The level control circuit 100 and Figure 2 The structure of the level control circuit 100 is the same as that of the level control circuit 100 described in the specification.

[0061] in addition, Figure 5 Compared with the voltage stabilizing and current expanding driving circuit 200 Figure 3 The voltage-stabilizing and current-expanding driving circuit 200 described in the embodiment of the present invention adds a third resistor R3. Specifically, Figure 5 The third resistor R3 in the voltage-stabilizing and current-expanding driving circuit 200 shown is connected in parallel with the voltage-stabilizing diode Z1. When the second transistor Q2 in the level control circuit 100 is turned off, a discharge path is provided for the base of the first transistor Q1 and the voltage-stabilizing diode Z1 to discharge the charge of the junction capacitance of the voltage-stabilizing diode Z1, so as to achieve the purpose of quickly turning off the first transistor Q1. Among them, the third resistor R3 is a pull-down resistor. The resistance value of the third resistor R3 cannot be too large when selected, which will affect the speed of the NMOS tube to discharge the charge. The resistance value of the third resistor R3 cannot be too small when selected, which will generate power consumption. Therefore, the resistance value selection of the third resistor R3 mainly depends on the actual demand for the NMOS tube turn-off speed, wherein the NMOS tube turn-off speed is usually at the nanosecond (ns) to microsecond (us) level.

[0062] here, Figure 5 Compared with the 300 Figure 4 The discharge circuit 300 is further provided with a fifth transistor Q5, a fifth resistor R5 and a ninth resistor R9. Figure 5The discharge circuit 300 shown includes a P-type Darlington amplifier circuit, a first diode D1, a fifth resistor R5 and a ninth resistor R9, wherein the P-type Darlington amplifier circuit includes an eleventh resistor R11, a fourth transistor Q4 and a fifth transistor Q5; wherein the anode of the first diode D1 is electrically connected to the voltage-stabilizing and current-expanding driving circuit 200, the first end of the eleventh resistor R11 and the base of the fifth transistor Q5, respectively, and the cathode of the first diode D1 is electrically connected to the emitter of the fourth transistor Q4. , the first end of the fifth resistor R5 and the first end of the ninth resistor R9 are electrically connected, the base of the fourth triode Q4 is electrically connected to the emitter of the fifth triode Q5, the collector of the fourth triode Q4, the collector of the fifth triode Q5, and the second end of the eleventh resistor R11 are all grounded, the second end of the fifth resistor R5 and the second section of the ninth resistor R9 are respectively electrically connected to the NMOS tube parallel switch circuit, and the fourth triode Q4 and the fifth triode Q5 are both PNP type. Figure 5 It also includes a partial NMOS tube parallel switch circuit, where the NMOS tube parallel switch circuit is composed of at least two NMOS tubes in parallel, and each NMOS tube is connected to a resistor in the discharge circuit 300 .

[0063] The following are mainly Figure 5 The working process of the discharge circuit 300 in the embodiment is described as follows. Here, the eleventh resistor R11, the fourth transistor Q4, and the fifth transistor Q5 constitute a P-type Darlington amplifier circuit. When the voltage-stabilizing and current-expanding driving circuit 200 is in the working state, the voltage across the first diode D1 is positive on the left and negative on the right, and the P-type Darlington circuit does not work; when the voltage-stabilizing and current-expanding driving circuit 200 is turned off, due to the reverse cutoff characteristic of the first diode D1, the charge stored in the NMOS tube has no path to be released. At the same time, since the first diode D1 loses the power supply, the anode of the first diode D1 and the base of the fifth transistor Q5 are pulled down by the eleventh resistor R11, generating I b Current, V of the fifth transistor Q5 and the fourth transistor Q4 E >V B , the fifth transistor Q5 and the fourth transistor Q4 both meet the transistor conduction conditions, so that the P-type Darlington circuit works, so that the charge of the NMOS tube GS flows quickly through the fifth resistor R5 and the ninth resistor R9 through the fourth transistor Q4 and the fifth transistor Q5 and is discharged quickly. The discharge circuit 300 cleverly avoids the charging and discharging loops by using the reverse characteristics of the diode, and does not generate conflicts. The P-type Darlington composite amplifier circuit is used to achieve β×β high-multiple amplification capability to quickly discharge the GS charge. Among them, changing the resistance value of the eleventh resistor R11 can adjust the discharge speed. In order to prevent ringing during driving, the gate resistor of the NMOS is set, such as the fifth resistor R5 and the ninth resistor R9. The resistance values ​​of the fifth resistor R5 and the ninth resistor R9 can be between 10-100 ohms.

[0064] in addition, Figure 5 The P-type Darlington amplifier circuit includes two PNP-type transistors. In practical applications, more than two PNP-type transistors can be set in the P-type Darlington amplifier circuit, and the number of PNP-type transistors mainly depends on the discharge speed requirement of the NMOS tube charge.

[0065] The following are mainly Figure 5 The overall working process of the NMOS tube parallel driving circuit 10 in the embodiment is briefly described. One working state is the conduction path of the NMOS tube. Specifically, when the MCU outputs a high-level signal, the third transistor Q3 and the second transistor Q2 in the level control circuit 100 are turned on, so that the first transistor Q1 in the voltage-stabilizing and current-expanding driving circuit 200 is turned on. The voltage-stabilizing and current-expanding driving circuit 200 is in a working state, and can provide a stable driving voltage for the NMOS tube to be turned on, and the driving current after the current expansion through the first transistor Q1 flows into the NMOS tube parallel switch circuit through the first diode D1 and the fifth resistor R5 / the ninth resistor R9 in the discharge circuit 300 to charge the NMOS tube GS, so that the GS voltage rises rapidly, and the NMOS tube Miller platform is transitioned as short as possible, so as to realize the NMOS tube being turned on in a relatively short us level time. Another working state is the off path of the NMOS tube. Specifically, when the MCU outputs a low-level signal, the third transistor Q3 and the second transistor Q2 in the level control circuit 100 are turned off, so that the first diode D1 in the voltage-stabilizing and current-expanding driving circuit 200 is turned off, and the voltage-stabilizing and current-expanding driving circuit 200 stops working. The voltage-stabilizing and current-expanding driving circuit 200 stops providing power to the discharge circuit 300, and the charge of each NMOS tube in the NMOS tube parallel switch circuit is discharged through the fifth resistor R5 / ninth resistor R9 in the discharge circuit 300 and the P-type Darlington amplifier circuit, so that the NMOS tube can be quickly turned off. In this way, the switching loss can be effectively reduced to prevent the NMOS tube from burning due to excessive junction temperature.

[0066] It should be noted that NMOS tubes are very critical power devices in BMS systems. Under high current demand conditions, NMOS tubes must be connected in parallel to achieve high current passing capacity. NMOS tubes have the Miller effect during the opening or closing process, which is an unfavorable factor. The more NMOS tubes are connected in parallel, the more serious the Miller effect. If the NMOS drive circuit is improperly designed, there may be excessive switching losses during the opening and closing process, resulting in excessive NMOS junction temperature and tube explosion. Therefore, the NMOS parallel drive circuit must ensure stability, safety and reliability. The designed circuit must have appropriate voltage and current to achieve the purpose of quickly opening and closing the NMOS tube, ensuring that the NMOS tube does not heat up and burn out due to switching losses. At the same time, the drive circuit should be compatible with power supply BMS systems and MCU control systems of different voltages.

[0067] The NMOS tube parallel drive circuit 10 provided in the embodiment of the present application is designed to solve the above-mentioned problems of the BMS system, and solves the power supply voltage compatibility problem caused by NMOS drive in the BMS system design, the control strategy incompatibility and the tube burning problem caused by insufficient drive current. At the same time, the circuit has the advantage of low cost, which is conducive to mass production. It can be applied to energy storage BMS, vehicle BMS, outdoor portable BMS and other occasions.

[0068] It should also be noted that the level control circuit 100, the voltage stabilizing and current expanding driving circuit 200, and the discharge circuit 300 in the NMOS tube parallel driving circuit 10 provided in the embodiment of the present application are all composed of common discrete components, such as resistors, diodes, transistors and other conventional components. The components are highly versatile and have high utilization rates, which is conducive to reducing component procurement costs. Moreover, each partial circuit can adjust and change one of the component parameters to obtain the corresponding function or parameter index. The circuit scheme can be used as a reference to derive other versions of the scheme circuit according to actual application requirements.

[0069] Figure 6 This is a schematic diagram of the structure of a battery management system 1 provided in an embodiment of the present application. Figure 6 As shown, the battery management system 1 includes an NMOS tube parallel switch circuit 20 and Figure 1 or Figure 5 The NMOS tube parallel driving circuit 10.

[0070] In addition, the NMOS tube parallel driving circuit 10 is electrically connected to the NMOS tube parallel switch circuit 20, the BMS battery terminal, and the microcontroller respectively.

[0071] Here, the BMS system includes an NMOS tube parallel switch circuit and an NMOS tube parallel drive circuit 10. The NMOS tube parallel drive circuit mainly controls the gate voltage of multiple parallel NMOS tubes to make them turn on or off at the same time, thereby realizing the on-off control or current regulation of the battery charging and discharging circuit. For example, when the battery needs to be charged, the drive circuit will output a suitable high-level signal to the gate of the NMOS tube, turning on the NMOS tube and allowing the charging current to pass; when the charging is completed or an abnormal situation occurs, the drive circuit outputs a low level to turn off the NMOS tube and cut off the charging circuit. The NMOS tube parallel switch circuit mainly plays the role of a switch in the BMS system, and the connection or disconnection of the battery and the external circuit is realized by controlling the conduction and cutoff of the NMOS tube. When the NMOS tube is turned on, the battery is connected to an external circuit such as a load or a charger to perform charging and discharging operations; when the NMOS tube is turned off, the battery is disconnected from the external circuit, which plays the role of isolation and protection.

[0072] In addition, power devices in the BMS system, such as NMOS tubes, need to be able to adapt to these different voltage environments, and in some cases, in order to meet the driving requirements of large currents, multiple NMOS tubes are connected in parallel, corresponding to the NMOS tube parallel switch circuit in the embodiment of the present application, and the NMOS tube parallel switch circuit includes multiple NMOS tubes connected in parallel. In BMS systems with different voltages, the NMOS tube parallel drive circuit 10 also needs to be reasonably designed to ensure that the NMOS tube can be turned on and off normally under different voltages. In this regard, the present application Figure 5 The specific circuit structure of the NMOS tube parallel driving circuit 10 is given in FIG.

[0073] Here, the embodiment of the present application also provides a battery pack, which includes a battery cell module and Figure 6 The battery management system 1.

[0074] It should be noted that, in the absence of conflict, the features in the embodiments of this application may be combined with each other.

[0075] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An NMOS tube parallel driving circuit, characterized in that: The NMOS tube parallel drive circuit includes a level control circuit, a voltage stabilizing current expansion drive circuit and a discharge circuit; the level control circuit is electrically connected to the BMS battery terminal and the voltage stabilizing current expansion drive circuit respectively, and the discharge circuit is electrically connected to the voltage stabilizing current expansion drive circuit and the NMOS tube parallel switch circuit respectively; wherein, The level control circuit is used to control the connection or disconnection between the BMS battery terminal and the voltage stabilizing and current expanding driving circuit by receiving a level signal; The voltage-stabilizing and current-expanding driving circuit is used to obtain a stable driving power supply from the BMS battery terminal, and transmit the output current of the BMS battery terminal to each NMOS tube in the NMOS tube parallel switch circuit through the discharge circuit after amplification, so that each NMOS tube is quickly turned on; The discharge circuit is used to quickly discharge the charge between the gate and the source of each NMOS tube in the NMOS tube parallel switch circuit, so that each NMOS tube is quickly turned off.

2. The circuit according to claim 1, characterized in that The level control circuit includes a low-end control circuit and a high-end switch circuit, wherein the first end of the low-end control circuit is electrically connected to the microcontroller, the second end of the low-end control circuit is electrically connected to the first end of the high-end switch circuit, and the third end of the low-end control circuit is grounded; the second end of the high-end switch circuit is electrically connected to the BMS battery end; the third end of the high-end switch circuit is electrically connected to the voltage stabilization and current expansion drive circuit; Among them, when the microcontroller outputs a high-level signal, the low-end control circuit controls the high-end switch circuit to transmit the BMS battery end to the voltage-stabilizing and current-expanding drive circuit; when the microcontroller outputs a low-level signal, the low-end control circuit controls the high-end switch circuit to cut off the connection between the BMS battery end and the voltage-stabilizing and current-expanding drive circuit.

3. The circuit according to claim 2, characterized in that The low-end control circuit includes a seventh resistor, an eighth resistor and a third transistor; the first end of the seventh resistor is electrically connected to the microcontroller, the second end of the seventh resistor is electrically connected to the first end of the eighth resistor and the base of the third transistor respectively, the second end of the eighth resistor and the emitter of the third transistor are both grounded, and the collector of the third transistor is electrically connected to the first end of the high-end switching circuit; wherein the third transistor is of NPN type.

4. The circuit according to claim 2, characterized in that The high-end switch circuit includes a second resistor, a fourth resistor and a second transistor, the first end of the fourth resistor is electrically connected to the second end of the low-end control circuit, the second end of the fourth resistor is electrically connected to the first end of the second resistor and the base of the second transistor respectively, the second end of the second resistor is electrically connected to the BMS battery end and the emitter of the second transistor respectively, and the collector of the second transistor is electrically connected to the voltage stabilizing and current expanding drive circuit; wherein the second transistor is a PNP type.

5. The circuit according to claim 1, characterized in that The voltage-stabilizing and current-expanding driving circuit includes a voltage-stabilizing circuit and a first transistor. The voltage-stabilizing circuit includes a first resistor and a voltage-stabilizing diode. The first end of the first resistor is electrically connected to the level control circuit, the second end of the first resistor is electrically connected to the cathode of the voltage-stabilizing diode and the base of the first transistor respectively, the anode of the voltage-stabilizing diode is grounded, the emitter of the first transistor is electrically connected to the discharge circuit, and the collector of the first transistor is electrically connected to the BMS battery terminal, wherein the first transistor is an NPN type.

6. The circuit according to claim 5, characterized in that The voltage-stabilizing and current-expanding driving circuit further includes a third resistor, and the third resistor is connected in parallel with the voltage-stabilizing diode.

7. The circuit according to claim 1, characterized in that The discharge circuit includes an eleventh resistor, a first diode and a fourth transistor; wherein the anode of the first diode is electrically connected to the voltage stabilizing and current expanding driving circuit, the first end of the eleventh resistor, and the base of the fourth transistor, respectively, the cathode of the first diode is electrically connected to the emitter of the fourth transistor and the NMOS tube parallel switch circuit, respectively, the collector of the fourth transistor and the second end of the eleventh resistor are both grounded, and the fourth transistor is a PNP type.

8. The circuit according to claim 1, characterized in that The discharge circuit includes a P-type Darlington amplifier circuit, a first diode, a fifth resistor and a ninth resistor, and the P-type Darlington amplifier circuit includes an eleventh resistor, a fourth transistor and a fifth transistor; wherein the anode of the first diode is electrically connected to the voltage stabilizing and current expanding driving circuit, the first end of the eleventh resistor and the base of the fifth transistor respectively, the cathode of the first diode is electrically connected to the emitter of the fourth transistor, the first end of the fifth resistor and the first end of the ninth resistor respectively, the base of the fourth transistor is electrically connected to the emitter of the fifth transistor, the collector of the fourth transistor, the collector of the fifth transistor and the second end of the eleventh resistor are all grounded, the second end of the fifth resistor and the second section of the ninth resistor are electrically connected to the NMOS tube parallel switch circuit respectively, and the fourth transistor and the fifth transistor are both PNP type.

9. A battery management system, characterized in that: The battery management system comprises an NMOS tube parallel switch circuit and an NMOS tube parallel drive circuit as described in any one of claims 1 to 8, and the NMOS tube parallel drive circuit is electrically connected to the NMOS tube parallel switch circuit, the BMS battery terminal, and the microcontroller respectively.

10. A battery pack, characterized in that: The battery pack comprises a battery cell module and a battery management system according to claim 9.

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