Printed circuit board and manufacturing method thereof

Abstract

The invention relates to a printed circuit board and a manufacturing method thereof. A printed wiring board according to the present invention is configured to include: a substrate including first to n-th layers stacked in a layered shape; a via hole formed through a layer including the first layer or the nth layer in a stacking direction; plating layers formed inside and outside the via holes; and a pad formed by separating the plating layer formed at the end of the via hole from the periphery. Consequently, the conduction path can be formed on one side of the bonding pad in the stacking direction to improve the component density, and thus the size of the substrate can be reduced.

Description

Technical Field

[0001] The invention relates to a printed circuit board and a manufacturing method thereof. Background Art

[0002] As is known to all, a printed circuit board or printed circuit board (PCB) has a structure of stacked conductors and insulators, and is equipped with various components such as semiconductors, capacitors and resistors.

[0003] Such printed circuit boards are also called single-sided PCB, double-sided PCB, 4-layer PCB, 6-layer PCB, and (n*2)-layer PCB according to the number of circuit layers.

[0004] Typically, computer motherboards use 6-layer PCBs, graphics cards and the like use 8-layer PCBs or 10-layer PCBs, and network equipment can also use dozens of layers of PCBs.

[0005] The substrate of a printed circuit board except the conductor (circuit) is composed of an insulator, and such a substrate is usually composed of multiple layers of glass fiber and epoxy plastic impregnation resin (PREPREG, PP).

[0006] On the other hand, vias are provided to electrically connect circuits (layers) of different layers stacked with the insulator 110I interposed therebetween.

[0007] The via is configured to include: a via hole formed through different layers (layered arrangement) with an insulator interposed therebetween; and a plated layer plated on the inner surface and both end surfaces of the via hole.

[0008] Thus, the circuit layers on both sides of the insulator are electrically connected.

[0009] However, according to this conventional printed circuit board and its manufacturing method, if a via is formed on the lower side of the component pad, there is a problem that an insulating material (PSR) is coated on the bottom surface and the upper end surface of the laminated substrate, and after the PCB washing process, washing liquid (acidic solution) remains inside the via hole, thereby causing cracks in the PCB due to corrosion.

[0010] In addition, if a via is formed on the lower side of the component pad, there is a problem: an insulator (PSR) is coated on the opposite side of the pad (for example, the bottom surface), and during surface mounting (SMT), the internal air of the via expands at a high temperature (for example, 245°C) and causes a cold solder defect.

[0011] Furthermore, if a via is formed under a component pad and the opposite side (eg, bottom surface) of the pad is opened, there is a problem that solder flows out to the bottom of the via at high temperature during surface mounting (SMT).

[0012] In view of such a problem, in a conventional printed circuit board and a method for manufacturing the same, a via is formed on one side separated from the lower side of a component pad in the board surface direction.

[0013] However, in this type of printed circuit board and its manufacturing method in which vias are formed at positions separated from the lower side of the component pads along the board surface direction, there is a problem of reduced component density per unit area of ​​the PCB because vias need to be formed separately at positions separated from the component pads along the board surface direction.

[0014] Therefore, there is a problem that the size of the PCB increases accordingly.

[0015] In addition, since a via is formed at a position spaced apart from the component pad along the board surface, a signal input to the component pad needs to move along the via spaced apart along the board surface, which increases the signal transmission path (length) accordingly.

[0016] Therefore, since the signal transmission path (length) becomes longer, the signal processing speed is correspondingly reduced, so there is a problem that there is a limit to improving product performance.

[0017] In view of such problems, some printed circuit boards and methods of manufacturing the same are using a method of forming a laser guide path on the lower side of a component pad using a laser.

[0018] However, in such a conventional printed circuit board having a laser guide path and a method for manufacturing the same, since expensive laser equipment is required, there is a problem that the manufacturing cost when manufacturing the printed circuit board increases significantly. Summary of the invention

[0019] Problems to be solved by the invention

[0020] Therefore, an object of the present invention is to provide a printed circuit board and a method for manufacturing the same, according to which a conductive path is formed on one side of a pad in a stacking direction, thereby being able to reduce the size of a substrate.

[0021] In addition, another object of the present invention is to provide a printed circuit board and a method for manufacturing the same. According to the printed circuit board and the method for manufacturing the same, the signal transmission path can be shortened and the signal processing speed can be increased.

[0022] In addition, another object of the present invention is to provide a printed circuit board and a method for manufacturing the same, according to which the density of components can be increased at a low cost.

[0023] Means for solving problems

[0024] The printed wiring board of the present invention for solving the above-mentioned problems is characterized in that a conductive path is formed on one side of a pad along a lamination direction.

[0025] Specifically, a via hole is provided that penetrates a substrate including a plurality of layers stacked in layers, the layers penetrated include the first layer at the bottom or the nth layer at the top, a plating layer composed of a conductor is formed inside and outside the via hole, and a pad is formed by separating the plating layer exposed on the outer surface from the surrounding area, thereby reducing the size of the printed circuit board.

[0026] In addition, a signal input from the pad is transmitted through the plating layer of the via hole, so that the signal transmission path can be shortened.

[0027] In addition, the signal processing speed can be increased.

[0028] The via hole is formed by drilling through it with a drill.

[0029] This can suppress an increase in manufacturing cost.

[0030] A printed circuit board according to one embodiment of the present invention includes: a substrate, including a first layer stacked in layers and arranged at the bottom along the stacking direction to an nth layer arranged at the top; a via hole formed by penetrating layers including the first layer or the nth layer along the stacking direction; a plating layer formed inside and outside the via hole; and a pad formed by separating the plating layer formed at the end of the via hole from the periphery.

[0031] Thus, by providing a conductive path on one side of the pad along the stacking direction, it is possible to increase the density of components.

[0032] Thereby, the size of the printed circuit board can be reduced.

[0033] In addition, the signal transmission path between the pad and the conductive path can be shortened, thereby improving the signal processing speed.

[0034] In one embodiment of the present invention, the via hole includes an n_n-1th via hole, and the n_n-1th via hole is formed by penetrating the nth layer and the n-1th layer.

[0035] The plating layer includes: an n_n-1th inner surface plating layer formed on the inner surface of the n_n-1th via hole; and an n_n-1th end plating layer formed on both ends of the n_n-1th via hole, respectively.

[0036] The pad is formed on the (n_n-1)th end plating layer of the (n_n-1)th end plating layer of the (n)th via hole that is exposed to the outside.

[0037] The n_n-1th filling portion is formed by filling an insulating material inside the n_n-1th inner surface plating layer and the n_n-1th end plating layer of the n_n-1th via hole.

[0038] As a result, the air layer inside the (n_n-1)th via hole is reduced (eliminated), so that cold welding defects caused by the expansion of air can be suppressed during surface mounting.

[0039] In addition, during surface mounting, since the n_n-1th via hole is blocked, it is possible to suppress leakage of solder through the n_n-1th via hole.

[0040] In one embodiment of the present invention, the via hole comprises a 2_1st via hole, and the 2_1st via hole is formed by penetrating the second layer and the first layer.

[0041] The plating layer includes: a 2_1 inner surface plating layer formed on the inner surface of the 2_1 via hole; and a 2_1 end plating layer formed on both ends of the 2_1 via hole, respectively.

[0042] The pad is formed on the 2_1 end plating layer of the 2_1 via hole, which is exposed to the outside.

[0043] The 2_1st filling portion is included, and the 2_1st filling portion is formed by filling an insulating material inside the 2_1st inner surface plating layer and the 2_1st end plating layer of the 2_1st via hole.

[0044] As a result, the air layer inside the 2_1st via hole is reduced (eliminated), so that cold welding defects caused by expansion of air can be suppressed during surface mounting.

[0045] In addition, during surface mounting, since the 2_1st via hole is blocked, it is possible to suppress the leakage of solder through the 2_1st via hole.

[0046] In one embodiment of the present invention, the vias include: a 2_1th via formed through the 2nd layer and the 1st layer; and an n_n-1th via formed through the nth layer and the n-1th layer.

[0047] The plating layer includes: a 2_1th inner surface plating layer formed on the inner surface of the 2_1th via hole; a 2_1th end plating layer formed on both ends of the 2_1th via hole; an n_n-1th inner surface plating layer formed on the inner surface of the n_n-1th via hole; and an n_n-1th end plating layer formed on both ends of the n_n-1th via hole.

[0048] The pads are respectively formed on the 2_1 end plating layer exposed to the outside among the 2_1 end plating layers of the 2_1 via hole and the n_n-1 end plating layer exposed to the outside among the n_n-1 end plating layers of the n_n-1 via hole.

[0049] The method comprises: a 2_1st filling portion, wherein the 2_1st filling portion is formed by filling an insulating material inside the 2_1st inner surface plating layer and the 2_1st end plating layer of the 2_1st via hole; and

[0050] The n_n-1th filling portion is formed by filling an insulating material inside the n_n-1th inner surface plating layer and the n_n-1th end plating layer of the n_n-1th via hole.

[0051] As a result, the air layer inside each of the 2_1th via hole and the (n_n-1th) via hole is reduced (eliminated), so that cold welding defects caused by expansion of air can be suppressed during surface mounting.

[0052] In addition, during surface mounting, since the 2_1th via hole and the n_n-1th via hole are blocked, respectively, it is possible to suppress leakage of solder through the 2_1th via hole and the n_n-1th via hole.

[0053] In one embodiment of the present invention, the via hole comprises a through hole formed through the first layer to the nth layer.

[0054] The plating layer includes an inner surface plating layer formed on the inner surface of the through hole and end plating layers respectively formed on both ends of the through hole.

[0055] The pads are respectively formed on end plating layers respectively formed on both ends of the through hole.

[0056] The method comprises a filling portion formed by filling an insulating material inside the inner surface plating and the end plating of the through hole.

[0057] As a result, the air layer inside the through hole is reduced (eliminated), so that cold welding defects caused by expansion of air inside the through hole can be suppressed during surface mounting.

[0058] Furthermore, during surface mounting, since the through hole is blocked, it is possible to suppress the occurrence of solder leakage through the through hole.

[0059] In one embodiment of the present invention, plate-shaped insulators are respectively provided between the first layer to the nth layer, and the via holes are formed by drilling through them.

[0060] This eliminates the need for expensive laser equipment, thereby suppressing an increase in cost when manufacturing the via hole.

[0061] In one embodiment of the present invention, the via hole further includes an intermediate via hole formed by penetrating two or more layers from the 2nd layer to the n-1th layer.

[0062] The plating layer includes: an inner surface plating layer formed on the inner surface of the middle via hole; and an end plating layer formed on both ends of the middle via hole.

[0063] The method comprises a filling portion, wherein the filling portion is formed by filling an insulating material inside the inner surface plating layer and the end plating layer of the middle via hole.

[0064] As a result, the air inside the intermediate via hole is reduced (removed), and the occurrence of defects caused by air expansion inside the intermediate via hole during surface mounting can be suppressed.

[0065] On the other hand, according to another field of the present invention, there is provided a method for manufacturing a printed circuit board, the method for manufacturing a printed circuit board comprising: forming a plurality of layers arranged in a layered manner with an insulator interposed therebetween;

[0066] a step of forming a via hole penetrating a layer including an uppermost n-th layer or a layer including a lowermost 1st layer in a stacking direction;

[0067] forming a plating layer inside and outside the via hole; and

[0068] The step of separating the plating layer exposed to the outside of the via hole from the periphery to form a pad.

[0069] Thus, the integration degree of components of the printed circuit board can be improved, and the size of the printed circuit board can be reduced.

[0070] In addition, the signal transmission path can be shortened and the signal processing speed can be increased.

[0071] In one embodiment of the present invention, the step of forming the coating layer comprises:

[0072] forming an inner surface plating layer on the inner surface of the via hole, and

[0073] The step of forming end plating layers at both ends of the via hole.

[0074] In one embodiment of the present invention, before the step of forming the end plating layer, the method further comprises:

[0075] The step of filling an insulating material inside the inner surface plating layer to form a filling portion.

[0076] As a result, the air inside the via hole can be reduced (exhausted), so that the occurrence of defects due to expansion of the air inside the via hole during surface mounting can be suppressed.

[0077] In one embodiment of the present invention, before the step of forming the via hole, the method includes:

[0078] The step of preparing a drill bit capable of penetrating the plurality of layers.

[0079] This eliminates the need for expensive equipment such as laser equipment, thereby suppressing an increase in manufacturing cost due to via hole formation.

[0080] In an embodiment of the present invention, the step of forming the via hole includes the step of forming a 2_1st via hole penetrating the second layer and the first layer.

[0081] In one embodiment of the present invention, the step of forming the via hole includes:

[0082] The step of forming an n_n-1th via hole penetrating the nth layer and the n-1th layer.

[0083] In one embodiment of the present invention, before the step of forming the pad, the method further includes:

[0084] a step of stacking the plurality of layers into a layered form, and

[0085] A step of insulating the surfaces of the plurality of layers stacked in layers.

[0086] On the other hand, according to another aspect of the present invention, there is provided a method for manufacturing a printed circuit board, comprising: forming a plurality of layers arranged in a layered manner with an insulator interposed therebetween;

[0087] a step of stacking the plurality of layers by arranging the first layer at the bottom and the nth layer at the top in a stacking direction,

[0088] forming a via hole including a through hole penetrating the nth layer to the first layer,

[0089] forming a plating layer inside and outside the via hole including the through hole, and

[0090] The step of separating the plating layer of the through hole exposed to the outside from the periphery to form a pad.

[0091] Thus, the integration degree of components of the printed circuit board can be improved, and the size of the printed circuit board can be reduced.

[0092] In addition, the signal transmission path can be shortened and the signal processing speed can be increased.

[0093] In one embodiment of the present invention, the step of forming a plating layer inside and outside the via hole including the through hole includes: forming a plating layer on the inner surface of the through hole, and forming a plating layer on both ends of the through hole.

[0094] Before the step of forming the end plating layer of the through hole, the method further includes the step of filling an insulating material inside the inner surface plating layer of the through hole to form a filling portion.

[0095] The step of forming a via hole including the through hole further includes:

[0096] A step of forming an intermediate via hole that penetrates two or more consecutive layers from the first layer to the nth layer and is not exposed to the outside.

[0097] The step of forming a plating layer inside and outside the via hole including the through hole includes: forming a plating layer on the inner surface of the middle via hole, and forming a plating layer on the end of the middle via hole.

[0098] Before the step of forming a plating layer at the end of the middle via hole, the method further includes the step of filling an insulating material inside the plating layer on the inner surface of the middle via hole to form a filling portion.

[0099] Effects of the Invention

[0100] As described above, according to an embodiment of the present invention, since it includes: a via hole formed by penetrating the layers including the first layer or the nth layer in the stacking direction; a plating layer formed inside and outside the via hole; and a pad formed by separating the plating layer formed at the end of the via hole from the periphery, it is possible to increase the density of components and thus reduce the size of the substrate. In addition, since the signal transmission path is shortened, the signal processing speed can be increased.

[0101] In addition, since an insulating material is filled inside the n_n-1th via hole penetrating the nth layer and the n-1th layer to form the n_n-1th filling portion, the air inside the n_n-1th via hole can be reduced. As a result, defects (cold welding) caused by air expansion inside the n_n-1th via hole can be suppressed. In addition, leakage of solder through the n_n-1th via hole can be suppressed.

[0102] Furthermore, since the 2_1st filling portion is formed by filling the insulating material inside the 2_1st via hole penetrating the second layer and the first layer, the air inside the 2_1st via hole is reduced, thereby suppressing the occurrence of cold welding defects caused by air expansion.

[0103] In addition, since the n_n-1th via hole and the 2_1th via hole are filled with insulating materials to form the n_n-1th filling part and the 2_1th filling part, respectively, the air inside each via hole can be reduced (removed). Therefore, the occurrence of cold welding defects caused by the expansion of the air inside each via hole due to high temperature can be suppressed during surface mounting.

[0104] In addition, since each via hole is formed by drilling with a drill, it is possible to eliminate the use of expensive laser equipment, thereby suppressing an increase in manufacturing cost due to the formation of the via holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0105] Figure 1 is a cross-sectional view of a main part of a printed circuit board according to an embodiment of the present invention,

[0106] Figure 2 FIG. 1 is a diagram for explaining a method for manufacturing a printed circuit board according to an embodiment of the present invention.

[0107] Figures 3a to 3i It is used to illustrate Figure 1 Diagram of the printed circuit board manufacturing process,

[0108] Figure 4 is a cross-sectional view of a main part of a printed circuit board according to another embodiment of the present invention,

[0109] Figures 5a to 5i It is used to illustrate Figure 4 Diagram of the printed circuit board manufacturing process,

[0110] Figure 6 is a cross-sectional view of a main part of a printed circuit board according to another embodiment of the present invention,

[0111] Figure 7 FIG. 2 is a diagram for explaining a method for manufacturing a printed circuit board according to another embodiment of the present invention.

[0112] Figure 8a to Figure 8h It is used to illustrate Figure 6 Diagram of the printed circuit board manufacturing process. DETAILED DESCRIPTION

[0113] Hereinafter, the embodiments disclosed in the present invention will be described in detail with reference to the accompanying drawings. In this specification, even for embodiments that are different from each other, the same or similar structures are given the same or similar figure marks, and the first description replaces the subsequent description. Unless the context clearly indicates otherwise, the singular expressions used in this specification include plural expressions. In addition, when explaining this specification, if it is determined that the specific description of the relevant known technology may unnecessarily confuse the subject matter of the present invention, its detailed description will be omitted. In addition, it should be noted that the drawings are only for easy understanding of the embodiments disclosed in this specification, and should not be interpreted as the technical ideas disclosed in this specification being limited by the drawings.

[0114] Figure 1 FIG. 2 is a cross-sectional view of a main part of a printed circuit board according to an embodiment of the present invention. Figure 1 As shown, the printed circuit board 100 of this embodiment includes a substrate 110 , a via 210 , a plating layer 230 a and a pad 270 .

[0115] The substrate 110 includes a plurality of layers 110L stacked in layers.

[0116] In this embodiment, the stacking direction of the plurality of layers 110L refers to the up-down direction in the figure.

[0117] In this embodiment, the plurality of layers 110L may be composed of, for example, circuit layers formed of a conductor (eg, copper (Cu)).

[0118] The plurality of layers 110L include a first layer 110L1 to an nth layer 110Ln along a stacking direction.

[0119] The plurality of layers 110L are configured to be spaced apart from each other along a stacking direction.

[0120] Plate-shaped insulators 110I are respectively provided between the plurality of layers 110L.

[0121] Thus, the plurality of layers 110L (circuit layers 110L) may be insulated from each other.

[0122] The plurality of layers 110L include a first layer 110L1 to a fourth layer 110L4 .

[0123] An insulator 110I is provided between the first layer 110L1 to the fourth layer 110L4 .

[0124] The insulator 110I is formed into a plate shape by, for example, a composite material called prepreg, which is a material in which a fiber reinforcement such as glass fiber or carbon fiber is impregnated with a liquid synthetic resin such as epoxy resin.

[0125] In this embodiment, the plurality of layers 110L may be disposed on one side or both sides of the plate-shaped insulator 110I.

[0126] In this embodiment, the plurality of layers 110L include a first layer 110L1 to a fourth layer 110L4 .

[0127] In this embodiment, the insulator 110I includes a first insulator 110I1 to a third insulator 110I3 .

[0128] Specifically, for example, the first layer 110L1 may be formed on the bottom surface of the first insulator 110I1, the second layer 110L2 may be formed on the bottom surface of the second insulator 110I2, the third layer 110L3 may be formed on the bottom surface of the third insulator 110I3, and the nth layer 110Ln (fourth layer 110L4) may be provided on the top surface of the third insulator 110I3.

[0129] In this embodiment, although the plurality of layers 110L includes the first layer 110L1 to the fourth layer 110L4, this is only an example and is not limited thereto. That is, the plurality of layers 110L may also include 6 layers, 8 layers, or 10 layers.

[0130] An insulating layer 150 may be formed on both side surfaces (bottom surface and upper end surface) of the substrate 110 along the stacking direction.

[0131] The insulating layer 150 may be formed, for example, by coating permanent ink on the outer surface of the circuit layer (in this embodiment, the first layer 110L1 and the fourth layer 110L4 ) plated with copper foil.

[0132] The insulating layer 150 includes, for example: a lower insulating layer 1501 coated on the outer surface of the first layer 110L1; and an upper insulating layer 1502 coated on the outer surface of the nth layer 110Ln (fourth layer 110L4).

[0133] The substrate 110 has a via hole 210 formed through layers including the uppermost n-th layer 110Ln (the fourth layer 110L4 in this embodiment).

[0134] In this embodiment, the via 210 includes an n_n-1th via 2101 formed through the nth layer 110Ln and the n-1th layer 110Ln-1. In this embodiment, the nth layer 110Ln as the uppermost layer is the 4th layer 110L4, so the n_n-1th via 2101 can be called a 4_3th via 2101.

[0135] In this embodiment, the via hole 210 may be formed by penetrating with a drill 220 .

[0136] Specifically, the via hole 210 (the n_n-1th via hole 2101 ) may be formed by a drill 220 penetrating the nth layer 110Ln, the third insulator 110I3 , and the n-1th layer 110Ln-1.

[0137] The inner diameter of the via hole 210 may be formed to be 0.6 mm, for example.

[0138] In this embodiment, although the inner diameter of the via hole 210 is 0.6 mm, this is only an example, and its size can be adjusted.

[0139] A plating layer 230 may be formed on the via hole 210 (the (n_n-1)th via hole 2101 ).

[0140] In this embodiment, the plating 230 includes: an n_n-1th inner surface plating 2301 formed on the inner surface of the n_n-1th via hole 2101; and an n_n-1th end plating 2302 formed on the end of the n_n-1th via hole 2101.

[0141] The plating layer 230 (the n_n-1th inner surface plating layer 2301 and the n_n-1th end plating layer 2302 ) may be, for example, copper (Cu) plating.

[0142] Thus, the nth layer 110Ln (the fourth layer 110L4) and the n-1th layer 110Ln-1 (the third layer 110L3) can be electrically connected, and a signal transmission path can be formed between the nth layer 110Ln and the n-1th layer 110Ln-1.

[0143] The n_n-1th via hole 2101 , the n_n-1th inner surface plating layer 2301 , and the n_n-1th end plating layer 2302 may be referred to as a conducting path 200 .

[0144] In this embodiment, the conducting path 200 may include the n_n-1th via hole 2101 , the n_n-1th inner surface plating layer 2301 , and the n_n-1th end plating layer 2302 .

[0145] In the present embodiment, although the first to nth layers 110L1 to 110Ln and the plating layer 230 are illustrated as being different (distinct) for the sake of convenience in describing the drawings, they may actually be formed of the same material (eg, copper (Cu)).

[0146] The plating layer 230 has a filling portion 250 filled with an insulating material.

[0147] Specifically, an n_n-1th filling portion 2501 is disposed inside the n_n-1th via hole 2101 .

[0148] Thus, the air inside the (n_n-1)th via hole 2101 can be reduced (removed).

[0149] According to such a structure, expansion of air inside the (n_n-1)th via hole 2101 due to high temperature can be suppressed during surface mounting.

[0150] This can prevent the solder 290 connected to the pad 270 described later from being cold-welded due to air expansion.

[0151] In this embodiment, a pad 270 may be included, which is formed by separating the plating layer 230 (the (n_n-1) end plating layer 2302 ) exposed to the outside from the periphery of the plating layer 230 .

[0152] The pad 270 may be formed to be larger than the via hole 210 , for example.

[0153] In this embodiment, the pad 270 may be configured to include the n_n-1th inner surface plating layer 2301 , the end of the n_n-1th end plating layer 2302 , and a portion of the nth layer 110Ln.

[0154] The pad 270 may be circular, for example.

[0155] In the present embodiment, although the pad 270 is circular, this is only an example, and the pad 270 may be a polygon such as a quadrilateral, a pentagon, a hexagon, an octagon, or an ellipse.

[0156] The component 300 may be bonded (mounted) on the pad 270 via solder 290 .

[0157] Figure 2 FIG. 1 is a diagram for explaining a method for manufacturing a printed circuit board according to an embodiment of the present invention. Figures 3a to 3i It is used to illustrate Figure 1 A diagram of the manufacturing process of a printed circuit board. Figure 2 As shown, a method for manufacturing a printed circuit board 100 according to an embodiment of the present invention includes: a step S110 of forming a plurality of layers 110L arranged in layers with an insulator 110I interposed therebetween, a step S130 of forming a via 210 penetrating a layer including the uppermost nth layer 110Ln or a layer including the lowermost first layer 110L1 along a stacking direction, a step S140 of forming a plating layer 230 inside and outside the via 210, and a step S180 of separating the plating layer 230 of the via 210 exposed to the outside from the periphery to form a pad 270.

[0158] like Figure 3a As shown, the plurality of layers 110L include the first layer 110L1 to the nth layer 110Ln separated in the stacking direction. In this embodiment, the plurality of layers 110L are exemplified as being composed of the first layer 110L1 to the fourth layer 110L4, but this is only an example and is not limited thereto.

[0159] The plurality of layers 110L may be circuit layers formed of copper (Cu).

[0160] The plurality of layers 110L are disposed on one or both surfaces of the insulator 110I.

[0161] In this embodiment, the insulator 110I is composed of a first insulator 110I1 to a third insulator 110I3.

[0162] Specifically, the first layer 110L1 is provided on the bottom surface of the first insulator 110I1 .

[0163] The second layer 110L2 is provided on the bottom surface of the second insulator 110I2.

[0164] The third layer 110L3 is disposed on the bottom surface of the third insulator 110I3, and the fourth layer 110L4 is disposed on the top surface of the third insulator 110I3.

[0165] Before the step S130 of forming the via hole 210 , a step S120 of preparing the drill bit 220 is included.

[0166] like Figure 3b As shown, the via hole 210 (the n_n-1th via hole 2101 ) is formed by penetrating with the drill bit 220 .

[0167] In this embodiment, the via hole 210 includes an (n_n-1)th via hole 2101 formed through the n-th layer 110Ln and the (n-1)-th layer 110Ln-1.

[0168] Specifically, the n_n-1th via hole 2101 is formed through the nth layer 110Ln, the third insulator 110I3 and the n-1th layer 110Ln-1. In this embodiment, since the nth layer 110Ln is the fourth layer 110L4, the n_n-1th via hole 2101 refers to the 4_3th via hole 2101.

[0169] The step S140 of forming the plating layer 230 inside and outside the via hole 210 includes: a step S145 of forming the inner surface plating layer 230 on the inner surface of the via hole 210 , and a step S155 of forming the end plating layer 230 at both ends of the via hole 210 .

[0170] like Figure 3c As shown, an inner surface plating layer 2301 (n_n-1 inner surface plating layer 2301) is formed by copper (Cu) plating on the inner surface of the n_n-1th via hole 2101 of the via hole 210. The n_n-1th inner surface plating layer 2301 is formed on the nth layer 110Ln, the third insulator 110I3 and the n-1th layer 110Ln-1 respectively.

[0171] Before the step S145 of forming the end plating layer 2302 , the process further includes filling the inner surface plating layer 2301 with an insulating material (resin) to form a filling portion 250 .

[0172] like Figure 3d As shown, an insulating material (resin) is filled inside the inner surface plating layer 2301 (the n_n-1th inner surface plating layer 2301) to form a filling portion 250 (the n_n-1th filling portion 2501).

[0173] Figure 3e As shown, end plating layers 2302 (n_n-1 end plating layers 2302) are formed at both ends of the via hole 210 (n_n-1th via hole 2101) along the stacking direction. The end plating layers 2302 are configured to form a plane with the nth layer 110Ln and the n-1th layer 110Ln-1.

[0174] After the step S145 of forming the end plating layer 2302 , the step S160 of stacking the plurality of layers 110L is further included.

[0175] like Figure 3f As shown, if the plating layer 230S140 is formed inside and outside the via hole 210, a plurality of layers 110L are stacked.

[0176] After the step S160 of stacking the plurality of layers 110L, the step S170 of bonding the plurality of layers 110L is further included.

[0177] like Figure 3g As shown, the stacked plurality of layers 110L are bonded (heat-bonded, hot pressed).

[0178] After the step S170 of bonding the plurality of layers 110L, the end portion plating layer 2302 exposed to the outside is separated from the periphery to form a pad 270 .

[0179] like Figure 3h As shown, the n_n-1th end plating layer 2302 exposed to the outside among the n_n-1th end plating layers 2302 is separated from the periphery to form a pad 270 .

[0180] The pad 270 , for example, may be formed to have a diameter larger than that of the via hole 210 (the (n_n-1)th via hole 2101 ).

[0181] The pad 270 may be configured to include a portion of the n-th layer 110Ln.

[0182] The pad 270 may be configured in a circular shape, for example. A cutout portion 280 where a portion of the n-th layer 110Ln is cut out is provided around the pad 270 to separate the pad 270 from the n-th layer 110Ln.

[0183] After the step S180 of forming the pad 270 , the method further includes the step S190 of insulating the surfaces of the bottom layer (the first layer 110L1 ) and the top layer (the nth layer 110Ln) of the plurality of layers 110L.

[0184] like Figure 3i As shown, an insulating layer 150 is formed on the outer surface (bottom surface) of the first layer 110L1 and the outer surface (top surface) of the n-th layer 110Ln.

[0185] The insulating layer 150 may be formed by, for example, coating permanent ink (Permanent Ink) on the outer surfaces of the first layer 110L1 and the nth layer 110Ln (the fourth layer 110L4 ).

[0186] After the step S190 of insulating the plurality of layers 110L, the method further includes a step S200 of mounting the component 300 on the pad 270 via the solder 290 .

[0187] Refer to Figure 1 The component 300 is mounted on the top surface of the pad 270 via the solder 290 .

[0188] With such a structure, the signal input from the component 300 is transmitted to the third layer 110L3 via the solder 290 and the pad 270 and the inner surface plating layer 230 (the n_n-1th inner surface plating layer 2301).

[0189] Figure 4 is a cross-sectional view of a main part of a printed circuit board according to another embodiment of the present invention, Figures 5a to 5i It is used to illustrate Figure 4 Diagram of the printed circuit board manufacturing process.

[0190] like Figure 4 As shown, the printed circuit board 100a of this embodiment includes a substrate 110, a via 210a, a plating layer 230a and a pad 270a.

[0191] The substrate 110 includes a plurality of layers 110L stacked in layers.

[0192] In the present embodiment, each of the plurality of layers 110L may be composed of a circuit layer formed of copper (Cu).

[0193] The plurality of layers 110L include a first layer 110L1 to an nth layer 110Ln stacked from a lower side in a stacking direction.

[0194] A plate-shaped insulator 110I (for example, prepreg) is provided between the plurality of layers 110L.

[0195] Thus, the plurality of layers 110L may be insulated from each other by the insulator 110I. In this embodiment, the plurality of layers 110L include a first layer 110L1 to a fourth layer 110L4.

[0196] In the present embodiment, although the case where the plurality of layers 110L include the first layer 110L1 to the fourth layer 110L4 is illustrated, this is merely an example and is not limited thereto.

[0197] The plurality of layers 110L may be disposed on one side or both sides of the insulator 110I.

[0198] The insulator 110I is composed of first to third insulators 110I1 to 110I3 that are separated in layers.

[0199] Specifically, in this embodiment, the first layer 110L1 is disposed on the bottom surface of the first insulator 110I1 , and the second layer 110L2 is disposed on the top surface of the first insulator 110I1 .

[0200] The third layer 110L3 is provided on the bottom surface of the third insulator 110I3, and the nth layer 110Ln (fourth layer 110L4) is provided on the top surface of the third insulator 110I3.

[0201] A second insulator 110I2 is interposed between the second layer 110L2 and the third layer 110L3 .

[0202] The second insulator 110I2 is disposed between the second layer 110L2 and the third layer 110L3 .

[0203] Thus, the second layer 110L2 and the third layer 110L3 can be insulated from each other.

[0204] The via hole 210 a includes, for example, an n_n-1th via hole 210 a 1 penetrating the nth layer 110Ln and the n-1th layer 110Ln-1.

[0205] The via hole 210a is configured to include, for example, a 2_1st via hole 210a2 formed penetrating the second layer 110L2 and the first layer 110L1.

[0206] The via hole 210 a may be formed to have a diameter of 0.6 mm, for example.

[0207] The via hole 210 a may be formed by a drill 220 .

[0208] Thus, when manufacturing the via hole 210 a , it is possible to suppress an increase in cost.

[0209] The plating layers 230a are formed by copper (Cu) plating.

[0210] The plating layer 230a includes, for example: an n_n-1th inner surface plating layer 230a1 formed on the inner surface of the n_n-1th via hole 210a1; and an n_n-1th end plating layer 230a2 formed on both ends of the n_n-1th via hole 210a1.

[0211] Thus, the n-th layer 110Ln and the n-1-th layer 110Ln-1 may be electrically connected to each other.

[0212] The plating layer 230a includes, for example: a 2_1st inner surface plating layer 230a3 formed on the inner surface of the 2_1st via hole 210a2; and a 2_1st end plating layer 230a4 formed on both ends of the 2_1st via hole 210a2.

[0213] Thus, the first layer 110L1 and the second layer 110L2 may be electrically connected to each other.

[0214] The n_n-1th via hole 210a1, the n_n-1th inner surface plating layer 230a1, and the n_n-1th end plating layer 230a2 may be referred to as an upper through hole, for example.

[0215] In addition, the 2_1st via hole 210a2, the 2_1st inner surface plating layer 230a3, and the 2_1st end plating layer 230a4 may be referred to as a lower through hole, for example.

[0216] In the present embodiment, although the first layer 110L1 to the nth layer 110Ln and the plating layers 230 a are illustrated as being distinguished from each other for the convenience of explaining the drawings, they are actually all formed of the same material (copper (Cu)).

[0217] On the other hand, a filling portion 250 a filled with an insulating material such as resin is provided inside the plating layer 230 a .

[0218] Specifically, an n_n-1th filling portion 250a1 is provided inside the n_n-1th inner surface plating layer 230a1 and the n_n-1th end plating layer 230a2.

[0219] As a result, the air inside the (n_n-1)th via hole 210a1 is reduced (removed), thereby preventing cold welding defects caused by air expansion during surface mounting.

[0220] A 2_1st filling portion 250a2 filled with an insulating material (eg, resin) is provided inside the 2_1st inner surface plating layer 230a3 and the 2_1st end plating layer 230a4.

[0221] As a result, the air inside the 2_1st via hole 210a2 is reduced, so that the occurrence of cold welding defects caused by air expansion during surface mounting can be suppressed.

[0222] In this embodiment, the exposed plating layer 230a of the plating layer 230a forms a pad 270a separated from the surrounding (circuit layer of the nth layer 110Ln and the first layer 110L1). The periphery of the pad 270a is formed with a cutout portion 280a for cutting off from the circuit layer.

[0223] Specifically, an upper pad 270a2 is formed on the n_n-1th end plating layer 230a2 exposed to the outside of the n_n-1th end plating layer 230a2. An upper cut-off portion 280a2 in which a part of the n_n-1th layer is cut off is formed on the periphery of the upper pad 270a2.

[0224] In addition, a lower pad 270a1 is formed on the 2_1 end plating layer 230a4 exposed to the outside of the 2_1 end plating layer 230a4. A lower cut-off portion 280a1 in which a part of the first layer 110L1 is cut off is formed on the periphery of the lower pad 270a1.

[0225] The components 300a are mounted on the pads 270a (the upper pad 270a2 and the lower pad 270a1) via solder 290a.

[0226] Specifically, the lower component 300a1 is mounted on the lower pad 270a1 via the lower solder 290a1, and the upper component 300a2 is mounted on the upper pad 270a2 via the upper solder 290a2.

[0227] Below, refer to Figures 5a to 5i A manufacturing process of printed wiring board 100a will be described.

[0228] like Figure 5aAs shown, the plurality of layers 110L include a first layer 110L1 to an nth layer 110Ln spaced apart from each other along a stacking direction. In this embodiment, the plurality of layers 110L include a first layer 110L1 to a fourth layer 110L4.

[0229] The plurality of layers 110L are respectively disposed on the surface of an insulator 110I (eg, prepreg).

[0230] The insulator 110I includes first to third insulators 110I1 to 110I3 spaced apart in a stacking direction.

[0231] Specifically, the first layer 110L1 and the second layer 110L2 are respectively disposed on the bottom surface and the top surface of the first insulator 110I1. The third layer 110L3 and the fourth layer 110L4 are respectively disposed on the bottom surface and the top surface of the third insulator 110I3. The second insulator 110I2 is inserted between the second layer 110L2 and the third layer 110L3. Thus, the second layer 110L2 and the third layer 110L3 can be insulated from each other.

[0232] Figure 5b As shown, a drill 220 is used to penetrate the nth layer 110Ln, the third insulator 110I3, the n-1th layer 110Ln-1, the second layer 110L2, the first insulator 110I1 and the first layer 110L1, thereby forming vias 210a (n_n-1th via 210a1 and 2_1th via 210a2), respectively.

[0233] Figure 5c As shown, inner surface plating layers 230a1 and 230a3 are formed inside each via hole 210a (the n_n-1th via hole 210a1 and the 2_1th via hole 210a2), respectively. The n_n-1th inner surface plating layer 230a1 is formed inside the n_n-1th via hole 210a1 by copper (Cu) plating. The 2_1st inner surface plating layer 230a3 is formed inside the 2_1st via hole 210a2 by copper (Cu) plating.

[0234] on the other hand, Figure 5d As shown, an insulating material (e.g., resin) is filled in each of the inner surface plating layers 230a1 and 230a3 to form a filling portion 250a. An n_n-1th filling portion 250a1 is formed in the n_n-1th inner surface plating layer 230a1. A 2_1th filling portion 250a2 is formed in the 2_1th inner surface plating layer 230a3.

[0235] like Figure 5eAs shown, end plated layers 230a2 and 230a4 are formed respectively at both ends of each via hole 210a (the n_n-1th via hole 210a1 and the 2_1th via hole 210a2) by copper (Cu) plating.

[0236] An n_n-1th end plating layer 230a2 is formed at both ends of the n_n-1th via hole 210a1.

[0237] 2_1 end plating layers 230a4 are respectively formed at both ends of the 2_1 via hole 210a2.

[0238] Figure 5f As shown, if end plating layers 230a2 and 230a4 are formed at both ends of each via hole, the plurality of layers 110L are arranged in a layered manner along the stacking direction.

[0239] like Figure 5g As shown, a plurality of layers 110L arranged in a layered manner are bonded to each other (for example, by heat bonding (hot press)).

[0240] After the plurality of layers 110L are bonded, the end portions of the plating layers 230a2 and 230a4 exposed to the outside of the plating layers 230a are cut off from the periphery to form pads 270a of a predetermined shape.

[0241] like Figure 5h As shown, the periphery of the n_n-1 end plating 230a2 exposed to the outside among the n_n-1 end plating 230a2 and the 2_1 end plating 230a4 exposed to the outside among the 2_1 end plating 230a4 are cut off to separate them from the periphery, thereby forming an upper solder pad 270a2 and a lower solder pad 270a1, respectively.

[0242] An upper cutout portion 280a2 in which a part of the n-th layer 110Ln (fourth layer 110L4) is removed is formed at the periphery of the upper pad 270a2.

[0243] In addition, a lower cutout portion 280a1 in which a part of the first layer 110L1 is removed is formed at the periphery of the lower pad 270a1.

[0244] After the pads 270 a are formed, the outer surfaces of the first layer 110L1 and the n-th layer 110Ln are coated with an insulating material to form insulating layers 150 .

[0245] The insulating layer 150 includes a lower insulating layer 1501 coated on the outer surface of the first layer 110L1 and an upper insulating layer 1502 coated on the outer surface of the n-th layer 110Ln.

[0246] The insulating layer 150 forming an insulator may be made of, for example, permanent ink.

[0247] After the insulating layer 150 is formed on the surface of the n-th layer 110Ln and the surface of the first layer 110L1, the components 300a are mounted on the pads 270a via the solder 290a (see Figure 4 Specifically, the lower component 300a1 is mounted on the lower pad 270a1 via the lower solder 290a1, and the upper component 300a2 is mounted on the upper pad 270a2 via the upper solder 290a2.

[0248] With such a structure, a signal input from the upper component 300a2 of the substrate 110 is transmitted to the third layer 110L3 via the upper solder 290a2 and the upper pad 270a2 and via the inner surface plating 230a (the n_n-1th inner surface plating 230a1).

[0249] In addition, a signal input from the lower component 300a1 of the substrate 110 is transmitted to the second layer 110L2 via the lower solder 290a1 and the lower pad 270a1 and via the inner surface plating layer 230a (the 2_1st inner surface plating layer 230a3).

[0250] Figure 6 FIG. 4 is a cross-sectional view of a main part of a printed circuit board according to another embodiment of the present invention.

[0251] like Figure 6 As shown, the printed circuit board 100b of this embodiment includes a substrate 110, a via 210b, a plating layer 230b and a pad 270b.

[0252] The substrate 110 includes a plurality of layers 110L stacked in layers.

[0253] In the present embodiment, the plurality of layers 110L are circuit layers formed of, for example, a conductor (copper (Cu)).

[0254] The plurality of layers 110L include a first layer 110L1 to an nth layer 110Ln along a stacking direction. In the present embodiment, the plurality of layers 110L include a first layer 110L1 to a fourth layer 110L4, but the present invention is not limited thereto.

[0255] Plate-shaped insulators 110I (for example, prepreg) are provided between the plurality of layers 110L.

[0256] The insulator 110I includes, for example, first to third insulators 110I1 to 110I3 that are spaced apart from each other in the thickness direction.

[0257] The plurality of layers 110L are, for example, disposed on one side or both sides of the insulator 110I.

[0258] Specifically, for example, the first layer 110L1 may be provided on the bottom surface of the first insulator 110I1 .

[0259] The second layer 110L2 may be provided on the bottom surface of the second insulator 110I2.

[0260] The third layer 110L3 may be disposed on a bottom surface of the third insulator 110I3, and the fourth layer 110L4 may be disposed on a top surface of the third insulator 110I3.

[0261] An insulating layer 150 is disposed on both surfaces of the substrate 110 along a stacking direction.

[0262] The insulating layer 150 is formed by coating the surface of the first layer 110L1 and the surface of the n-th layer 110Ln with permanent ink, for example.

[0263] The insulating layer 150 includes a lower insulating layer 1501 coated on the surface of the first layer 110L1 and an upper insulating layer 1502 coated on the surface of the n-th layer 110Ln.

[0264] The substrate 110 is provided with a via hole 210 b penetrating at least two layers.

[0265] The via hole 210 b may be formed by, for example, drilling through with a drill 220 .

[0266] Thus, it is possible to eliminate the need to use expensive equipment when forming the via hole 210 b , thereby suppressing a significant increase in manufacturing cost.

[0267] The diameter of the via hole 210 b may be, for example, 0.6 mm.

[0268] Specifically, the via hole 210 b includes, for example, a through hole 210 b 1 formed penetrating from the n-th layer 110Ln to the first layer 110L1 .

[0269] The through hole 210b1 may be formed to sequentially penetrate the nth layer 110Ln (fourth layer 110L4), the third insulator 110I3, the third layer 110L3, the second insulator 110I2, the second layer 110L2, the first insulator 110I1, and the first layer 110L1.

[0270] The via hole 210 b includes, for example, a middle via hole 210 b 2 , which is formed by penetrating two consecutive layers among the first layer 110L1 to the nth layer 110Ln and is not exposed to the outside.

[0271] The middle via hole 210b2 may be formed, for example, to sequentially penetrate the nth layer 110Ln (fourth layer 110L4), the third insulator 110I3, the third layer 110L3, the second insulator 110I2, the second layer 110L2, the first insulator 110I1, and the first layer 110L1.

[0272] In the present embodiment, although the middle via hole 210 b 2 is formed from the n-th layer 110Ln through the first layer 110L1 , this is merely an example and is not limited thereto.

[0273] A plating layer 230b is formed inside and outside the via hole 210b. The plating layer 230b is formed of, for example, copper (Cu) plating.

[0274] Specifically, an inner surface plating layer 230b1 is formed on the inner surface of the through hole 210b1.

[0275] End plated layers 230b2 are formed at both ends of the through hole 210b1 in the stacking direction.

[0276] An inner surface plating layer 230b3 is formed on the inner surface of the middle via hole 210b2.

[0277] End plating layers 230b4 are respectively formed at both ends of the middle via hole 210b2 along the stacking direction.

[0278] In this embodiment, the plating layers 230 b 4 at both side ends of the middle via hole 210 b 2 are disposed inside the insulating layer 150 and are therefore not exposed to the outside.

[0279] The end plating layers 230b2 on both sides of the through hole 210b1 are exposed to the outside.

[0280] A filling portion 250b filled with an insulating material is provided inside the plating layer 230b.

[0281] The filling portion 250 b includes: a first filling portion 250 b 1 formed inside the through hole 210 b 1 ; and a second filling portion 250 b 2 formed inside the middle via hole 210 b 2 .

[0282] Specifically, the end plating layers 230b2 on both sides of the through hole 210b1 are respectively cut off to be separated from the periphery (the nth layer 110Ln and the first layer 110L1) to form pads 270b. The pads 270b formed on both sides of the through hole 210b1 include a lower pad 270b1 formed on the lower part of the substrate 110 and an upper pad 270b2 formed on the upper part of the substrate 110.

[0283] The pad 270 b is formed to be larger than the via hole 210 b.

[0284] Thus, a portion of the conductor around the inner surface plating layers 230a1 and 230a3 is formed by the pad 270b.

[0285] A cutout portion 280b having a cutout area is formed at the periphery of each of the pads 270b. Specifically, a lower cutout portion 280b1 is formed at the periphery of the lower pad 270b1, and an upper cutout portion 280b2 is formed at the periphery of the upper pad 270b2.

[0286] Components 300b are respectively mounted on the pads 270b1 and 270b2 on both sides of the through hole 210b1 via solder 290b.

[0287] Specifically, the lower component 300b1 is mounted on the lower pad 270b1 via the lower solder 290b1, and the upper component 300b2 is mounted on the upper pad 270b2 via the upper solder 290b2.

[0288] Figure 7 FIG. 2 is a diagram for explaining a method for manufacturing a printed circuit board according to another embodiment of the present invention. Figure 8a to Figure 8h It is used to illustrate Figure 6 Diagram of the printed circuit board manufacturing process.

[0289] like Figure 7 As shown, a method for manufacturing a printed circuit board 100b according to an embodiment of the present invention includes: a step S310 of forming a first layer 110L1 to an nth layer 110Ln respectively arranged in layers via an insulator 110I; a step S320 of stacking the first layer 110L1 to the nth layer 110Ln by arranging the first layer 110L1 at the bottom and the nth layer 110Ln at the top along the stacking direction; a step S350 of forming a via hole 210b including a through hole 210b1 penetrating the first layer 110L1 from the nth layer 110Ln; a ​​step S360 of forming a plating layer 230b inside and outside the via hole 210b including the through hole 210b1; and a step S380 of separating the plating layer 230b exposed to the outside of the plating layer 230b of the through hole 210b1 from the periphery to form a solder pad 270b.

[0290] like Figure 8a As shown, the plurality of layers 110L of the substrate 110 include the first layer 110L1 to the nth layer 110Ln separated along the stacking direction. In this embodiment, although the plurality of first layer 110L1 to the nth layer 110Ln are illustrated as the first layer 110L1 to the fourth layer 110L4, it is not limited thereto.

[0291] The first to n-th layers 110L1 to 110Ln are separated in a stacking direction, and insulators 110I are provided between the first to n-th layers 110L1 to 110Ln, respectively. Thus, the plurality of first to n-th layers 110L1 to 110Ln can be insulated from each other.

[0292] The plurality of first to nth layers 110L1 to 110Ln are circuit layers formed of a conductor (eg, copper (Cu)).

[0293] The insulator 110I may be, for example, a prepreg.

[0294] The insulator 110I includes plate-shaped first to third insulators 110I1 to 110I3.

[0295] In this embodiment, the first layer 110L1 is disposed on the bottom surface of the first insulator 110I1, the second layer 110L2 is disposed on the bottom surface of the second insulator 110I2, the third layer 110L3 is disposed on the bottom surface of the third insulator 110I3, and the fourth layer 110L4 is disposed on the upper surface of the third insulator 110I3.

[0296] After the step S320 of stacking the plurality of layers, a step S330 of bonding the plurality of layers 110L is further included.

[0297] like Figure 8b As shown, the plurality of first layers 110L1 to nth layers 110Ln are bonded after being stacked. The plurality of first layers 110L1 to nth layers 110Ln may be bonded to each other by being pressed, for example, in a vacuum state at a high temperature.

[0298] A via hole 210 b is formed in the bonded substrate 110 .

[0299] Before the step S350 of forming the via hole 210 b , the step S340 of preparing the drill bit 220 is included.

[0300] like Figure 8c As shown, the drill 220 is used to form a via hole 210 b in the mutually bonded substrates 110 .

[0301] The via hole 210 b includes, for example, a through hole 210 b 1 formed from the n-th layer 110Ln and sequentially penetrating the first layer 110L1 .

[0302] A middle via hole 210b2 is disposed on one side of the through hole 210b1. The middle via hole 210b2 penetrates two consecutive layers from the first layer 110L1 to the nth layer 110Ln and is not exposed to the outside.

[0303] In the present embodiment, although the intermediate via 210b2 is illustrated as being formed from the nth layer 110Ln through the first layer 110L1, this is only an example and is not limited thereto.

[0304] A plating layer 230 b is formed inside and outside the via hole 210 b (through hole 210 b 1 , middle via hole 210 b 2 ) by copper (Cu) plating.

[0305] Step S360 of forming the plating layer 230b inside and outside the via hole 210b including the through hole 210b1 includes: step S365 of forming the inner surface plating layer 230b on the inner surface of the via hole 210b; and step S375 of forming the end plating layer 230b at both ends of the via hole 210b.

[0306] In this embodiment, the step S365 of forming the inner surface plating layer 230b includes: forming the inner plating layer 230b on the inner surface of the through hole 210b1; and forming the inner surface plating layer 230b on the inner surface of the middle via hole 210b2.

[0307] The step S375 of forming end plating layers 230b at both ends of the via hole 210b includes: forming end plating layers 230b at both ends of the through hole 210b1; and forming end plating layers 230b at both ends of the middle via hole 210b2.

[0308] like Figure 8d As shown, inner surface plating layers 230 b are formed on the inner surfaces of the through hole 210 b 1 and the middle via hole 210 b 2 by copper (Cu) plating.

[0309] On the other hand, before the step S375 of forming the end plating layer 230b of the via hole 210b, the method further includes the step S370 of filling the via hole 210b with an insulating material (resin) to form a filling portion 250b.

[0310] like Figure 8e As shown, the insulating material (resin) is filled inside the through hole 210b1 and inside the middle via hole 210b2 to form filling portions 250b respectively.

[0311] The filling portion 250 b includes: a first filling portion 250 a 1 filled in the through hole 210 b 1 ; and a second filling portion 250 a 2 filled in the middle via hole 210 b 2 .

[0312] like Figure 8f As shown, end plating layers 230b2 are respectively formed on both sides of the through hole 210b1 and the middle via hole 210b2 along the stacking direction of the substrate 110 by copper plating.

[0313] Thus, the nth layer 110Ln (the fourth layer 110L4 ), the n-1th layer 110Ln-1 (the third layer 110L3 ), the second layer 110L2 , and the first layer 110L1 may be electrically connected to each other.

[0314] On the other hand, Figure 8g As shown, the end plating layers 230b2 of the through hole 210b1 on both sides along the stacking direction of the substrate 110 are separated from the periphery by cutting to form pads 270b.

[0315] In this embodiment, the pad 270b may be formed by being separated from the nth layer 110Ln and the first layer 110L1. A cutout portion 280b formed by cutting out the nth layer 110Ln and the first layer 110L1 is provided at the periphery of the pad 270b.

[0316] The pad 270 b may be formed to have a size greater than the diameter of the through hole 210 b 1 , for example.

[0317] The pads 270 b include an upper pad 270 b 2 disposed on the upper side along the thickness direction (up and down direction in the figure) of the substrate 110 and a lower pad 270 b 1 disposed on the lower side.

[0318] The upper pad 270 b 2 may be configured to include a portion of the n-th layer 110Ln (fourth layer 110L4 ), for example.

[0319] An upper cut-off portion 280b2 in which a part of the n-th layer 110Ln (fourth layer 110L4) is cut off and removed is provided at the periphery of the upper pad 270b2.

[0320] The lower pad 270 b 1 may be formed to include a portion of the first layer 110L1 , for example.

[0321] A lower cutout portion 280b1 in which a part of the first layer 110L1 is cut out (removed) is provided at the periphery of the lower pad 270b1.

[0322] On the other hand, after step S380 of separating the exposed plating 230b of the through hole 210b1 from the surrounding area to form a solder pad 270b, an insulation treatment step S390 is also included. In the insulation treatment step S390, insulation treatment is performed on both side surfaces along the thickness direction of the substrate 110 to form an insulation layer 150.

[0323] Both sides (bottom and top) of the substrate 110 in the thickness direction may be coated with permanent ink to form an insulating layer 150. The insulating layer 150 includes a lower insulating layer 1501 coated on the outer surface of the first layer 110L1 and an upper insulating layer 1502 coated on the outer surface of the nth layer 110Ln.

[0324] The upper pad 270b2 and the lower pad 270b1 are exposed to the outside.

[0325] Both ends of the plating layer 230 b 4 at both ends of the middle via hole 210 b 2 are coated by the insulating layer 150 and are not exposed to the outside.

[0326] After step S390 of performing insulation treatment on both side surfaces of the substrate 110 along the thickness direction to form an insulation layer 150 , step S400 of mounting components on the pads 270 a via solder 290 a is also included.

[0327] The lower component 300a1 is mounted on the lower pad 270a1 via the lower solder 290a1, and the upper component 300a2 is mounted on the upper pad 270a2 via the upper solder 290a2.

[0328] With such a structure, the signal input from the upper component 300b2 of the substrate 110 can be input to the inner surface plating layer 230b1 via the upper solder 290b2 and the upper pad 270b2. In addition, the signal input from the lower component 300b2 can be input to the inner surface plating layer 230b1 via the lower solder 290b1 and the lower pad 270b1.

[0329] The signal input to the inner surface plating layer 230b1 of the through hole 210b1 may be transmitted to the third layer 110L3 and / or the second layer 110L2, respectively.

[0330] The specific embodiments of the present invention are illustrated and described above. However, since the present invention can be implemented in various forms within the scope of its concept or essential characteristics, the embodiments described above are not limited to the specific contents of implementing the present invention.

[0331] In addition, even embodiments not listed one by one in the above detailed description should be interpreted broadly within the scope of the technical concept defined in the attached claims. Moreover, all changes and modifications included in the technical scope of the claims and the equivalent scope thereof should be included in the attached claims.

Claims

1. A printed circuit board, wherein: include: A substrate, including first to nth layers stacked in layers; A via hole is formed by penetrating the layer including the first layer or the nth layer along the stacking direction; a plating layer formed inside and outside the via hole; as well as The pad is formed by separating the plating layer formed at the end of the via hole from the periphery.

2. The printed circuit board according to claim 1, wherein: The via hole includes an n_n-1th via hole formed through the nth layer and the n-1th layer; The plating layer includes an n_n-1th inner surface plating layer formed on the inner surface of the n_n-1th via hole, and an n_n-1th end plating layer formed respectively on both ends of the n_n-1th via hole; The pad is formed on the n_n-1th end plating layer of the n_n-1th via hole and is exposed to the outside.

3. The printed circuit board according to claim 2, wherein: Also includes: The n_n-1th filling portion is formed by filling an insulating material inside the n_n-1th inner surface plating layer and the n_n-1th end plating layer of the n_n-1th via hole.

4. The printed circuit board according to claim 1, wherein: The via hole includes a 2_1st via hole formed through the second layer and the first layer; The plating layer includes a 2_1 inner surface plating layer formed on the inner surface of the 2_1 via hole, and a 2_1 end plating layer formed respectively on both ends of the 2_1 via hole; The pad is formed on the 2_1 end plating layer of the 2_1 via hole, which is exposed to the outside.

5. The printed circuit board according to claim 4, wherein: Also includes: The 2_1 filled portion is formed by filling an insulating material inside the 2_1 inner surface plating layer and the 2_1 end plating layer of the 2_1 via hole.

6. The printed circuit board according to claim 1, wherein: The via holes include a 2_1th via hole formed by penetrating the 2nd layer and the 1st layer, and an n_n-1th via hole formed by penetrating the nth layer and the n-1th layer; The plating layer includes a 2_1 inner surface plating layer formed on the inner surface of the 2_1 via hole, a 2_1 end plating layer formed respectively at both ends of the 2_1 via hole, an n_n-1 inner surface plating layer formed on the inner surface of the n_n-1 via hole, and an n_n-1 end plating layer formed respectively at both ends of the n_n-1 via hole; The pads are respectively formed on the 2_1 end plating layer exposed to the outside among the 2_1 end plating layers of the 2_1 via hole and the n_n-1 end plating layer exposed to the outside among the n_n-1 end plating layers of the n_n-1 via hole.

7. The printed circuit board according to claim 6, wherein: Also includes: The 2_1 filling portion is formed by filling an insulating material inside the 2_1 inner surface plating layer and the 2_1 end plating layer of the 2_1 via hole; and The n_n-1th filling portion is formed by filling an insulating material inside the n_n-1th inner surface plating layer and the n_n-1th end plating layer of the n_n-1th via hole.

8. The printed circuit board according to claim 1, wherein: The via hole comprises a through hole formed through the first layer to the nth layer; The plating layer includes an inner surface plating layer formed on the inner surface of the through hole, and end plating layers respectively formed on both ends of the through hole; The pads are respectively formed on end plating layers respectively formed at both ends of the through hole.

9. The printed circuit board according to claim 8, wherein: Also includes: The filling portion is formed by filling an insulating material inside the inner surface plating layer and the end plating layer of the through hole.

10. The printed circuit board according to any one of claims 1 to 9, wherein: A plate-shaped insulator is provided between the first layer to the nth layer, respectively. The via hole is formed by drilling through it.

11. The printed circuit board according to claim 10, wherein: The via hole further includes an intermediate via hole, which is formed by penetrating two or more consecutive layers from the first layer to the nth layer and is not exposed to the outside; The plating layer includes an inner surface plating layer formed on the inner surface of the middle via hole, and end plating layers respectively formed on both ends of the middle via hole; The printed circuit board further includes a filling portion, which is formed by filling an insulating material inside the inner surface plating layer and the end plating layer of the middle via hole.

12. A method for manufacturing a printed circuit board, wherein: include: a step of forming a plurality of layers arranged in a layered manner with an insulator interposed therebetween; a step of forming a via hole penetrating a layer including an nth layer arranged on the uppermost side or a layer including a first layer on the lowermost side in a stacking direction; A step of forming a plating layer inside and outside the via hole; as well as The step of separating the plating layer exposed to the outside of the via hole from the periphery to form a pad.

13. The method for manufacturing a printed circuit board according to claim 12, wherein: The steps of forming the coating include: forming an inner surface plating layer on the inner surface of the via hole, and The step of forming end plating layers at both ends of the via hole.

14. The method for manufacturing a printed circuit board according to claim 13, wherein: Before the step of forming the end plating layer, the method further comprises: The step of filling an insulating material inside the inner surface plating layer to form a filling portion.

15. The method for manufacturing a printed circuit board according to claim 12, wherein: Before the step of forming the via hole, the method further includes: The step of preparing a drill bit capable of penetrating the plurality of layers.

16. The method for manufacturing a printed circuit board according to claim 12, wherein: The step of forming the via hole includes the step of forming a 2_1st via hole penetrating the second layer and the first layer.

17. The method for manufacturing a printed circuit board according to claim 12, wherein: The step of forming the via hole includes the step of forming an n_n-1th via hole penetrating the nth layer and the n-1th layer.

18. The method for manufacturing a printed circuit board according to any one of claims 12 to 17, wherein: Before the step of forming the pad, the method further includes: a step of stacking the plurality of layers in layers; and The step of insulating the surfaces of the plurality of layers stacked in layers.

19. A method for manufacturing a printed circuit board, wherein: include: a step of forming the first layer to the nth layer arranged in layers with an insulator interposed therebetween, a step of stacking the first to n layers by arranging the first layer at the bottom and the nth layer at the top in a stacking direction, forming a via hole including a through hole penetrating from the nth layer through the first layer, forming a plating layer inside and outside the via hole including the through hole, and The step of separating the plating layer of the through hole exposed to the outside from the periphery to form a pad.

20. The method for manufacturing a printed circuit board according to claim 19, wherein: The step of forming the via hole includes the step of forming an intermediate via hole that is formed through two or more consecutive layers among the first layer to the nth layer and is not exposed to the outside.

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