A Preparation Method of Cavity-SOI with a Thermally Oxidized Layer on the Inner Wall of the Cavity

Abstract

The present invention discloses a method for fabricating Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity. The present invention relates to the technical field of Cavity-SOI fabrication. The method includes obtaining a cavity wafer, performing a first thermal oxidation process on the cavity wafer to form a first thermal oxidation layer, etching and removing the first thermal oxidation layer using a wet process, performing a second thermal oxidation process on the cavity wafer to form a second thermal oxidation layer, and bonding the cavity wafer with another wafer to obtain a Cavity-SOI structure. The Cavity-SOI fabrication method of the present invention utilizes the rounding and sinking effects of the thermal oxidation process on the corners of the non-planar silicon structure. By applying two thermal oxidation processes, the micro-protrusion effect of the thermal oxidation layer at the silicon corners is weakened and controlled below the top bonding surface, which is beneficial to the subsequent direct silicon bonding process.

Description

Technical Field

[0001] The present invention relates to the technical field of Cavity - SOI fabrication, and particularly to a method for preparing Cavity - SOI with a thermally oxidized layer covering the inner wall of the cavity. Background Art

[0002] In MEMS silicon wafer process technology, the silicon dioxide layer grown by thermal oxidation process has the advantages of thin film denseness, good uniformity, strong insulation, etc., and is a common process in technologies such as silicon - silicon direct bonding and SOI fabrication. In the MEMS device processing technology, the preparation of Cavity - SOI structure is often involved. Taking MEMS inertial devices as a typical application, the bulk silicon processing technology thereof all requires the fabrication of Cavity - SOI structure. A common process scheme is as follows: First, a silicon dioxide insulating layer is thermally oxidized on the initial silicon substrate wafer. After lithographing the anchor point pattern, the oxide layer etching and deep cavity silicon etching are carried out. Then, it is directly bonded with another silicon double - polished wafer or SOI wafer by silicon - silicon direct bonding. The bonded wafer is thinned to the required thickness, and then deep silicon etching is carried out to form the sensitive structure of the device. In this process scheme, since there is no thermally oxidized layer at the bottom and side walls of the cavity, during the deep silicon etching of the sensitive structure, the silicon substrate wafer will be severely etched and damaged, causing device reliability problems.

[0003] In order to prevent the etching damage to the substrate silicon during the deep silicon etching of the sensitive structure, it is necessary to first carry out deep cavity silicon etching, and then carry out the thermal oxidation process, so as to cover the inner wall of the cavity with a thermally oxidized layer, and then carry out the silicon - silicon direct bonding and the etching process of the sensitive mechanism. In addition to the above situation, MEMS devices often involve growing a silicon dioxide layer by thermal oxidation process on a non - planar surface with a three - dimensional cavity structure, and then carrying out the silicon - silicon direct bonding process with another wafer to form a Cavity - SOI structure with a thermally oxidized layer covering the inner wall of the cavity.

[0004] However, the experimental results show that when carrying out the thermal oxidation process on a non - planar surface with a three - dimensional cavity structure, due to reasons such as a large contact surface at the silicon step corner, micro - protrusions will be formed on the thermally oxidized layer, that is, the surface of the oxide layer on the wafer top bonding surface is uneven, and these micro - protrusions are nanoscale. And the silicon - silicon direct bonding has extremely high requirements for the flatness of the wafer bonding surface, and these nanoscale micro - protrusions will cause bonding failure.

[0005] To avoid the failure of the silicon-silicon direct bonding process, the general preparation method is as follows: (1) After thermal oxidation, lithography is used to expose the oxide layer at the corners, and then the micro-protrusions of the thermal oxide layer are removed by dry etching or wet etching; or (2) On the bonding surface of another bonding wafer, lithography is used to expose the corresponding positions of the micro-protrusions of the thermal oxide layer, and then a shallow cavity is etched to remove the silicon at the corresponding positions of the micro-protrusions. Method (1) involves deep cavity lithography, which is difficult and inefficient, does not meet the mass production requirements, and may not be achievable when the cavity depth is large; Method (2) adds more process steps and involves alignment bonding, which also increases the process complexity and does not meet the mass production requirements.

[0006] The invention application with the application number 202410541275.X discloses a preparation process for the vacuum cavity structure of a high-temperature Cavity-SOI absolute pressure sensor chip. Using the application solution, problems such as long outsourcing processing cycle, high cost, and uncontrollable process of the vacuum cavity silicon-silicon bonding Cavity-SOI process for high-temperature MEMS absolute pressure sensor chips are solved. However, it also has the problem that micro-protrusions will form on the thermal oxide layer, affecting silicon-silicon bonding. Summary of the Invention

[0007] Aiming at the above existing problems, the purpose of the present invention is to provide a preparation method for Cavity-SOI with a thermal oxide layer covering the inner wall of the cavity, which uses two thermal oxidation processes to weaken the micro-protrusions of the thermal oxide layer at the silicon corners, facilitating the silicon-silicon bonding process.

[0008] The purpose of the present invention can be achieved through the following technical solutions: A preparation method for Cavity-SOI with a thermal oxide layer covering the inner wall of the cavity, including:

[0009] S1. Fabricate a cavity on the wafer to obtain a cavity wafer;

[0010] S2. Perform a first thermal oxidation process on the cavity wafer to form a first thermal oxide layer

[0011] S3. Use a wet process to etch and remove the first thermal oxide layer;

[0012] S4. Perform a second thermal oxidation process on the cavity wafer to form a second thermal oxide layer;

[0013] S5. Bond the cavity wafer with another wafer to obtain a Cavity-SOI structure.

[0014] As a further solution of the present invention, in S1, when fabricating a cavity on a silicon substrate wafer, the steps include:

[0015] S11. Use a lithography process to obtain an anchor point pattern;

[0016] S12. Etch the deep cavity according to the anchor pattern by using deep silicon etching process.

[0017] As a further solution of the present invention, the silicon wafer in S1 uses a silicon substrate.

[0018] As a further solution of the present invention, when performing the first thermal oxidation process in S2, the reaction gases are O2 and H2O.

[0019] As a further solution of the present invention, when performing the first thermal oxidation process in S2, the oxidation temperature range is 1000°C to 1200°C. Among them, the silicon corners wrapped by the first thermal oxidation layer sink slightly lower than the top surface of the cavity wafer.

[0020] As a further solution of the present invention, when performing the first thermal oxidation process in S2, the oxidation temperature is 1100°C.

[0021] As a further solution of the present invention, the wet process in S3 uses BOE wet process.

[0022] As a further solution of the present invention, the thickness of the first thermal oxidation layer is adjusted according to the required thickness of the second thermal oxidation layer.

[0023] As a further solution of the present invention, the thickness range of the first thermal oxidation layer is 1μm to 3μm.

[0024] As a further solution of the present invention, in S5, after the cavity wafer is bonded to another wafer, a thinning process is performed to obtain Cavity-SOI.

[0025] Advantages of the present invention:

[0026] 1. The Cavity-SOI preparation method of the present invention utilizes the rounding and sinking effects of the thermal oxidation process on the corners of the non-planar silicon structure. By using two thermal oxidation processes, the micro-protrusion effect of the thermal oxidation layer at the silicon corners is weakened and controlled below the top bonding surface, which is beneficial to the subsequent direct silicon-to-silicon bonding process.

[0027] 2. The process of the Cavity-SOI preparation method of the present invention has a simple and easy-to-control process flow. The inner wall of the cavity and the bonding surface have a uniform thermal oxidation layer. It does not involve deep cavity lithography and alignment bonding, is suitable for batch manufacturing, and has strong flexibility. It can realize structures that are difficult to achieve by traditional methods and meet the complex and changeable application requirements of MEMS device manufacturing. Brief Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of the cavity wafer of the present invention;

[0029] Figure 2This is a schematic diagram of the structure of the cavity wafer after one thermal oxidation of the present invention;

[0030] Figure 3 This is a schematic diagram of the structure of the cavity wafer after the wet process of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure of the cavity wafer after one thermal oxidation of the present invention;

[0032] Figure 5 Schematic diagram of the structure after the silicon-silicon bonding process of the present invention;

[0033] Figure 6 It is a schematic diagram of the structure after the thinning process of the present invention.

[0034] 110. Cavity wafer; 120. Silicon substrate; 130. Primary thermal oxide layer; 140. Secondary thermal oxide layer; 150. Silicon corner; 160. Micro-bump; 170. Bonded wafer. DETAILED DESCRIPTION

[0035] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0036] When obtaining a Cavity-SOI structure in which the inner wall of the cavity is covered with a thermal oxide layer, micro-bumps 160 are formed in the thermal oxide layer at the corners of the silicon steps due to the large contact area. That is, the surface of the oxide layer on the bonding surface of the top of the wafer is uneven. These micro-bumps 160 are nanometer-scale. Since direct silicon-silicon bonding requires extremely high flatness of the wafer bonding surface, these nanometer-scale micro-bumps 160 can cause bonding failure.

[0037] In order to solve the above problems, the present invention discloses a method for preparing Cavity-SOI with a cavity inner wall covered with a thermal oxide layer. Figures 1 to 6 As shown, the steps include:

[0038] S1, making a cavity on a wafer to obtain a cavity wafer 110;

[0039] S2, performing a primary thermal oxidation process on the cavity wafer 110 to form a primary thermal oxidation layer 130;

[0040] S3, removing the primary thermal oxide layer 130 by wet etching;

[0041] S4, performing a secondary thermal oxidation process on the cavity wafer 110 to form a secondary thermal oxidation layer 140;

[0042] S5. Bond the cavity wafer 110 to another bonded wafer 170 to obtain a Cavity-SOI structure.

[0043] Example: As Figure 1 shown, the wafer uses a silicon substrate 120. Through photolithography and deep silicon etching processes, a wafer cavity structure is fabricated to obtain the cavity wafer 110. Specifically: First, obtain the anchor pattern through photolithography, and then, based on the anchor pattern, use the deep silicon etching process to etch the deep cavity. For example, the etching depth is 50 μm.

[0044] First, perform a first thermal oxidation process on the cavity wafer 110. The reaction gases are O2 and H2O, and the oxidation temperature is controlled at 1100 °C. The thickness of the first thermal oxide layer 130 formed is 2 μm.

[0045] After the first thermal oxidation process, as Figure 2 shown, micro-protrusions 160 will form at the silicon corners 150 of the first thermal oxide layer 130, resulting in an uneven surface of the oxide layer on the top bonding surface, which affects the subsequent direct silicon-silicon bonding process. At the same time, the silicon corners 150 wrapped by the thermal oxide layer will present a smooth morphology and sink below the top surface.

[0046] Then, use the BOE wet process to etch the first thermal oxide layer 130 clean, exposing the surface of the silicon substrate 120. As Figure 3 shown, at this time, the silicon corners 150 present a smooth morphology and sink slightly below the top surface.

[0047] The smoothness and sinking degree of the silicon corners 150 can be controlled by controlling the thickness of the first thermal oxide layer 130, as well as the gases and oxidation temperature used in the thermal oxidation process. The thickness range of the first thermal oxide layer 130 can be controlled from 1 μm to 3 μm. The oxidation temperature range can be adjusted between 1000 °C and 1200 °C. By adjusting and controlling the smoothness of the silicon corners 150, the silicon corners 150 wrapped by the first thermal oxide layer 130 sink slightly below the top surface of the cavity wafer 110.

[0048] Then, perform a second thermal oxidation process on the cavity wafer 110. The thickness and oxidation conditions of the second oxide layer are adopted as needed. For example, the reaction gases are also O2 and H2O, the oxidation temperature is 1100 °C, and the thickness of the second thermal oxide layer 140 formed is 2 μm, etc. The second thermal oxidation process and the first thermal oxidation process have a similar environment, making the entire process flow simple and easy to control, with high practical value.

[0049] During the second thermal oxidation process, since the silicon corners 150 already present a smooth morphology and sink slightly below the top highest surface, the micro-protrusions 160 formed by the second thermal oxidation are effectively offset. As Figure 4As shown, after secondary thermal oxidation, the 150 oxide layer at the silicon corner no longer has micro-protrusions 160, and the oxide layer surface for bonding is flat, which can meet the subsequent direct silicon-to-silicon bonding process and meet the requirements for the flatness of the bonding surface, facilitating the acquisition of a high-quality Cavity-SOI structure.

[0050] After secondary thermal oxidation, the inner wall of the cavity and the bonding surface of the cavity wafer 110 have a uniform thermal oxide layer, as Figure 5 shown. The cavity wafer 110 is directly bonded to another bonding wafer 170 through silicon-to-silicon bonding, and then thinned to the required thickness, as Figure 6 shown, completing the fabrication of the Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity.

[0051] The method for preparing the Cavity-SOI of the present invention has a simple and easily controllable process flow. The inner wall of the cavity and the bonding surface have a uniform thermal oxide layer, without involving deep cavity lithography and alignment bonding, being suitable for mass production, and having strong flexibility, capable of realizing structures that are difficult to achieve by traditional methods, meeting the complex and diverse application requirements of MEMS device manufacturing.

[0052] The above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and inventive concept of the present invention, makes equivalent substitutions or changes, and all should be covered within the protection scope of the present invention.

[0053] In the present invention, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "below" and "beneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.

Claims

1. A method for fabricating Cavity-SOI with a thermally oxidized layer on the inner wall of the cavity, characterized in that, include: S1, making a cavity on a wafer to obtain a cavity wafer (110); S2, performing a primary thermal oxidation process on the cavity wafer (110) to form a primary thermal oxidation layer (130); S3, removing the primary thermal oxide layer (130) by wet etching; S4, performing a secondary thermal oxidation process on the cavity wafer (110) to form a secondary thermal oxidation layer (140); S5. Bonding the cavity wafer (110) to another bonding wafer (170) to obtain a Cavity-SOI structure.

2. The manufacturing method of Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity according to claim 1, wherein, The wafer in S1 uses a silicon substrate (120).

3. A method for manufacturing Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity according to claim 2, wherein, In S1, a cavity is formed on the wafer, and the steps include: S11, obtaining an anchor point pattern using a photolithography process; S12. Based on the anchor point pattern, a deep silicon etching process is used to etch a deep cavity.

4. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: When a thermal oxidation process is performed in S2, the reaction gases are O2 and H2O.

5. A method for preparing Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity according to claim 4, characterized in that, When a thermal oxidation process is performed in S2, the oxidation temperature range is 1000° C. to 1200° C., wherein the silicon corner (150) wrapped by the primary thermal oxidation layer (130) sinks slightly below the top surface of the cavity wafer (110).

6. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 5, characterized in that: When the thermal oxidation process is performed once in S2, the oxidation temperature is 1100°C.

7. A method for fabricating Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity according to claim 1, characterized in that, The wet process in S3 adopts BOE wet process.

8. The method for preparing a Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: The thickness of the primary thermal oxidation layer (130) is adjusted according to the required thickness of the secondary thermal oxidation layer (140).

9. A method for preparing Cavity-SOI with a thermally oxidized layer covering the inner wall of the cavity according to claim 8, wherein The thickness of the primary thermal oxidation layer (130) ranges from 1 μm to 3 μm.

10. The method for preparing Cavity-SOI with a cavity inner wall covered with a thermal oxide layer according to claim 1, characterized in that: In S5, after the cavity wafer (110) is bonded to another bonding wafer (170), a thinning process is performed to obtain Cavity-SOI.

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