Three-dimensional stacked dynamic random access memory and preparation method thereof

Abstract

The invention discloses a three-dimensional stacked dynamic random access memory and a preparation method thereof. The three-dimensional stacked dynamic random access memory comprises a semiconductor substrate; the fin-type structure comprises a plurality of fin-type sub-structures which are sequentially stacked on the surface of the semiconductor substrate; the fin type substructure comprises a first end, a first part channel, a second part channel and a second end which are arranged in sequence along the length direction of the fin type structure; the second ends are P-type doped and are respectively used as N-type doped drain electrodes, and different drain electrodes are insulated and isolated from one another; the N-type doped source electrode is electrically contacted with the first end and is grounded; the first grid electrode is positioned above the first part of channel, and the second grid electrode is positioned above the second part of channel; the first grid electrode is used for accessing negative voltage to enable the first part of channel to accumulate holes to form P-type doping, and the second grid electrode is used for accessing positive voltage to enable the second part of channel to accumulate electrons to form N-type doping, so that the fin type substructure forms the FBFET with the NPNP structure along the length direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, and more particularly, to a three-dimensionally stacked dynamic random access memory (DRAM) and a preparation method thereof. BACKGROUND

[0002] As shown in Figure 1 , a circuit diagram of a memory cell is shown. Figure 1 At present, the memory cell of the DRAM mostly adopts a 1T1C (one transistor T and one capacitor C) structure as shown in Figure 1 . The gate of the transistor T is connected with a word line, the drain is connected with a bit line BL, and the source is connected with the capacitor C.

[0003] When the DRAM adopts the memory cell with the structure as shown in Figure 1 , the charge stored in the capacitor C will be consumed in each reading operation, and after each reading operation, a writing operation is needed to write the stored value into the memory cell again, and the reading form is destructive. Even if not read, the charge stored in the capacitor C will gradually leak from the transistor T due to the off-state leakage current of the transistor T, which will cause the stored information of the memory cell to be invalid. Therefore, the memory cell with the 1T1C structure needs a fixed refresh time to ensure the reliability of the stored data.

[0004] In recent years, in order to meet the requirements of industrial development, the size of the memory cell in the DRAM is continuously miniaturized. In the process of miniaturizing the size of the memory cell, in order to ensure the reliability of the stored data in the DRAM while keeping the refresh time not less than 64 milliseconds, the capacitance value of the capacitor C in the memory cell with the 1T1C structure cannot be continuously reduced. Although this problem can be alleviated by using a high width-depth ratio capacitor, the width-depth ratio cannot be infinitely increased, and therefore the size of the capacitor C limits the miniaturization of the memory cell in the DRAM. SUMMARY

[0005] Therefore, the present application provides a three-dimensionally stacked dynamic random access memory and a preparation method thereof, and the scheme is as follows:

[0006] The first aspect of the present application provides a three-dimensionally stacked dynamic random access memory, comprising:

[0007] a semiconductor substrate;

[0008] a fin-type structure comprising a plurality of fin-type sub-structures stacked in sequence on the surface of the semiconductor substrate; along the length direction of the fin-type structure, the fin-type sub-structure comprises a first end, a first part channel, a second part channel and a second end arranged in sequence; the second end is P-type doped to be used as a drain of N-type doping respectively, and the drains are insulated and separated from each other;

[0009] The source is N-doped, and is in electrical contact with the first end and is connected to ground;

[0010] The first gate is above the first part of the channel, and the second gate is above the second part of the channel;

[0011] The first gate is connected to a negative voltage, so that the first part of the channel accumulates holes to form P-doping, and the second gate is connected to a positive voltage, so that the second part of the channel accumulates electrons to form N-doping, so that the fin substructure forms a negative feedback field effect transistor with an NPNP structure along the length direction.

[0012] Optionally, in the dynamic random access memory, the length of the first part of the channel is not equal to the length of the second part of the channel.

[0013] Optionally, in the dynamic random access memory, along the length direction, the first part of the channel includes a plurality of first sub-channels arranged in sequence; and the first gate includes a plurality of first gates corresponding to the first sub-channels one by one.

[0014] And / or, along the length direction, the second part of the channel includes a plurality of second sub-channels arranged in sequence; and the second gate includes a plurality of second gates corresponding to the second sub-channels one by one.

[0015] Optionally, in the dynamic random access memory, the length of the second part of the channel is greater than the length of the first part of the channel.

[0016] Optionally, in the dynamic random access memory, along a direction of the semiconductor substrate pointing to the fin structure, the length of the second end of each fin substructure decreases in sequence, so that the second end forms a step structure respectively.

[0017] The second aspect of the present application provides a preparation method of the above dynamic random access memory, comprising:

[0018] Providing a semiconductor substrate;

[0019] Forming a fin structure on the semiconductor substrate, including a plurality of fin substructures stacked in sequence on the surface of the semiconductor substrate; along the length direction of the fin structure, the fin substructure includes a first end, a first part of the channel, a second part of the channel, and a second end arranged in sequence;

[0020] Forming an N-doped source connected to the first end, and a P-doped drain based on the second end; wherein the source is connected to ground; and the second end forms a drain respectively, and different drains are insulated and separated;

[0021] forming a gate structure including a first gate and a second gate, the first gate being above the first part of the channel, and the second gate being above the second part of the channel;

[0022] wherein the first gate is configured to access a negative voltage to cause the first part of the channel to accumulate holes to form a P-type doping, and the second gate is configured to access a positive voltage to cause the second part of the channel to accumulate electrons to form an N-type doping, so that the fin-type sub-structure forms a negative feedback field effect transistor of NPNP structure along the length direction.

[0023] Optionally, in the above preparation method, the adjacent fin-type sub-structures have a sacrificial layer therebetween.

[0024] Before forming the source and the drain, the method further comprises:

[0025] depositing a dummy gate, the dummy gate covering the first part of the channel and the second part of the channel, and exposing the first end and the second end, the dummy gate having opposite first and second side walls in the length direction;

[0026] forming a first isolation sidewall on the surface of the first side wall, and forming a second isolation sidewall on the surface of the second side wall, wherein the first isolation sidewall is configured to isolate the gate structure from the source, and the second isolation sidewall is configured to isolate the gate structure from the drain.

[0027] Optionally, in the above preparation method, the method of forming the drain comprises:

[0028] etching the second end, so that the length of the second end of each fin-type sub-structure decreases in sequence in the direction of the fin-type structure of the semiconductor substrate, so that the second end forms a step structure respectively;

[0029] after removing the sacrificial layer between the second ends, performing P-type doping on the second end to form the drain;

[0030] the method of forming the source comprises:

[0031] removing the sacrificial layer between the first ends;

[0032] epitaxially covering the N-type doped source of each first end.

[0033] Optionally, in the above preparation method, the method of forming the gate structure comprises:

[0034] removing the dummy gate and the remaining sacrificial layer;

[0035] forming a dielectric layer on the surface of the fin-type sub-structure between the first end and the second end;

[0036] depositing an insulating filling material in the first isolation sidewall and the second isolation sidewall, the insulating filling material covering the fin-type sub-structure whose surface is covered with the dielectric layer;

[0037] forming a gate isolation wall based on the insulating filling material, forming a first gate on the first part of the channel, and forming a second gate on the second part of the channel based on the gate isolation wall.

[0038] Optionally, in the preparation method, the method of forming the gate isolation wall comprises:

[0039] etching the insulating filling material to form at least a first gate isolation wall;

[0040] wherein the first gate is formed between the first isolation sidewall and the first gate sidewall, and the second gate is formed between the first gate isolation wall and the second isolation sidewall.

[0041] As can be seen from the above description, in the three-dimensional stacked dynamic random access memory and the preparation method thereof provided by the technical scheme, for each layer of fin-type substructure, a negative feedback field-effect transistor (FBFET) can be formed based on the NPNP structure, and thus each layer of fin-type substructure can be based on the corresponding FBFET as a 1T0C storage unit, and based on the plurality of layers of stacked fin-type substructures, a plurality of three-dimensional stacked 1T0C storage units can be formed. The 1T0C storage unit based on the FBFET has the advantages of a large storage window, a high on-off current ratio, low power consumption, high speed, and no capacitance. Therefore, compared with the conventional 1T1C storage unit, the storage unit in the DRAM of the present application does not need to be provided with a capacitor, avoiding the problem that the size of the storage unit cannot be further reduced due to the need to set the capacitor; and based on the plurality of three-dimensional stacked 1T0C storage units, the area of the DRAM can be reduced, and the integration of high-density storage units can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical scheme in the embodiments or related art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and those skilled in the art can obtain other drawings based on the provided drawings without creating any creative labor.

[0043] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0044] Figure 1A circuit diagram of a memory cell;

[0045] Figure 2 A schematic diagram of the principle of constructing a 1T0C memory cell by FBFET;

[0046] Figure 3 A three-dimensional view of a three-dimensionally stacked DRAM provided by an embodiment of the present application;

[0047] Figure 4 A front view of the DRAM shown in Figure 3

[0048] Figure 5 An output curve hysteresis diagram of FBFET;

[0049] Figure 6 A band diagram from point A to point B in Figure 5

[0050] Figure 7 A band diagram from point B to point C in Figure 5

[0051] Figure 8 A flowchart of a DRAM manufacturing method provided by an embodiment of the present application;

[0052] Figures 9-29 Product structure diagrams of a DRAM manufacturing method provided by an embodiment of the present application at different process steps.

[0053] Reference signs:

[0054] 10 - semiconductor substrate; 11 - fin structure; 12 - fin substructure; 131 - first end; 132 - second end; 141 - first part channel; 142 - second part channel; 151 - first sub-channel; 152 - second sub-channel; 17 - silicon oxide layer; 181 - active layer; 182 - sacrificial layer; 19 - dummy gate; 201 - first isolation sidewall; 202 - second isolation sidewall; 21 - first insulating layer; 22 - gate isolation wall; 221 - first gate isolation wall; 222 - second gate isolation wall; 23 - first dielectric layer; 24 - second dielectric layer; 25 - insulating filling material; 26 - second insulating layer; 27 - via hole; T - transistor; C - capacitor; BL - bit line; WL - word line; S - source; D - drain; G - gate structure; G1 - first gate; G2 - second gate; Via - contact hole; GND - ground. DETAILED DESCRIPTION

[0055] ​​​The embodiments in the present application will be described below in detail with the accompanying drawings of the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments in the present application, rather than all the embodiments in the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of the present application.

[0056] For DRAM using 1T1C memory cell, the size shrinkage is limited by the capacitor C. The capacitor C cannot keep the same shrinkage rate as the transistor T, and a minimum capacity is needed to store the charge to ensure stable storage data. Due to the existence of the capacitor C, the size shrinkage of the 1T1C memory cell is limited, which further limits the miniaturization and high-density design of DRAM.

[0057] In order to solve the above problems, 1T0C memory cell using FBFET is born. FBFET is a device based on positive feedback effect, with excellent sub-threshold swing and high on-off current ratio. Based on the NPNP doping structure, it can be used as a 1T0C memory cell for DRAM.

[0058] As shown in Figure 2 , the principle diagram of 1T0C memory cell using FBFET is shown. Figure 2 Figure 2 The upper diagram in the middle is the NPNP doping structure of FBFET. Figure 2 The lower diagram in the middle is the band diagram of FBFET, E C represents the conduction bottom, E V represents the valence band top. FBFET includes a source and a drain and a channel between the source and the drain. The source and the drain are respectively N-type heavily doped and P-type heavily doped. The channel includes N-type doped part and P-type doped part, thereby forming the NPNP doping structure as shown in the upper diagram in the middle. Figure 2

[0059] ​​The positive feedback effect of the FBFET is that the decrease of the barrier increases the current, and the increase of the current further decreases the barrier. The positive feedback effect generally exists in two aspects, one is the transfer curve, and the other is the output curve. When the gate is applied to the P-type doped channel or the N-type doped channel between the source and the drain, the size of the electron and hole barrier can be adjusted by the gate, which is very sensitive. When the gate voltage makes the barrier decrease to the threshold value, the positive feedback effect is triggered, and the barrier suddenly decreases, so the transfer curve is very steep. When the voltage is applied to the drain, as the drain voltage gradually increases, the drain hole barrier decreases, the holes in the P-type doped drain enter the P-type doped channel, the holes decrease the electron barrier of the N-type doped source, the electrons of the N-type doped source cross the barrier and enter the N-type doped channel, and the electrons decrease the hole barrier of the P-type doped drain, thereby triggering the positive feedback effect, and the barrier suddenly disappears, and the current suddenly increases. When the drain voltage decreases from large to small, the barrier does not suddenly change, but slowly forms. Therefore, the hysteresis effect is formed, so that the FBFET can be used as a 1T0C storage unit for DRAM.

[0060] However, in the conventional FBFET-based DRAM using planar integration, the storage unit area is still large, resulting in low storage density, and it is difficult to realize three-dimensional integration.

[0061] Therefore, embodiments of the present application provide a three-dimensionally stacked DRAM, which realizes three-dimensional stacking of multiple 1T0C storage units based on a fin field effect transistor (FINFET) architecture, thereby realizing three-dimensional stacking of FBFETs, and further realizing three-dimensional integration of storage units in the DRAM, reducing the storage unit area of the DRAM and improving the storage density.

[0062] In addition, the 1T0C storage unit based on the FBFET has the advantages of large storage window, high on-off current ratio, low power consumption, high speed, and no capacitor. Therefore, compared with the conventional 1T1C storage unit, the storage unit in the DRAM of the present application does not need to be provided with a capacitor, avoiding the problem that the size of the storage unit cannot be further reduced due to the need to set the capacitor. Moreover, based on multiple three-dimensionally stacked 1T0C storage units, the area of the DRAM can be reduced, and integration of high-density storage units can be realized.

[0063] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0064] Reference Figure 3 and Figure 4 , Figure 3 A three-dimensional view of a three-dimensionally stacked DRAM is provided for embodiments of the present application, Figure 4 for Figure 3a front view of a DRAM, the DRAM comprising:

[0065] a semiconductor substrate 10;

[0066] a fin-type structure 11 comprising a plurality of fin-type substructures 12 stacked in sequence on a surface of the semiconductor substrate 10; along a length direction X of the fin-type structure 11, the fin-type substructure 12 comprises a first end 131, a first part channel 141, a second part channel 142 and a second end 132 arranged in sequence; the second end 132 is P-type doped to be used as a drain D of N-type doped respectively, and different drains D are insulated and separated;

[0067] a source S of N-type doped, the source S being in electrical contact with the first end 131, and the source S being used for grounding;

[0068] a gate structure G comprising a first gate G1 and a second gate G2, the first gate G1 being located above the first part channel 141, and the second gate G2 being located above the second part channel 142;

[0069] wherein the first gate G1 is used to access a negative voltage, so that the first part channel 141 accumulates holes to form P-type doped, and the second gate G2 is used to access a positive voltage, so that the second part channel 142 accumulates electrons to form N-type doped, so that the fin-type substructure 12 forms a negative feedback field effect transistor of NPNP structure along the length direction X.

[0070] The first part channel 141 and the second part channel 142 of each layer fin-type substructure 12 are intrinsic semiconductors, which are non-doped structures. When the first gate G1 accesses a negative voltage, the negative voltage will attract holes, so that the first part channel 141 accumulates holes to form P-type doped. When the second gate G2 accesses a positive voltage, the positive voltage will attract electrons, so that the second part channel 142 accumulates electrons to form N-type doped. In this way, for any fin-type substructure 12, the source S, the first part channel 141, the second part channel 142 and the drain D are N-type doped, P-type doped, N-type doped and P-type doped in sequence, thereby forming a negative feedback field effect transistor of NPNP structure.

[0071] In the embodiments of the present application, the first part channel 141 and the second part channel 142 of each layer fin substructure 12 are intrinsic semiconductors, and the doping of the first part channel 141 and the second part channel 142 can be controlled by the voltage of the first gate G1 and the second gate G2, respectively, so that the dynamic adjustment of the conductive path can be realized. This method is more flexible than static doping, and can adjust the performance of the device in real time according to different working conditions. In addition, the hole concentration in the first part channel 141 and the electron concentration in the second part channel 142 can be accurately controlled by the voltage input by the first gate G1 and the second gate G2, respectively, so as to adjust the size and characteristics of the current, thereby improving the accuracy and response speed of the device.

[0072] Moreover, since the first part channel 141 and the second part channel 142 are intrinsic semiconductors, the channel region of the DRAM does not need a complex doping process, which can simplify the process flow of device preparation, reduce production cost, and also improve product yield.

[0073] In addition, in a high-temperature environment, the diffusion of the doping element will affect the performance of the device. The embodiments of the present application can control the doping type of the channel by the gate voltage, which can avoid this problem and improve the temperature stability of the device. Since the channel region does not need to be doped, the device performance fluctuation caused by uneven doping is reduced, thereby improving the reliability and consistency of the device.

[0074] In the embodiments of the present application, the semiconductor substrate 10 can be an SOI (Silicon on Insulator) substrate, and the two-layer stacked FBFET nanosheet can be prepared based on the SOI substrate to form a two-layer 1T0C memory cell stacked DRAM. The number of stacked layers of the fin substructure 12 in the fin structure 11 can be set according to requirements, and is not limited to the two-layer stacked structure shown in FIGS. 1 and 2. Figure 3 and Figure 4

[0075] As described above, in the three-dimensional stacked DRAM provided by the technical scheme of the present application, the FBFET with NPNP structure is formed by using the fin substructure 12, so that the FBFET can be used as the 1T0C memory cell. The technical scheme of the present application not only can realize the three-dimensional stacking of multiple 1T0C memory cells based on the FINFET architecture, but also can realize the three-dimensional stacking of the FBFET, and further realize the three-dimensional integration of the memory cell in the DRAM, thereby reducing the area of the memory cell of the DRAM and improving the storage density.

[0076] ​In addition, the 1T0C memory cell formed by the FBFET has the advantages of large storage window, high on-off current ratio, low power consumption, high speed, and no capacitance. Therefore, compared with the conventional 1T1C memory cell, the memory cell in the DRAM of the present application does not need to be provided with a capacitor, thereby avoiding the problem that the size of the memory cell cannot be further reduced due to the need to provide a capacitor. Moreover, based on the plurality of three-dimensionally stacked 1T0C memory cells, the area of the DRAM can be reduced, and the integration of high-density memory cells can be realized.

[0077] As described above, in the embodiments of the present application, since the source S and the second part channel 142 are both N-type doped, and the first part channel 141 and the drain D are both P-type doped, each fin-type substructure 12 can form an FBFET as a 1T0C memory cell. The plurality of stacked fin-type substructures 12 in the fin-type structure 11 can thus form a plurality of three-dimensionally stacked FBFETs as a plurality of three-dimensionally stacked 1T0C memory cells.

[0078] In one implementation of the embodiments of the present application, the length of the first part channel 141 and the second part channel 142 of each fin-type substructure 12 can be set to be different. Therefore, for the same fin-type substructure 12, the length of the first part channel 141 is set to be L1, and the length of the second part channel 142 is set to be L2, L1≠L2. At this time, for the same fin-type substructure 12, the channel length of the P-type channel (the first part channel 141) and the N-type channel (the second part channel 142) in the FBFET formed thereby are different. By differentiating the channel length of the N-type channel and the P-type channel in the FBFET, the device performance of the FBFET can be optimized, so as to improve the reliability and stability of the 1T0C memory cell and the DRAM.

[0079] In order to facilitate process preparation, in other implementations of the embodiments of the present application, the length of the first part channel 141 and the second part channel 142 of each fin-type substructure 12 can also be set to be equal, i.e., L1=L2.

[0080] On the basis of any of the above-mentioned implementations, in the length direction X, the first part channel 141 can include a first sub-channel 151, Figure 3 and Figure 4 In the above-mentioned manner, the first part channel 141 is taken as an example for illustration, and at this time, a first gate G1 is provided above the first part channel 141.

[0081] In other implementations, in the length direction X, the first part channel 141 can also include a plurality of first sub-channels 151 arranged in sequence; and the first gate can include a plurality of first gates G1 corresponding to the first sub-channels 151 one by one.

[0082] In the embodiments of the present application, the first part channel 141 can include one or more first sub-channels 151, and the number of the first sub-channels 151 is not limited in the embodiments of the present application.

[0083] In other embodiments, in the length direction X, as shown in Figure 3 or Figure 4 In the length direction X, the second part channel 142 can include one second sub-channel 152 or a plurality of second sub-channels 152 arranged in sequence.

[0084] If the second part channel 142 includes one second sub-channel 152, a second gate G2 is arranged above the second part channel 142, and if the second part channel 142 includes a plurality of second sub-channels 152, a plurality of second gates G2 corresponding to the second sub-channels 152 are arranged above the second part channel 142.

[0085] In the embodiments of the present application, the second part channel 142 can include one or more second sub-channels 152, and the number of the second sub-channels 152 is not limited in the embodiments of the present application.

[0086] The number of the first sub-channels 151 and the second sub-channels 152 can be set according to requirements, and by adjusting the number of the two sub-channels, the channel length ratio of the first part channel 141 and the second part channel 142 can be better adjusted, so as to better optimize the device performance of the FB-FET, and improve the reliability and stability of the 1T0C memory cell and the DRAM.

[0087] In Figure 3 and Figure 4 , the first part channel 141 includes the first sub-channel 151, and the second part channel 142 includes two second sub-channels 152, which are taken as examples for illustration, and a first gate G1 is arranged on the first part channel 141, and a second gate G2 is arranged above the second part channel 142 corresponding to the two second sub-channels 152. At this time, the DRAM has three gates. The three gates control the channel doping type of each layer FB-FET in the fin-type structure 11. The first gate G1 can control the first part channel 141 to realize multi-sub-accumulation, and the two second gates G2 control the second part channel 142 to be inverted, so as to form an FB-FET with an NPNP structure. The hysteresis effect of the transfer curve of the FB-FET can realize stable storage of data.

[0088] In the embodiments of the present application, preferably, the length of the second part channel 142 is greater than the length of the first part channel 141. At this time, the length of the N-type channel in the FB-FET is greater than the length of the P-type channel, that is, L1 is less than L2.

[0089] In the FBFET, when the length of the N-type channel is large, the resistance of the N-type channel is low, the electron mobility is high, and thus the current carrying capacity of the N-type channel is stronger; the P-type channel has low hole mobility, and when the length of the P-type channel is short, the impedance of the P-type channel can be reduced, and the conduction efficiency of the FBFET can be improved.

[0090] In addition, the longer N-type channel in the FBFET can form a conduction channel at a lower gate-source voltage, and can reduce the device opening voltage; and the shorter P-type channel can help to reach the protection state at a lower drain-source voltage, and improve the response speed of the device.

[0091] In addition, the longer N-type channel in the FBFET can form a conduction channel at a lower gate-source voltage, and can reduce the device opening voltage; and the shorter P-type channel can help to reach the protection state at a lower drain-source voltage, and improve the response speed of the device.

[0092] In the embodiment of the present application, in the direction of the semiconductor substrate 10 pointing to the fin structure 11, the length of the second end 132 of each fin substructure 12 decreases in turn, so that the second end 132 forms a step structure respectively. As shown in FIG. 1 and FIG. 2, for the fin substructure 12 with one layer, the length of the second end 132 of each fin substructure 12 decreases in turn, so that the second end 132 forms a step structure respectively. Figure 3 Figure 4 As shown in FIG. 3 and FIG. 4, for the fin substructure 12 with two layers, the length of the second end 132 of the fin substructure 12 close to the semiconductor substrate 10 is longer, and the length of the second end 132 of the fin substructure 12 above the fin substructure 12 is shorter. In this way, a two-stage step structure can be formed, and each second end 132 forms a step structure respectively.

[0093] The multi-stage step structure formed by the fin structure 11 at the second end 132 of each fin substructure 12 facilitates that each drain D is connected with the word line WL through a contact hole Via penetrating through the first insulating layer 21. Each gate can be connected with the bit line BL through a contact hole Via penetrating through the second insulating layer 26. The source S can be grounded (GND) through a contact hole Via penetrating through the first insulating layer 21.

[0094] As can be seen from the above description, the embodiment of the present application provides a new three-dimensionally stacked DRAM. The DRAM forms a plurality of three-dimensionally stacked FBFETs based on the FINFET framework, and the FBFETs can be used as 1T0C storage units, so as to realize the three-dimensional integration of the 1T0C storage units in the DRAM.

[0095] The working principle of the DRAM provided by the embodiment of the present application will be described below with reference to the device structure as shown in FIG. 3 and FIG. 4. Figures 5-7 Figure 5 The working principle of the DRAM provided by the embodiment of the present application will be described below with reference to the device structure as shown in FIG. 3 and FIG. 4.​​

[0096] refer to Figure 6 , Figure 5 The output hysteresis plot of the FBFET is shown. Figure 7 for Figure 5 Band diagram from point A to point B. Figure 6 for Figure 7 The band structure diagram from point B to point C. Figure 6 The solid line represents the energy band at point A, and the dashed line represents the energy band at point B. Figure 6 The solid line represents the energy band at point C, and the dashed line represents the energy band at point B.

[0097] When the DRAM is operating, the first gate G1 is connected to a negative voltage, and the two second gates G2 are connected to a positive voltage, so that the fin substructures 12 can form an NPNP FBFET. When a positive voltage is applied to the drain D, as... Figure 7 The energy band at point A is defined by the electron barrier on the left and the hole barrier on the right. Due to these barriers, the current at point A is very small, typically less than 10 Ω. -12 A. When the voltage at drain D continues to increase to point B, the band barrier will suddenly disappear due to positive feedback, as... Figure 8 The band structure diagram at point B is shown. Due to the disappearance of the potential barrier, the drain current will experience a sudden change, from 10... -12 The order of magnitude of A becomes 10. -4 The order of magnitude of A. And when the voltage at the drain D decreases from point B to point C, the energy band... Figure 8 As shown, the energy band does not change abruptly, so the current decreases slowly. Since the forward and reverse currents rise and fall at different rates, a hysteresis window is formed between the forward and reverse currents. This window can be used to store data: 0 is stored when the current is off, and 1 is stored when the current is on.

[0098] As can be seen from the above description, the DRAM provided in this application embodiment is a novel three-dimensional DRAM based on multi-layer 1T0C memory cell stacking, which overcomes the problem that traditional DRAM based on 1T1C memory cells is limited by the capacitor C in the memory cell and cannot continue to shrink in size, thus providing a new implementation method for the development of DRAM.

[0099] Compared to planar DRAM based on 1T0C memory cells, the technical solution of this application addresses the problem of excessive density, simplifies the stacking structure, and provides the possibility for continuously increasing DRAM chip density. This application example can control the doping type of the channel region using multiple dual-gate (one first gate G1 and one second gate G2) or multiple gates (such as a tri-gate structure with one first gate G1 and two second gates G2) to realize an NPNP FBFET device structure. The channel region can be left undoped, reducing trench doping processes.

[0100] Furthermore, the drain D can have a multi-step structure, so that the step structure corresponding to each drain D can be connected to the bit line BL through the corresponding contact hole Via, simplifying the structure of the bit line BL. In this embodiment, other graphic structures can also be used to connect the drain D and the bit line BL, and this embodiment does not limit this.

[0101] Based on the above embodiments, another embodiment of this application also provides a method for fabricating the three-dimensional stacked DRAM provided in any of the above embodiments, the fabrication method being as follows: Figure 8 As shown.

[0102] refer to Figures 9-29 , Figures 9-29 This is a schematic flowchart of a DRAM fabrication method provided in an embodiment of this application. The fabrication method includes:

[0103] Step S11: Provide a semiconductor substrate.

[0104] Step S12: Form a fin structure on a semiconductor substrate, including a plurality of fin substructures stacked sequentially on the surface of the semiconductor substrate; along the length direction of the fin structure, the fin substructure includes a first end, a first partial channel, a second partial channel and a second end arranged sequentially.

[0105] Step S13: Form an N-type doped source that is connected to the first end, and form a P-type doped drain based on the second end; wherein the source is used for grounding; and a drain is formed at the second end respectively, with insulation between different drains.

[0106] Step S14: Form a gate structure, including a first gate and a second gate, wherein the first gate is located above a first partial channel and the second gate is located above a second partial channel.

[0107] The first gate is used to apply a negative voltage, which allows holes to accumulate in the first part of the channel to form P-type doping. The second gate is used to apply a positive voltage, which allows electrons to accumulate in the second part of the channel to form N-type doping, so that the fin substructure forms an NPNP structure negative feedback field-effect transistor along the length direction.

[0108] The preparation method provided in this application embodiment can be used to prepare the DRAM provided in the above embodiment. It can prepare three-dimensionally stacked FBFETs in the DRAM, thereby forming a DRAM with multiple 1TOC memory cells.

[0109] The following section, in conjunction with device structure diagrams at different process stages, further illustrates the fabrication method provided in the embodiments of this application.

[0110] refer to Figure 9 , Figure 10This application provides a DRAM fabrication method with different process steps, and the fabrication method shown includes:

[0111] Step S101: As Figure 11 As shown, a semiconductor substrate 10 is provided.

[0112] In this embodiment, the semiconductor substrate 10 is a Si substrate as an example for illustration. Obviously, other semiconductor materials can also be used as substrates, such as gallium nitride, germanium, gallium arsenide and silicon carbide layers.

[0113] Step S102: As Figure 12 As shown, a silicon oxide layer 17 is formed on the surface of the semiconductor substrate 10.

[0114] A Si substrate and its surface silicon oxide layer 17 can form an SOI substrate.

[0115] Step S103: As Figure 13 As shown, multiple active layers 181 are deposited on the surface of silicon oxide layer 17, and a sacrificial layer 182 is present between adjacent active layers 181.

[0116] Optionally, the active layer 181 is an undoped intrinsic semiconductor, such as a Si layer. The sacrificial layer 182 can be a SiGe layer.

[0117] Step S104: As Figure 14 As shown, the stacked structure of the active layer 181 and the sacrificial layer 182 is etched to form a fin-shaped structure 11. The etched active layer 181 forms a fin-shaped substructure 12.

[0118] Step S105: As Figure 15 As shown, before forming the source and drain, the method further includes: depositing a dummy gate 19, which covers the first portion of the channel 141 and the second portion of the channel 142, and exposes the first end 131 and the second end 132; the dummy gate 19 has opposing first sidewalls and second sidewalls in the length direction X.

[0119] Alternatively, the material of the virtual gate 19 can be SiO2.

[0120] Step S106: As Figure 16 As shown, a first isolation sidewall 201 is formed on the surface of the first sidewall, and a second isolation sidewall 202 is formed on the second sidewall; wherein, the first isolation sidewall 201 is used to isolate the gate structure G from the source S, and the second isolation sidewall 202 is used to isolate the gate structure G from the drain D.

[0121] Optionally, the first isolation sidewall 201 and the second isolation sidewall 202 can be made of Si3N4. Si3N4 has good filling capacity and a low K value.

[0122] Step S107: The method for forming the drain D includes:

[0123] First, such as Figure 17 As shown, the second end 132 is etched in the direction from the semiconductor substrate 10 to the fin structure 11, so that the length of the second end 132 of each fin substructure 12 decreases sequentially, so that the second end 132 forms a step structure respectively.

[0124] Then as Figure 18 As shown, after removing the sacrificial layer 182 between the second ends 132, the second ends 132 are P-type doped to form the drain D. Optionally, the P-type doped drain D can be formed by boron doping the etched second ends 132. Further, the drain D can be heavily P-type doped.

[0125] Step S108: The method for forming the source includes:

[0126] First, such as Figure 19 As shown, the sacrificial layer 182 between the first ends 131 is removed;

[0127] Then, as Figure 20 As shown, the N-type doped source S at each of the first ends is epitaxially coated. The height of the source S is less than the height of the virtual gate 19.

[0128] Finally, as Figure 21 As shown, a first insulating layer 21 is formed on the source S and drain D. The first insulating layer 21 is located on the surface of the source S and covers each drain D. The first insulating layer 21 can be SiO2. The first insulating layer 21 is flush with the height of the virtual gate 19.

[0129] In this embodiment, the order in which the source S and the drain D are formed is not limited. The drain D can be formed first and then the source S can be formed, or the source S can be formed first and then the drain D can be formed.

[0130] Step S109: The method for forming the gate structure G includes:

[0131] First, such as Figure 20 and Figure 21 As shown, the dummy gate 19 and the remaining sacrificial layer 182 are removed. Figure 22 As shown, after removing the dummy gate 19, the fin substructure 12 and sacrificial layer 182 in the channel region are exposed, and then... Figure 23 As shown, the sacrificial layer 182 in the trench region is removed.

[0132] Then, a dielectric layer is formed on the surface of the fin-shaped substructure 12 between the first end 131 and the second end 132. This process specifically includes: Figure 24 andFigure 25 As shown, a first dielectric layer 23 and a second dielectric layer 24 are sequentially formed on the surface of the fin-shaped substructure 12 between the first end 131 and the second end 132. The first dielectric layer 23 can be SiO2. The second dielectric layer 24 is a high-k dielectric, such as HfO2. After the surfaces of two adjacent fin-shaped substructures 12 are covered with the first dielectric layer 23 and the second dielectric layer 24, a gap is maintained between the second dielectric layers 24 on the surfaces of the two adjacent fin-shaped substructures 12.

[0133] For example Figure 26 As shown, an insulating filler material 25 is deposited on the first isolation sidewall 201 and the second isolation sidewall 202, and the surface of the insulating filler material 25 is covered with a fin-shaped substructure 12 of dielectric layer. The insulating filler material 25 can be Si3N4.

[0134] Finally, as Figure 27 As shown, a gate isolation wall 22 is formed based on the insulating filler material 25, such as Figure 28 As shown, based on the gate isolation wall 22, a first gate G1 is formed on the first partial channel 141 and a second gate G2 is formed on the second partial channel 142 to form a gate structure G.

[0135] The method for forming the gate isolation wall 22 includes: etching the insulating filling material 25 to form at least a first gate isolation wall 221; wherein a first gate G1 is formed between the first isolation sidewall 201 and the first gate isolation wall 221, and a second gate G2 is formed between the first gate isolation wall 221 and the second isolation sidewall 202.

[0136] If the first portion of the channel 141 includes a plurality of first sub-channels 151 and / or the second portion of the channel 142 includes a plurality of second sub-channels 152, a second gate isolation wall 222 is formed simultaneously with the formation of the first gate isolation wall 221. Adjacent first gates G1 are isolated based on the corresponding second gate isolation wall 222, and adjacent second gates G2 are isolated based on the corresponding second gate isolation wall 222.

[0137] Each gate can be formed above the corresponding sub-channel region by depositing TiN. TiN has the functions of work function regulation and resistivity reduction, which can avoid the depletion effect of polysilicon gate, while ensuring good contact between the high-k dielectric material and the metal gate.

[0138] Step S110: As Figure 29 As shown, a second insulating layer 26 is deposited above each gate, and the second insulating layer 26 may be flush with the surface of the first insulating layer 21. The material of the second insulating layer 26 may be SiO2.

[0139] Step S111: As ​As shown, a through-hole 27 is formed that penetrates the insulating layer, and the source S, the first gate G1, the second gate G2 and each drain D are exposed through the corresponding through-hole 27.

[0140] Step S111: As ​ As shown, metal is deposited within the through-hole 27 to form a contact hole Via for electrical connection. The metal deposited within the through-hole 27 can be tungsten.

[0141] In this embodiment of the application, a two-layer stacked fin substructure 12 is used as an example for illustration. It can form a stacked structure of two layers of 1T0C memory cells. Obviously, the DRAM can be set to include a stacked structure of more than two layers according to the requirements. Theoretically, if the process conditions allow, a stacked structure of 64 layers or even more can be made. This embodiment of the application does not limit this.

[0142] In DRAM fabrication methods, deep hole etching and lateral etching can be performed as needed to obtain the desired pattern structure.

[0143] In this design, both the source (S) and drain (D) are heavily doped. Since the doping concentration in the channel region has a certain impact on the storage window, it is preferable that the channel region is an undoped intrinsic semiconductor. This not only avoids the influence of channel region doping on the window region, but also avoids the increased process difficulty caused by channel region doping, thus simplifying the fabrication process.

[0144] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The implementation methods provided in this application can be combined with each other without contradiction.

[0145] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0146] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0147] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0148] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A three-dimensional stacked dynamic random access memory, characterized in that, include: Semiconductor substrate; The fin structure includes a plurality of fin substructures stacked sequentially on the surface of the semiconductor substrate; Along the length of the fin structure, the fin substructure includes a first end, a first channel, a second channel, and a second end arranged in sequence; the second end is P-type doped to serve as N-type doped drains, and the different drains are insulated from each other. The source electrode is an N-type doped electrode, which is electrically connected to the first terminal and is used for grounding. A first gate and a second gate, wherein the first gate is located above the first portion of the channel and the second gate is located above the second portion of the channel; Wherein, the first gate is used to apply a negative voltage, so that holes accumulate in the first part of the channel to form P-type doping, and the second gate is used to apply a positive voltage, so that electrons accumulate in the second part of the channel to form N-type doping, so that the fin substructure forms an NPNP structure negative feedback field-effect transistor along the length direction.

2. The dynamic random access memory according to claim 1, characterized in that, The lengths of the first part of the channel and the second part of the channel are not equal.

3. The dynamic random access memory according to claim 2, characterized in that, In the length direction, the first portion of the channel includes a plurality of first sub-channels arranged in sequence; the first gate includes a plurality of first gates that are one-to-one opposite to the first sub-channels. And / or, in the length direction, the second portion of the channel includes a plurality of second sub-channels arranged in sequence; the second gate includes a plurality of second gates that are one-to-one opposite to the second sub-channels.

4. The dynamic random access memory according to claim 2, characterized in that, The length of the second part of the channel is greater than the length of the first part of the channel.

5. The dynamic random access memory according to claim 1, characterized in that, In the direction of the semiconductor substrate pointing towards the fin structure, the length of the second end of each fin substructure decreases sequentially, so that the second end respectively forms a stepped structure.

6. A method for fabricating a dynamic random access memory as described in any one of claims 1-5, characterized in that, include: Provide semiconductor substrates; A fin structure is formed on the semiconductor substrate, comprising a plurality of fin substructures stacked sequentially on the surface of the semiconductor substrate; Along the length of the fin structure, the fin substructure includes a first end, a first channel, a second channel, and a second end arranged sequentially. An N-type doped source is formed, which is connected to the first end, and a P-type doped drain is formed based on the second end; wherein the source is used for grounding; and a drain is formed at each of the second ends, with the different drains being insulated from each other. A gate structure is formed, including a first gate and a second gate, wherein the first gate is located above the first portion of the channel and the second gate is located above the second portion of the channel; Wherein, the first gate is used to apply a negative voltage, so that holes accumulate in the first part of the channel to form P-type doping, and the second gate is used to apply a positive voltage, so that electrons accumulate in the second part of the channel to form N-type doping, so that the fin substructure forms an NPNP structure negative feedback field-effect transistor along the length direction.

7. The preparation method according to claim 6, characterized in that, A sacrificial layer exists between adjacent fin-shaped substructures; Before forming the source and the drain, the process also includes: A dummy gate is deposited, the dummy gate covering the first portion of the channel and the second portion of the channel, and exposing the first end and the second end; the dummy gate has opposing first sidewalls and second sidewalls in the length direction; A first isolation sidewall is formed on the surface of the first sidewall, and a second isolation sidewall is formed on the second sidewall; wherein the first isolation sidewall is used to isolate the gate structure from the source, and the second isolation sidewall is used to isolate the gate structure from the drain.

8. The preparation method according to claim 7, characterized in that, The method of forming the drain includes: The second end is etched in the direction of the semiconductor substrate pointing to the fin structure, so that the length of the second end of each fin substructure decreases sequentially, so that the second end forms a stepped structure respectively; After removing the sacrificial layer between the second ends, the second ends are P-type doped to form the drain. The method for forming the source includes: Remove the sacrificial layer between the first ends; The source electrode is epitaxially coated with the N-type doped portion of each of the first ends.

9. The preparation method according to claim 7, characterized in that, The method of forming the gate structure includes: Remove the virtual gate and the remaining sacrificial layer; A dielectric layer is formed on the surface of the fin-shaped substructure between the first end and the second end; An insulating filler material is deposited between the first isolation sidewall and the second isolation sidewall, and the surface of the insulating filler material is covered with the fin-shaped substructure of the dielectric layer. A gate isolation wall is formed based on the insulating filler material, and a first gate is formed on the first portion of the channel based on the gate isolation wall, and a second gate is formed on the second portion of the channel.

10. The preparation method according to claim 9, characterized in that, The method of forming the gate isolation wall includes: Etch the insulating filler material to form at least a first gate isolation wall; A first gate is formed between the first isolation sidewall and the first gate sidewall, and a second gate is formed between the first gate isolation wall and the second isolation sidewall.

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