Insulated gate bipolar transistor (IGBT)
By employing a ring-shaped gate electrode and emitter contact structure in the IGBT, the problem of insufficient open-circuit withstand capability during IGBT turn-off is solved, thereby improving the open-circuit withstand capability and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-08
- Publication Date
- 2026-03-27
AI Technical Summary
Existing IGBTs have insufficient short-circuit withstand capability during turn-off and are easily damaged.
A ring-shaped gate electrode and emitter contact structure was designed. By setting the ring-shaped gate electrode and emitter contact in the gate connection area, the hole discharge efficiency was improved, current concentration was avoided, and the fault tolerance of the IGBT was enhanced.
This improves the IGBT's open-circuit withstand capability, reduces the incidence of gate breakdown voltage failure, and enhances the device's reliability.
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Figure CN121751660A_ABST
Abstract
Description
[0001] Related applications
[0002] This application claims priority to Japanese Patent Application No. 2024-164811 (filed on September 24, 2024). This application incorporates the entire contents of that basic application by reference. Technical Field
[0003] The implementation method involves IGBTs. Background Technology
[0004] As a type of semiconductor device used for power control, the IGBT (insulated gate bipolar transistor) has been developed. For the IGBT, there is a desire to improve its short-circuit withstand capability as a form of breakdown resistance during turn-off. Summary of the Invention
[0005] An IGBT according to an embodiment includes: a collector electrode; a semiconductor portion disposed on the collector electrode; a plurality of emitter electrodes disposed on a portion of the semiconductor portion and separated from each other in a first direction; a gate wiring disposed between the emitter electrodes in the first direction; a gate electrode having two first portions arranged in a second direction intersecting the first direction and extending in the first direction, and a second portion connecting the head ends of the two first portions to each other, the gate electrode being connected to the gate wiring and insulated from the semiconductor portion; and an emitter contact having its upper end connected to the emitter electrode and its lower end connected to a portion between the region directly below the gate wiring in the semiconductor portion and the second portion.
[0006] According to the implementation method, it is possible to provide IGBTs that can improve the fault tolerance. Attached Figure Description
[0007] Figure 1 A top view showing the IGBT of the first embodiment.
[0008] Figure 2 To show Figure 1 A magnified top view of area A.
[0009] Figure 3 For along Figure 2 A cross-sectional view of line B-B'.
[0010] Figure 4 For along Figure 2 A cross-sectional view of the C-C' line.
[0011] Figure 5 A cross-sectional view illustrating the operation of the IGBT in the first embodiment.
[0012] Figure 6 A plan view of the IGBT for the comparative example is shown.
[0013] Figure 7 A plan view of the IGBT according to the second embodiment is shown.
[0014] Figure 8 A plan view of the IGBT according to the third embodiment is shown.
[0015] Figure Labels
[0016] 1, 2, 3: IGBT; 10: Collector electrode; 20: Semiconductor section; 21: Collector layer (first semiconductor layer); 22: Drift layer (second semiconductor layer); 22a: First layer; 22b: Second layer; 23: Base layer (third semiconductor layer); 24: Emitter layer (fourth semiconductor layer); 30: Insulating film; 40: Emitter electrode; 41: Trench electrode; 42: Trench insulating film; 43, 44: Emitter plugs; 50: Gate wiring; 51: Gate pad; 52: Gate electrode; 52a: Part 1; 52b: Part 2; 53: Gate insulating film; 55: Internal gate wiring; 55a: Opening; 56: Gate plug; 60: Emitter contact; 61: Emitter contact; 101: IGBT; R1: Power-on area; R2: Gate connection area; h: Hole. Detailed Implementation
[0017] <First Implementation>
[0018] Figure 1 This is a top view showing the IGBT of this embodiment.
[0019] Figure 2 To show Figure 1 A magnified top view of area A.
[0020] Figure 3 For along Figure 2 A cross-sectional view of line B-B'.
[0021] Figure 4 For along Figure 2 A cross-sectional view of the C-C' line.
[0022] Furthermore, all figures are schematic and have been emphasized or simplified as appropriate. For example, in Figure 2 The insulation portion has been omitted. The same applies to the other diagrams described later.
[0023] like Figures 1 to 4As shown, in the IGBT1 of this embodiment, a collector electrode 10, a semiconductor portion 20, an insulating film 30, a plurality of emitter electrodes 40, and a gate wiring 50 are provided. The collector electrode 10 is disposed on one surface of the semiconductor portion 20, and the emitter electrodes 40 and the gate wiring 50 are disposed on the other surface of the semiconductor portion 20.
[0024] Collector electrode 10 is disposed on the entire lower surface of semiconductor portion 20 and is in contact with semiconductor portion 20. Insulating film 30 is disposed on the entire upper surface of semiconductor portion 20. A plurality of emitter electrodes 40 are disposed on a portion of insulating film 30 in a mutually separated manner. Gate wiring 50 is disposed on a portion of the insulating film 30 in which no emitter electrodes 40 are disposed.
[0025] like Figure 1 As shown, the emitter electrodes 40 are disposed in the cell regions of IGBT1, excluding the end regions, and are arranged, for example, along one direction. Hereinafter, for ease of explanation, an XYZ orthogonal coordinate system will be used. The direction from the collector electrode 10 towards the emitter electrode 40 will be defined as the "Z direction," the direction in which multiple emitter electrodes 40 are arranged will be defined as the "X direction," and the direction orthogonal to both the Z and X directions will be defined as the "Y direction." Furthermore, although the Z direction is also referred to as "up" and its opposite as "down," this is merely for convenience and is independent of the direction of gravity.
[0026] Viewed from the Z direction, each emitter electrode 40 is a rectangle whose length in the Y direction is longer than its length in the X direction. Viewed from the Z direction, the gate wiring 50 is, for example, a ladder-like shape surrounding each emitter electrode 40. Alternatively, the emitter electrodes 40 can be arranged in a matrix along both the X and Y directions. In this case, viewed from the Z direction, the gate wiring 50 can be a lattice-like shape surrounding each emitter electrode 40. In the gate wiring 50, gate pads 51 are provided at the corners of the cell regions.
[0027] like Figure 2 As shown, in the cell region of IGBT1, the area directly below the center of the emitter electrode 40 in the X direction is designated as the "current-carrying region R1". In the current-carrying region R1, current can flow from the collector electrode 10 through the semiconductor portion 20 to the emitter electrode 40. Additionally, in the cell region, the area directly below the gate wiring 50 and the area directly below the gate wiring 50 in the emitter electrode 40 are designated as the "gate connection region R2". In the gate connection region R2, the gate electrode 52, described later, is connected to the gate wiring 50. Furthermore, in this specification, "connection" means electrical connection. In the cell region, the current-carrying region R1 and the gate connection region R2 are arranged alternately along the X direction.
[0028] The gate electrode 52 is configured to span the energized region R1 and the gate connection region R2. When viewed from the Z direction, the gate electrode 52 has a loop shape. That is, the gate electrode 52 has two first portions 52a, mainly disposed in the energized region R1 and extending in the X direction; and a second portion 52b, disposed in the gate connection region R2 and extending in the Y direction, connecting the head ends of the two first portions 52a on the gate connection region R2 side to each other.
[0029] like Figure 2 and Figure 3 As shown, in the energized region R1, a trench electrode 41, a trench insulating film 42, a first portion 52a of a gate electrode 52, and a gate insulating film 53 are disposed within the semiconductor portion 20. Furthermore, an emitter plug 43 and an emitter plug 44 are disposed within the insulating film 30. The gate insulating film 53 is disposed around the gate electrode 52, insulating the gate electrode 52 from the semiconductor portion 20. The emitter electrode 40 is connected to the trench electrode 41 via the emitter plug 43. Additionally, the emitter electrode 40 is connected to the semiconductor portion 20 via the emitter plug 44.
[0030] Multiple trench electrodes 41 are provided and arranged along the Y direction. Each trench electrode 41 extends in the X direction. A trench insulating film 42 is disposed around the trench electrodes 41 to insulate the trench electrodes 41 from the semiconductor portion 20. The first portion 52a of the gate electrode 52 is arranged in a manner that it is inserted into the arrangement of the trench electrodes 41.
[0031] Multiple trench electrodes 41 are disposed on the inner side of the ring of the gate electrode 52 and between two adjacent gate electrodes 52 in the Y direction. Figure 2 In the example shown, two trench electrodes 41 are disposed inside the ring of the gate electrode 52, and two trench electrodes 41 are disposed between the two gate electrodes 52, but this is not a limitation. Three or more trench electrodes 41 may also be disposed inside the ring of the gate electrode 52 and between the gate electrodes 52, or no trench electrodes 41 may be disposed inside the ring of the gate electrode 52 or between the gate electrodes 52.
[0032] like Figure 2 and Figure 4 As shown, in the gate connection region R2, a second portion 52b of the gate electrode 52 and a gate insulating film 53 are disposed within the semiconductor portion 20. Additionally, an internal gate wiring 55, a gate plug 56, and an emitter contact 60 are disposed within the insulating film 30. The gate wiring 50 is connected to the internal gate wiring 55 via the gate plug 56. The internal gate wiring 55 is connected to the second portion 52b of the gate electrode 52.
[0033] An opening 55a is formed in the internal gate wiring 55. An emitter contact 60 penetrates the opening 55a of the internal gate wiring 55 in the Z direction. The upper end of the emitter contact 60 is connected to the emitter electrode 40, and the lower end of the emitter contact 60 is connected to the semiconductor portion 20.
[0034] like Figure 2 As shown, in this embodiment, in the gate connection region R2, a plurality of emitter contacts 60 are arranged, for example, at equal intervals along the Y direction. Each emitter contact 60 is approximately cylindrical in shape with its central axis extending in the Z direction. The emitter contacts 60 are disposed between two gate electrodes 52 located directly below two emitter electrodes 40 separated in the X direction.
[0035] A portion of the emitter contacts 60 are connected between the region directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52. Other emitter contacts 60 are connected between the trench electrode 41 disposed between the gate electrodes 52 and the region directly below the gate wiring 50 in the semiconductor portion 20.
[0036] like Figure 3 and Figure 4 As shown, in the semiconductor section 20, a conductivity type of p is provided. + 21. Collector layer of type n, drift layer of type p. + The base layer 23 is of shape and the conductivity type is n. + The emitter layer 24 is of type n. A first layer 22a of type n conductivity and a second layer of type n conductivity are disposed in the drift layer 22. － The second layer of the shape, 22b.
[0037] In addition, the record "n + "Type" indicates that the carrier concentration is higher than that recorded as "n-type". － "Type" indicates that the carrier concentration is lower than that recorded as "n-type". Additionally, "n" + Type", n-type", n － The term "type" is also collectively referred to as "n-type". The same applies to p-type. "Carrier concentration" refers to the concentration of impurities that contribute to the conductivity of a semiconductor. When a part contains both acceptor and donor impurities, it refers to the effective concentration after removing the offsetting amount.
[0038] Collector layer 21 is connected to collector electrode 10. The first layer 22a of drift layer 22 is disposed on and connected to collector layer 21. The second layer 22b of drift layer 22 is disposed on the first layer 22a. Base layer 23 is disposed on and connected to drift layer 22. In the energized region R1, emitter layer 24 is disposed on a portion of base layer 23. Emitter layer 24 is connected to gate insulating film 53 and faces the first portion 52a of gate electrode 52 across gate insulating film 53. Trench electrode 41 and trench insulating film 42, gate electrode 52 and gate insulating film 53 are disposed within base layer 23.
[0039] In the energized region R1, the emitter plug 44 is connected to the base layer 23 and the emitter layer 24. In other words, in the energized region R1, the base layer 23 and the emitter layer 24 are connected to the emitter electrode 40 via the emitter plug 44. In the gate connection region R2, the emitter contact 60 is connected to the base layer 23. In other words, in the gate connection region R2, the base layer 23 is connected to the emitter electrode 40 via the emitter contact 60. In the gate connection region R2, the gate electrode 52 is connected to the gate wiring 50 via the internal gate wiring 55 and the gate plug 56.
[0040] The following section provides examples of materials for each part.
[0041] As described above, the semiconductor portion 20 comprises, for example, monocrystalline silicon. The insulating film 30 comprises, for example, silicon oxide (SiO2). The internal gate wiring 55 comprises, for example, polycrystalline silicon. The collector electrode 10, the emitter electrode 40, and the gate wiring 50 comprise, for example, one or more materials selected from the group consisting of aluminum (Al), aluminum-copper alloy (AlCu), aluminum silicide (AlSi), titanium (Ti), and titanium nitride (TiN). The emitter contact 60, emitter plug 43, emitter plug 44, and gate plug 56 comprise, for example, one or more materials selected from the group consisting of titanium (Ti), titanium nitride (TiN), and tungsten (W).
[0042] Next, the operation of IGBT1 in this embodiment will be described.
[0043] Figure 5 A cross-sectional view illustrating the operation of the IGBT in this embodiment.
[0044] Figure 5 Showing with Figure 4 Same cross-section.
[0045] like Figure 5As shown, when IGBT1 is turned off, holes h, acting as charge carriers, enter the semiconductor portion 20. Holes h entering the energized region R1 move to the emitter electrode 40 via the emitter plug 44 and are discharged to the outside of IGBT1. Holes h entering the gate connection region R2 move to the emitter electrode 40 via the emitter contact 60 and are discharged to the outside of IGBT1.
[0046] Next, the effects of this implementation method will be explained.
[0047] In this embodiment, an emitter contact 60 is provided outside the annular gate electrode 52 and the gate insulating film 53 in the gate connection region R2. Therefore, holes h within the gate connection region R2 are discharged to the emitter electrode 40 via the emitter contact 60. Consequently, current is less likely to concentrate during turn-off, and the IGBT1 is less prone to breakdown. Therefore, the IGBT1 of this embodiment has high open-circuit tolerance.
[0048] Furthermore, in the IGBT1 of this embodiment, the gate electrode 52 is formed in a ring shape. Therefore, compared to the case where the gate electrode 52 is formed in a straight line, the gate withstand voltage is higher. That is, experiments have shown that when the gate electrode 52 has a second portion 52b, the gate withstand voltage failure rate is sometimes lower compared to the case where the gate electrode 52 is formed only by the first portion 52a without the second portion 52b.
[0049] <Comparative Example>
[0050] Figure 6 A plan view of the IGBT for the comparative example is shown.
[0051] like Figure 6 As shown, in the IGBT 101 of this comparative example, there is no emitter contact 60. Therefore, when the IGBT 101 is turned off, the holes h that have entered the gate connection region R2 need to move to the energized region R1 before being discharged to the emitter electrode 40 via the emitter plug 44.
[0052] However, because the movement of some holes h into the gate connection region R2 is blocked by the annular gate electrode 52 and the gate insulating film 53, the movement distance to the emitter plug 44 becomes longer. Therefore, the emission of holes h is suppressed. As a result, the current concentrates in the portion of the gate connection region R2 where holes h remain, and the IGBT 101 is very likely to break down.
[0053] <Second Implementation Method>
[0054] Figure 7 This is a plan view of the IGBT according to this embodiment.
[0055] like Figure 7As shown, the IGBT2 of this embodiment differs from the first embodiment in the configuration of the emitter contact 60. In the IGBT2, when viewed from the Z direction, the emitter contact 60 is not located between the portion of the gate electrode 52 in the semiconductor portion 20 and the gate wiring 50, but is only located between the gate electrode 52 and the gate wiring 50 in the semiconductor portion 20. That is, in this embodiment, the lower end of the emitter contact 60 is only connected to the portion between the region directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52.
[0056] According to this embodiment, holes h between the region directly below the gate wiring 50 in the semiconductor portion 20 and the gate electrode 52 are easily discharged via the emitter contact 60. Additionally, holes h between the region directly below the gate wiring 50 in the semiconductor portion 20 and the portion between the gate electrode 52 in the Y direction are easily discharged via the emitter plug 44. This achieves the same effect as in the first embodiment. The structure, operation, and effects of this embodiment other than those described above are the same as in the first embodiment.
[0057] <Third Implementation Method>
[0058] Figure 8 This is a plan view of the IGBT according to this embodiment.
[0059] like Figure 8 As shown, the emitter contact 61 of the IGBT3 in this embodiment has a different shape compared to the first embodiment.
[0060] like Figure 8 As shown, an emitter contact 61 is provided in the IGBT3. The emitter contact 61 is plate-shaped, with its length in the Y direction longer than its length in the X direction. The upper end of the emitter contact 61 is connected to the emitter electrode 40, and the lower end of the emitter contact 61 is connected to the portion between the area directly below the gate wiring 50 in the semiconductor portion 20 and the second portion 52b of the gate electrode 52. The structure, operation, and effects of this embodiment other than those described above are the same as those of the first embodiment.
[0061] Based on the implementation method described above, it is possible to realize an IGBT that can improve the fault tolerance.
[0062] The foregoing has described several embodiments of the present invention, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention as described in the claims and its equivalents. Furthermore, the above embodiments can also be implemented in combination with each other.
[0063] For example, in the embodiments described above, the p-type and n-type can be reversed to form a p-channel IGBT. In this case, the emitter contact functions as a contact for discharging electrons.
[0064] The present invention includes the following methods.
[0065] (Postscript 1)
[0066] An IGBT has the following characteristics:
[0067] Collector electrode;
[0068] The semiconductor portion is disposed on the collector electrode;
[0069] Multiple emitter electrodes are disposed on a portion of the semiconductor portion and are separated from each other in a first direction;
[0070] A gate wiring is disposed between the emitter electrodes in the first direction;
[0071] A gate electrode has two first portions arranged in a second direction intersecting the first direction and extending in the first direction, and a second portion connecting the head ends of the two first portions to each other. This gate electrode is connected to the gate wiring and is insulated from the semiconductor portion.
[0072] An emitter contact, the upper end of which is connected to the emitter electrode, and the lower end of which is connected to the portion between the area directly below the gate wiring in the semiconductor portion and the second portion.
[0073] (Postscript 2)
[0074] According to the IGBT described in Appendix 1, wherein,
[0075] When viewed from above, the emitter contact is positioned between the gate electrode and the gate wiring.
[0076] (Note 3)
[0077] According to Appendix 2, the IGBT, wherein,
[0078] A plurality of gate electrodes are disposed along the second direction.
[0079] When viewed from above, the emitter contact is also disposed between the portion of the semiconductor portion between the gate electrode and the gate wiring.
[0080] (Note 4)
[0081] According to any one of Appendices 1 to 3, the IGBT wherein,
[0082] The emitter contacts are provided in multiple quantities and arranged along the second direction.
[0083] (Note 5)
[0084] According to any one of Appendices 1 to 3, the IGBT wherein,
[0085] The length of the emitter contact in the second direction is longer than the length of the emitter contact in the first direction.
[0086] (Note 6)
[0087] According to any one of Appendices 1 to 5, the IGBT wherein,
[0088] A plurality of gate electrodes are disposed along the second direction.
[0089] This IGBT also features:
[0090] A first trench electrode is disposed within the semiconductor portion and between the gate electrodes in the second direction, and is connected to the emitter electrode; and
[0091] The first plug has its upper end connected to the emitter electrode and its lower end connected to the portion between the gate electrode and the first trench electrode in the semiconductor portion.
[0092] (Note 7)
[0093] According to Appendix 6, the IGBT also has the following features:
[0094] A second trench electrode is disposed within the semiconductor portion between the two first portions belonging to one of the gate electrodes and connected to the emitter electrode; and
[0095] The second plug has its upper end connected to the emitter electrode and its lower end connected to the portion between the gate electrode and the second trench electrode in the semiconductor portion.
[0096] (Note 8)
[0097] According to any one of Appendices 1 to 7, the IGBT wherein,
[0098] The semiconductor portion has:
[0099] The first semiconductor layer of the p-type is connected to the collector electrode;
[0100] The second semiconductor layer of type n is disposed on the first semiconductor layer;
[0101] A third p-type semiconductor layer is disposed on the second semiconductor layer and connected to the emitter contact; and
[0102] The fourth semiconductor layer of the n-type is disposed on a portion of the third semiconductor layer, is opposite to the first portion across the gate insulating film, and is connected to the emitter electrode.
Claims
1. An IGBT, comprising: Collector electrode; The semiconductor portion is disposed on the collector electrode; Multiple emitter electrodes are disposed on a portion of the semiconductor portion and are separated from each other in a first direction; A gate wiring is disposed between the emitter electrodes in the first direction; A gate electrode has two first portions arranged in a second direction intersecting the first direction and extending in the first direction, and a second portion connecting the head ends of the two first portions to each other. This gate electrode is connected to the gate wiring and is insulated from the semiconductor portion. An emitter contact, the upper end of which is connected to the emitter electrode, and the lower end of which is connected to the portion between the area directly below the gate wiring in the semiconductor portion and the second portion.
2. The IGBT according to claim 1, wherein, When viewed from above, the emitter contact is positioned between the gate electrode and the gate wiring.
3. The IGBT according to claim 2, wherein, A plurality of gate electrodes are disposed along the second direction. When viewed from above, the emitter contact is also disposed between the portion of the semiconductor portion between the gate electrode and the gate wiring.
4. The IGBT according to claim 1, wherein, The emitter contacts are provided in multiple quantities and arranged along the second direction.
5. The IGBT according to claim 1, wherein, The length of the emitter contact in the second direction is longer than the length of the emitter contact in the first direction.
6. The IGBT according to claim 1, wherein, A plurality of gate electrodes are disposed along the second direction. This IGBT also features: The first trench electrode is disposed between the gate electrodes in the second direction within the semiconductor portion and is connected to the emitter electrode; as well as The first plug has its upper end connected to the emitter electrode and its lower end connected to the portion between the gate electrode and the first trench electrode in the semiconductor portion.
7. The IGBT according to claim 6 further comprises: A second trench electrode is disposed within the semiconductor portion between the two first portions belonging to one of the gate electrodes and connected to the emitter electrode; and The second plug has its upper end connected to the emitter electrode and its lower end connected to the portion between the gate electrode and the second trench electrode in the semiconductor portion.
8. The IGBT according to any one of claims 1 to 7, wherein, The semiconductor portion has: The first semiconductor layer of the p-type is connected to the collector electrode; The second semiconductor layer of type n is disposed on the first semiconductor layer; The third semiconductor layer of the p-type is disposed on the second semiconductor layer and connected to the emitter contact; as well as The fourth semiconductor layer of the n-type is disposed on a portion of the third semiconductor layer, is opposite to the first portion across the gate insulating film, and is connected to the emitter electrode.
Citation Information
Patent Citations
Graded-index elements and phase elements for in-fiber beam shaping and switching
JP2024164811A