Multi-bit trigger design method for standard cell library and scan chain
By placing the single-bit flip-flop with the lowest flip-flop rate at the last position in a multi-bit flip-flop and arranging them in descending order of flip-flop rate, the problem of high dynamic power consumption in multi-bit flip-flops during DFT testing is solved, thus achieving power consumption optimization.
Patent Information
- Application Number
- CN202511701427.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-19
- Publication Date
- 2026-04-14
AI Technical Summary
In existing technologies, multi-bit flip-flops consume a lot of dynamic power during DFT testing, mainly because the random arrangement of individual single-bit flip-flops leads to an uneven flip-flop rate, resulting in increased power consumption.
By setting the arrangement order of multi-bit flip-flops, the single-bit flip-flop with the lowest flip-flop rate is placed at the last position and arranged in descending order of flip-flop rate, and then connected in series to form a scan chain, the arrangement order of single-bit flip-flops is optimized to reduce dynamic power consumption.
It effectively reduces the dynamic power consumption of DFT, optimizes power signoff, and lowers the overall power consumption of multi-bit flip-flops.
Smart Images
Figure CN121864060A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a design method and scan chain for multi-bit flip-flops used in standard cell libraries. Background Technology
[0002] A multi-bit flip-flop (FF) refers to a standard cell library that integrates multiple (typically 2, 4, or 8) independent, functionally identical single-bit flip-flops into a single standard cell. Multi-bit flip-flops share clock, reset, and scan chain control signals.
[0003] Currently, when IP vendors perform DFT (Design for Testability) testing on standard cell libraries, the individual single-bit flip-flops in multi-bit flip-flops are often arranged in a random combination, which consumes a lot of DFT dynamic power.
[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this invention is to provide a design method and scan chain for multi-bit flip-flops in standard cell libraries to solve the problem of excessive DFT dynamic power consumption.
[0006] To address the aforementioned technical problems, this invention provides a method for designing multi-bit flip-flops for standard cell libraries, comprising:
[0007] Provide several single-bit flip-flops and set the toggle rate of each single-bit flip-flop;
[0008] Arrange the single-bit flip-flops, placing the single-bit flip-flop with the lowest toggle rate at the last position;
[0009] Single-bit flip-flops are connected in series to form a scan chain according to the order. The first single-bit flip-flop is used to receive input data and scan chain control signals, and the output of the last single-bit flip-flop is used to output data.
[0010] Preferably, the single-bit flip-flops are arranged in descending order of flip rate from the first to the last bit of the scan chain.
[0011] Preferably, the output of the last single-bit flip-flop is also connected to an inverter to provide drive strength to the circuit connected to the output of the inverter.
[0012] Preferably, the output of the inverter is used to connect to another multi-bit flip-flop.
[0013] Preferably, the single-bit flip-flop shares a clock signal and a reset signal.
[0014] A scan chain includes a multi-bit flip-flop, which comprises a plurality of single-bit flip-flops connected in series to form a scan chain. The single-bit flip-flop with the lowest flip-flop rate is placed at the end of the scan chain. The first single-bit flip-flop is used to receive input data and scan chain control signals, and the output terminal of the last single-bit flip-flop is used to output data.
[0015] Preferably, the single-bit flip-flops are arranged in descending order of flip rate from the first to the last bit of the scan chain.
[0016] Preferably, the output of the last single-bit flip-flop is also connected to an inverter to provide drive strength to the circuit connected to the output of the inverter.
[0017] Preferably, the output of the inverter is used to connect to another multi-bit flip-flop.
[0018] Preferably, the single-bit flip-flop shares a clock signal and a reset signal.
[0019] In the multi-bit flip-flop design method for standard cell library provided by the present invention, by changing the arrangement order of each single-bit flip-flop contained in the multi-bit flip-flop in the standard cell library, the arrangement order of each single-bit flip-flop in the multi-bit flip-flop is changed according to the toggle rate, and the single-bit flip-flop with the lowest toggle rate is arranged at the output terminal, which can reduce DFT dynamic power consumption and optimize power signoff.
[0020] The scan chain provided by this invention and the multi-bit flip-flop design method for standard cell libraries provided by this invention belong to the same inventive concept. Therefore, the scan chain provided by this invention has at least all the advantages of the multi-bit flip-flop design method for standard cell libraries provided by this invention, which will not be repeated here. Attached Figure Description
[0021] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0022] Figure 1 This is a schematic diagram of a multi-bit flip-flop combination;
[0023] Figure 2 These are schematic diagrams of a single trigger and a trigger with scanning capabilities;
[0024] Figure 3 This is a schematic diagram of the scanning chain structure in the prior art;
[0025] Figure 4 This is a schematic diagram of the structure of multiple single-bit flip-flops in the prior art;
[0026] Figure 5 This is a schematic diagram of a multi-bit flip-flop structure according to an embodiment of the present invention;
[0027] Figure 6 This is a schematic diagram of a test case according to an embodiment of the present invention;
[0028] Figure 7 This is a schematic diagram of the running script of an embodiment of the present invention;
[0029] Figure 8 This is a schematic diagram of the code for setting the toggle rate of a single-bit flip-flop according to an embodiment of the present invention;
[0030] Figure 9 This is a schematic diagram illustrating the sorting of single-bit flip-flops according to their toggle rate, according to an embodiment of the present invention.
[0031] Figure 10 This is a flowchart of an embodiment of the present invention.
[0032] In the picture,
[0033] 10. First single-bit flip-flop; 20. Second single-bit flip-flop; 30. Third single-bit flip-flop; 40. Fourth single-bit flip-flop; 50. Inverter. Detailed Implementation
[0034] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0035] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; the term “at least two” is generally used to mean “two or more”; furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," and "third" may explicitly or implicitly include one or at least two of those features. The term "proximal" typically refers to the end closer to the operator, and the term "distal" typically refers to the end closer to the patient. "One end" and "the other end," as well as "proximal" and "distal," generally refer to two corresponding parts, including not only endpoints. The terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements or interactions between two elements. Furthermore, as used in this invention, the placement of one element on another element generally only indicates a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of another element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0036] Research has found that, Figure 1 The diagram shows a combined schematic of multi-bit flip-flops, which share clock, reset, and scan chain control signals. The scan chain is a commonly used digital integrated circuit (IC) testing technique, falling under the category of Design for Testability (DFT). DFT is a technique that considers testing requirements during the integrated circuit design phase. By adding additional test structures (such as scan chains) inside the chip, the internal logic state of the chip can be observed and controlled externally. This design method not only improves testing efficiency but also reduces testing costs, becoming an indispensable process in modern chip design.
[0037] Scan design exposes the internal logic state of a chip to the outside by inserting a scan chain inside the chip, thereby enabling observation and control of the internal logic. The basic principle is to replace ordinary flip-flops (DFFs) with scan-enabled flip-flops (SDFFs) and connect them into a shift register chain, such as... Figure 2 and Figure 3 As shown.
[0038] In normal mode, the scan chain has no impact on the circuit's functionality, and the chip operates normally according to its design specifications. In test mode, the scan chain is activated, test vectors are input through the scan chain, and the output results are read, thereby enabling the testing of the circuit's internal logic. By analyzing the output results, the test equipment can determine whether the chip has a fault.
[0039] Further research revealed that, within the scan chain, the dynamic power consumption of the DFT is directly related to the signal's flip rate, expressed by the formula P = αCV. 2 f, where α is the toggle rate, which refers to the number of times a signal changes from high level (1) to low level (0) or from low level to high level within a certain time, C is the load capacitance, V is the voltage, and f is the clock frequency. The toggle rate of the flip-flop at the final output end largely determines the dynamic power consumption of the multibit DFT.
[0040] Based on this, the core idea of this invention is to reduce DFT dynamic power consumption and optimize Powersignoff (Power signoff mainly includes static and dynamic power consumption analysis, Signal-EM analysis, and SIPI analysis based on chip packaging model, etc.) for multi-bit flip-flops in the standard cell library.
[0041] For details, please refer to Figures 5-10 This is a schematic diagram of an embodiment of the present invention. Figure 10 As shown, a design method for multi-bit flip-flops for a standard cell library includes:
[0042] Provide several single-bit flip-flops and set the toggle rate of each single-bit flip-flop;
[0043] Arrange the single-bit flip-flops, placing the single-bit flip-flop with the lowest toggle rate at the last position;
[0044] Single-bit flip-flops are connected in series to form a scan chain according to the order. The first single-bit flip-flop is used to receive input data and scan chain control signals, and the output of the last single-bit flip-flop is used to output data.
[0045] Dynamic power consumption is positively correlated with the signal's toggle rate. Furthermore, during DFT, the individual single-bit flip-flops in the multi-bit flip-flop (FF) are serially connected into a scan chain. Adjacent single-bit flip-flops are connected in the scan chain as follows: the scan input SI (Scan In) of the current single-bit flip-flop is connected to the output Q of the preceding single-bit flip-flop, and the output Q of the current single-bit flip-flop is connected to the scan input SI (Scan In) of the following single-bit flip-flop. This end-to-end serial connection of single-bit flip-flops involves the first single-bit flip-flop being connected to the scan chain control signal, which originates from other standard cells or other DFT scan chains.
[0046] Based on the above, if the high flip-flop (SDFF) is placed last, it will cause a surge in current density, resulting in a drop in the power supply voltage at the output of the multi-bit flip-flop (Iflip-flop). R A drop in voltage causes a series of chain reactions: the reduced voltage slows down the switching speed of the transistors, requiring a stronger drive and further increasing power consumption. The flip-flop's toggle rate at the output determines the dynamic power consumption of this multi-bit flip-flop's DFT.
[0047] In addition, the scan chain of DFT is serial, so the input (SI) and output (Q) of DFT scan chain in a multi-bit flip-flop are separate and unique, but do not affect the individual output Q of each flip-flop in the multi-bit flip-flop (parallel).
[0048] In one implementation, single-bit flip-flops are arranged according to their toggle rate, with the single-bit flip-flop with the lowest toggle rate set at the last position, thereby reducing DFT dynamic power consumption and optimizing power signoff.
[0049] The number of single-bit flip-flops is set according to the bit requirement of the multi-bit flip-flops. These single-bit flip-flops are independent and functionally identical. Furthermore, they share a clock signal, a reset signal, and a scan chain control signal.
[0050] For example, the output of the last single-bit flip-flop is also connected to an inverter to provide drive strength to the circuit connected to the output of the inverter. The output of the inverter is used to connect to another multi-bit flip-flop.
[0051] The inverter connected to the output Q of the last single-bit flip-flop requires greater drive strength to drive the subsequent circuits connected to its output, resulting in increased power consumption. Setting the single-bit flip-flop with the lowest flip-flop at the last position can significantly reduce dynamic power consumption and facilitate the implementation of DFT.
[0052] like Figure 5 As shown, four single-bit flip-flops are configured: a first single-bit flip-flop 10, a second single-bit flip-flop 20, a third single-bit flip-flop 30, and a fourth single-bit flip-flop 40. The scan input SI of the first single-bit flip-flop 10 is connected to the scan chain control signal, which is provided, for example, by another DFT scan chain. The input D of the first single-bit flip-flop 10 is connected to the input signal d0, and the output Q is connected to the scan input SI of the second single-bit flip-flop 20. Similarly, the third single-bit flip-flop 30 and the fourth single-bit flip-flop 40 are connected. The clock input (CK) of each single-bit flip-flop receives the same clock signal (CLK). The output of the fourth single-bit flip-flop 40 is connected to an inverter 50, and the output of the inverter 50 can be used to connect to the input of another multi-bit flip-flop.
[0053] More preferably, the single-bit flip-flops are arranged in descending order of flip rate from the first to the last bit of the scan chain.
[0054] For example, such as Figure 6 The diagram shown illustrates a test case model, configured as a single-bit flip-flop. Figure 7 The corresponding script shown sets the switching activity-toggle rate of a single-bit trigger through code, setting a different switching rate for each single-bit trigger, such as... Figure 8 As shown, the single-bit flip-flops with the toggle rate set are combined into two multi-bit flip-flops, reg1_reg[0,7:6,2] and reg1_reg[5:3,1]. The single-bit flip-flops inside the multi-bit flip-flops are arranged in descending order of toggle rate, as follows. Figure 9 As shown.
[0055] Based on the same technical concept, the present invention also provides a scan chain, including a multi-bit flip-flop, wherein the multi-bit flip-flop includes a plurality of single-bit flip-flops, the single-bit flip-flops are connected in series to form a scan chain, and the single-bit flip-flop with the lowest flip-flop rate is placed at the end of the scan chain, wherein the first single-bit flip-flop is used to receive input data and scan chain control signals, and the output terminal of the last single-bit flip-flop is used to output data.
[0056] The connection method for two adjacent single-bit flip-flops within a scan chain is as follows: the scan input terminal SI (SI is an abbreviation for Scan In) of the current single-bit flip-flop is connected to the output terminal Q of the previous single-bit flip-flop, and the output terminal Q of the current single-bit flip-flop is connected to the scan input terminal SI of the next single-bit flip-flop. Using this end-to-end connection method, the single-bit flip-flops are connected serially. The first single-bit flip-flop is connected to the scan chain control signal, which comes from other standard cells or other scan chains performing DFT (DFT scan chain).
[0057] The scan chain is used for DFT. During the design process of the standard cell library, the number of single-bit flip-flops is selected according to the bit requirement of multi-bit flip-flops, and the toggle rate of the single-bit flip-flops is preset. Based on the toggle rate, the single-bit flip-flops with the lowest toggle rate are placed at the end of the scan chain to minimize the power consumption at the output end during DFT testing, while optimizing the dynamic power consumption signoff of the SOC.
[0058] The output of the last single-bit flip-flop is also connected to an inverter. The output of the inverter is used to connect to another multi-bit flip-flop. The inverter connected to the output Q of the last single-bit flip-flop requires a greater drive strength, resulting in increased power consumption. Placing the single-bit flip-flop with the lowest flip-flop at the last position can significantly reduce dynamic power consumption and facilitate the implementation of DFT.
[0059] The number of single-bit flip-flops is set according to the bit requirement of the multi-bit flip-flops. These single-bit flip-flops are independent and functionally identical. Furthermore, they share a clock signal, a reset signal, and a scan control signal.
[0060] More preferably, the single-bit flip-flops are arranged in descending order of flip rate from the first to the last bit of the scan chain.
[0061] In the multi-bit flip-flop design method and scan chain for standard cell libraries provided by this invention, since the dynamic power consumption of DFT is directly related to the signal flip-flop rate, and when setting the single-bit flip-flops inside the scan chain, if the high flip-flop rate SDFF (Scan D Flip-Flop) is placed at the end, it will cause a surge in current density, resulting in a drop in the power supply voltage at the output of the multi-bit flip-flop (I). RA drop in voltage causes a series of chain reactions: the reduced voltage slows down the transistor switching speed, requiring a stronger drive, further increasing power consumption. Furthermore, when an inverter is used, it requires an even stronger drive, leading to increased energy consumption. Therefore, the toggle rate of the output flip-flop determines the DFT dynamic power consumption of this multi-bit flip-flop. By placing the single-bit flip-flop with the lowest toggle rate at the last position, DFT dynamic power consumption is reduced and Powersignoff is optimized. A better implementation is to arrange the single-bit flip-flops in descending order of toggle rate.
[0062] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for designing multi-bit flip-flops for a standard cell library, characterized in that, include: Provide several single-bit flip-flops and set the toggle rate of each single-bit flip-flop; Arrange the single-bit flip-flops, placing the single-bit flip-flop with the lowest toggle rate at the last position; Single-bit flip-flops are connected in series to form a scan chain according to the order. The first single-bit flip-flop is used to receive input data and scan chain control signals, and the output of the last single-bit flip-flop is used to output data.
2. The design method for multi-bit flip-flops using a standard cell library according to claim 1, characterized in that, The single-bit flip-flops are arranged in descending order of their flip rate from the first to the last bit of the scan chain.
3. The design method for multi-bit flip-flops using a standard cell library according to claim 1, characterized in that, The output of the last single-bit flip-flop is also connected to an inverter to provide drive strength to the circuit connected to the output of the inverter.
4. The design method for multi-bit flip-flops using a standard cell library according to claim 3, characterized in that, The output of the inverter is used to connect to another multi-bit flip-flop.
5. The design method for multi-bit flip-flops using a standard cell library according to claim 1, characterized in that, The single-bit flip-flop shares a clock signal and a reset signal.
6. A scanning chain, characterized in that, The system includes a multi-bit flip-flop, which comprises several single-bit flip-flops connected in series to form a scan chain. The single-bit flip-flop with the lowest toggle rate is placed at the end of the scan chain. The first single-bit flip-flop is used to receive input data and scan chain control signals, and the output of the last single-bit flip-flop is used to output data.
7. The scanning chain according to claim 6, characterized in that, The single-bit flip-flops are arranged in descending order of their flip rate from the first to the last bit of the scan chain.
8. The scan chain according to claim 6, characterized in that, The output of the last single-bit flip-flop is also connected to an inverter to provide drive strength to the circuit connected to the output of the inverter.
9. The scanning chain according to claim 8, characterized in that, The output of the inverter is used to connect to another multi-bit flip-flop.
10. The scan chain according to claim 6, characterized in that, The single-bit flip-flop shares a clock signal and a reset signal.