Analog-to-digital converter for battery management system, battery management system and voltage quantification method

Abstract

The invention provides an analog-to-digital converter for a battery management system, the battery management system and a voltage quantification method, which can be applied to the technical field of quantification. The analog-to-digital converter includes: a timing control circuit; the feed-forward integral and feedback circuit is used for generating an nth integral voltage according to the reference voltage and the input voltage received from the battery in the nth period of the M1 periods under the control of the time sequence control circuit and the (n-1) th low-order digital code; the successive approximation analog-to-digital conversion circuit is used for generating an nth low-order digital code based on the nth integral voltage in the nth period under the control of the time sequence control circuit; quantizing the residual voltage, which is not quantized, of the M1 integral voltage for M2 cycles to obtain M2 high-order digital codes of which the digits are higher than the digits of the low-order digital codes; and the filter is used for generating a target quantized value according to the M1 low-order digital codes and the M2 high-order digital codes.

Description

Technical Field

[0001] This invention relates to the field of quantization technology, and more specifically to an analog-to-digital converter for a battery management system, a battery management system, and a voltage quantization method. Background Technology

[0002] Analog-to-digital converters (ADCs) are core circuits in battery management integrated circuits (BMICs) for electric vehicles. Specifically, ADCs used in battery management chips primarily quantize battery-related analog signals into digital signals for battery status detection. However, there is an inherent trade-off between quantization speed and quantization accuracy in such ADCs. Summary of the Invention

[0003] In view of the above problems, the present invention provides an analog-to-digital converter for a battery management system, a battery management system, and a voltage quantization method.

[0004] One aspect of the present invention provides an analog-to-digital converter (ADC) for a battery management system, comprising: a timing control circuit; a feedforward integration and feedback circuit, configured to generate an nth integral voltage in the nth cycle of M1 cycles, under the control of the timing control circuit and the (n-1)th low-order digit code, based on a reference voltage and an input voltage received from the battery, where M1 is an integer greater than 1 and n is a positive integer less than or equal to M1; a successive approximation ADC circuit, configured to: in the nth cycle, under the control of the timing control circuit, generate an nth low-order digit code based on the nth integral voltage; wherein, when M1 cycles have been completed, the M1th integral voltage generated by the feedforward integration and feedback circuit is not fully quantized; quantizing the residual voltage of the unquantized M1th integral voltage for M2 cycles to obtain M2 high-order digit codes with a higher number of bits than the low-order digit codes; wherein M2 is a positive integer less than M1; and a filter, configured to generate a target quantized value based on the M1 low-order digit codes and the M2 high-order digit codes.

[0005] Another aspect of the present invention provides a battery management system, comprising: a battery; and the aforementioned analog-to-digital converter; wherein the feedforward integration and feedback circuit of the analog-to-digital converter operates in a high-voltage domain matching the cell voltage of the battery, and the successive approximation analog-to-digital conversion circuit operates in a low-voltage domain lower than the high-voltage domain.

[0006] Another aspect of the present invention provides a voltage quantization method applied to the aforementioned analog-to-digital converter. This voltage quantization method includes: a feedforward integration and feedback circuit, under the control of a timing control circuit and a (n-1)th low-order digital code, generating an nth integrated voltage based on a reference voltage and an input voltage received from a battery, where M1 is an integer greater than 1 and n is a positive integer less than or equal to M1; a successive approximation analog-to-digital converter circuit, under the control of the timing control circuit, generating an nth low-order digital code based on the nth integrated voltage in the nth cycle; wherein, when M1 cycles have been completed, the M1th integrated voltage generated by the feedforward integration and feedback circuit is not fully quantized; the successive approximation analog-to-digital converter circuit quantizes the remaining unquantized M1th integrated voltage for M2 cycles to obtain M2 high-order digital codes with a higher number of bits than the low-order digital codes; wherein M2 is a positive integer less than M1; and a filter generates a target quantized value based on the M1 low-order digital codes and the M2 high-order digital codes.

[0007] According to an embodiment of the present invention, an analog-to-digital converter (ADC) for a battery management system is provided. In this ADC, a feedforward integration and feedback circuit and a successive approximation ADC circuit can operate together for M1 cycles to convert the input voltage into low-order digital codes. Subsequently, the successive approximation ADC circuit can further quantize the residual voltage that was not quantized in the M1 cycles into high-order digital codes within M2 cycles to achieve precision extension. Thus, the successive approximation ADC circuit can be used as a Δ-Σ quantizer within M1 cycles and can also perform precision extension within M2 cycles, realizing the reuse of the successive approximation ADC circuit in both low-precision and high-precision quantization processes, reducing the precision requirements of the Δ-Σ process. Therefore, based on the feedforward integration and feedback circuit, the present invention uses a small number of components to construct the successive approximation ADC circuit, enabling both low-precision and high-precision quantization of the input voltage from the battery. Compared to ADCs in related technologies, the ADC of the present invention can reduce the number of quantization cycles and improve quantization speed while maintaining the same resolution. Attached Figure Description

[0008] The above-mentioned contents, other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the present invention with reference to the accompanying drawings, which will be described in conjunction with the drawings.

[0009] Figure 1 A schematic diagram of a battery management system according to an embodiment of the present invention is shown.

[0010] Figure 2 A schematic diagram of an analog-to-digital converter according to an embodiment of the present invention is shown.

[0011] Figure 3A schematic diagram of an analog-to-digital converter according to another embodiment of the present invention is shown.

[0012] Figure 4 A schematic diagram of an analog-to-digital converter according to yet another embodiment of the present invention is shown.

[0013] Figure 5 The present invention is shown Figure 4 The embodiment shows the timing diagram of the analog-to-digital converter.

[0014] Figure 6 The present invention is shown Figure 4 The embodiment shows a schematic diagram of the successive approximation analog-to-digital converter circuit and the feedback capacitor network.

[0015] Figure 7 The present invention is shown Figure 4 A block diagram of the analog-to-digital converter in the embodiment.

[0016] Figure 8A A schematic diagram of the output time-domain waveform of an analog-to-digital converter with a DC input according to an embodiment of the present invention is shown.

[0017] Figure 8B A schematic diagram of the output power spectral density of an analog-to-digital converter with AC input according to an embodiment of the present invention is shown.

[0018] Figure 9 The present invention is shown Figure 4 A schematic diagram of the first integrator in the embodiment.

[0019] Figure 10 A schematic diagram of a voltage quantization method according to an embodiment of the present invention is shown. Detailed Implementation

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0022] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0023] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0024] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. The terms "parallel," "perpendicular," and "equal" include the described situation and situations similar to the described situation, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism can be, for example, within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity can also be, for example, within 5°. "Equal" includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality can be, for example, a difference between the two equal items being less than or equal to 5% of either one. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] In battery management scenarios, analog-to-digital converters (ADCs) need to convert analog signals such as cell voltage, current, and temperature collected by sensors into digital signals to monitor the battery's state. In this scenario, the ADC needs to meet a high resolution of over 14 bits to accurately characterize minute changes in the analog signals and the battery's noise and offset voltage. Furthermore, the ADC's single-transformation (or quantization) time needs to be minimized for rapid response to abnormal battery conditions. Additionally, taking cell voltage as an example, this reduces additional errors introduced by inconsistent detection times of different cell voltages. Moreover, the ADC's own DC offset voltage also needs to be minimized to improve the DC measurement accuracy.

[0026] In some solutions, an analog-to-digital converter (ADC) based on an incremental Δ-Σ architecture can be used. This type of ADC can achieve high-precision quantization of analog signals based on oversampling and noise shaping techniques. However, there is an inherent trade-off between quantization speed and accuracy in this type of ADC. Specifically, when using an ADC built with a low-order modulator loop, a high oversampling rate is required to achieve the target accuracy. This leads to problems such as a large number of quantization cycles and slow quantization speed. On the other hand, an ADC built with a high-order modulator loop introduces complex operational stability issues. This increases the design complexity of the ADC. It should be understood that low operational stability of the ADC increases the risk of battery malfunctions.

[0027] This invention proposes an extended counting analog-to-digital converter (ADC) based on an asynchronous successive approximation converter. This ADC can be applied to battery management systems. The following detailed description is in conjunction with the accompanying drawings.

[0028] Figure 1 A schematic diagram of a battery management system according to an embodiment of the present invention is shown.

[0029] like Figure 1 As shown, the battery management system of this embodiment may include a battery and an analog-to-digital converter (ADC). In one embodiment of the invention, the battery may be a single battery, and the single battery may directly provide its voltage as an input voltage to the ADC. In another embodiment of the invention, there may be I batteries, where I is an integer greater than 1. The I batteries may include battery 1, ..., battery I. The I batteries may provide their battery voltages to a multiplexer, which, under the control of a control signal, may select the battery voltage of a target battery from the battery voltages of the I batteries as its input voltage and provide it to the ADC, so that the ADC quantizes the analog input voltage into a target quantized value in digital form.

[0030] Figure 2A schematic diagram of an analog-to-digital converter according to an embodiment of the present invention is shown.

[0031] like Figure 2 As shown, the analog-to-digital converter for a battery management system in this embodiment may include a timing control circuit, a feedforward integration and feedback circuit, and a successive approximation analog-to-digital conversion circuit.

[0032] The timing control circuit can generate a clock signal. This clock signal can be used to control the timing of the feedforward integration and feedback circuits and the successive approximation analog-to-digital converter circuits.

[0033] Based on this, the feedforward integrator and feedback circuit can process the input voltage in each of the M1 cycles (which can be called the low-order quantization cycle) to obtain the corresponding integrated voltage, where M1 is an integer greater than 1. The successive approximation analog-to-digital converter circuit can quantize the integrated voltage in each of the M1 cycles to generate the low-order digital code.

[0034] Specifically, taking the nth cycle out of M1 cycles as an example, the feedforward integration and feedback circuit, under the control of the timing control circuit and the (n-1)th low-order digital code, can generate the nth integral voltage based on the reference voltage and the input voltage received from the battery, where n is a positive integer less than or equal to M1. The reference voltage can include a positive reference voltage and a negative reference voltage. For example, the (n-1)th low-order digital code can be used as a feedback signal to control the feedforward integration and feedback circuit in the nth cycle. Thus, under the control of the (n-1)th digital code, the feedforward integration and feedback circuit can perform differential operations on the input voltage using either the positive or negative reference voltage to obtain the nth integral voltage corresponding to the unquantized low-order digital code. Subsequently, in the nth cycle, under the control of the timing control circuit, the successive approximation analog-to-digital converter circuit can generate the nth low-order digital code based on the nth integral voltage. In this way, by repeating M1 cycles, the feedforward integration and feedback circuit can perform Δ-Σ conversion on the input voltage to generate M1 integral voltages. The successive approximation analog-to-digital converter circuit can quantize M1 integral voltages in M1 cycles to generate M1 low-order digital codes.

[0035] When the successive approximation analog-to-digital converter (ADC) quantizes the M1th integral voltage to generate the M1th low-order digital code, it can be determined that M1 cycles have been completed. However, even after M1 cycles have been completed, the M1th integral voltage generated by the feedforward and feedback circuits has not been fully quantized. Therefore, the successive approximation ADC needs to further quantize the residual voltage of the M1th integral voltage that has not been quantized. Specifically, the residual voltage of the M1th integral voltage that has not been quantized is quantized for M2 cycles (which can be called the high-order quantization cycle), resulting in M2 high-order digital codes with a higher bit count than the low-order digital codes. Here, M2 is a positive integer less than M1. For example, for a 16-bit digital code, in the multi-bit digital code b15, ..., b0, b15~b8 can belong to the high-order bits (bit weight 2). 15 ~2 8 b7~b0 can be considered low positions (position weight 2) 7 ~2 0 ).

[0036] The filter can be implemented based on a microcontroller unit (MCU). The filter generates a target quantized value based on M1 low-order bits and M2 high-order bits. For example, the filter can filter the M1 low-order bits and perform calculations on the filtered M1 low-order bits and M2 high-order bits to obtain the target quantized value. This target quantized value can correspond to the battery's operating state parameters. For example, the battery's operating state parameters can specifically include the cell's operating state parameters. Based on these operating state parameters, dynamic management and energy scheduling of the battery can be achieved.

[0037] Based on this, in this embodiment of the invention, the feedforward integration and feedback circuit and the successive approximation analog-to-digital converter (ADC) circuit can operate together for M1 cycles to convert the input voltage into low-order digital code. Subsequently, the successive approximation ADC circuit can further quantize the residual voltage that was not quantized in the M1 cycles into high-order digital code within M2 cycles to achieve precision extension. Thus, the successive approximation ADC circuit can be used as a quantizer for Δ-Σ within M1 cycles and can also perform precision extension within M2 cycles, realizing the reuse of the successive approximation ADC circuit in both low-precision and high-precision quantization processes, reducing the precision requirements of the Δ-Σ process. Therefore, this embodiment of the invention, based on the feedforward integration and feedback circuit, uses a small number of components to construct the successive approximation ADC circuit, enabling both low-precision and high-precision quantization of the input voltage from the battery. Compared to analog-to-digital converters in related technologies, the analog-to-digital converter in this embodiment of the invention can reduce the number of quantization cycles and improve quantization speed while maintaining the same resolution.

[0038] Furthermore, a pre-quantization cycle can be included before the M1 cycles. Specifically, under the control of the timing control circuit, the successive approximation analog-to-digital converter circuit can quantize the initial abnormal voltage received within the pre-quantization cycle, generating an abnormal quantization value. For example, in the case of a battery short circuit, the abnormal quantization value can be 0, and vice versa. Thus, based on the abnormal quantization value, the abnormal state of the battery can be detected. Based on this, in emergency situations (such as a battery short circuit or excessive battery current), a rapid response to the abnormal state of the battery based on the abnormal quantization value can be achieved, improving battery safety.

[0039] Furthermore, combined Figure 1 and Figure 2 As can be seen, in one embodiment of the present invention, the multiplexer can sequentially provide the cell voltages of I batteries as input voltages to the analog-to-digital converter (ADC) of the present invention. Based on this, the ADC of the present invention quantizes the cell voltages and other information of the I batteries in a multiplexed manner. In some schemes, the ADC needs to quantize the cell voltages for at least 360 cycles to achieve 16-bit resolution. However, in this embodiment of the present invention, with a 16-bit resolution, M1=14, M2=1, and adding the pre-quantization cycle, the total quantization cycle of the ADC is 16 cycles. Thus, the ADC of the present invention shortens the total number of quantization cycles compared to the ADC in the other scheme. Furthermore, when quantizing the signals of multiple channels of batteries (e.g., cell voltage, temperature, or current) separately, the ADC of the present invention can improve the synchronization of the quantized operating state parameters. This allows for timely detection and response to the battery status. Specifically, it can improve the synchronization of multiple operating parameters of a single cell, as well as the synchronization of multiple operating parameters of I cells.

[0040] It should be noted that the feedforward integration and feedback circuits of the analog-to-digital converter operate in a high-voltage domain that matches the cell voltage of the battery. For example, the voltage domain of a single cell voltage (i.e., the high-voltage domain) may include 3.6V to 4.3V. The successive approximation analog-to-digital converter circuit can operate in a low-voltage domain, which is lower than the high-voltage domain and may include 1.2V to 1.8V.

[0041] Figure 3 A schematic diagram of an analog-to-digital converter according to another embodiment of the present invention is shown.

[0042] like Figure 3As shown, the clock control circuit may include a state control unit, a clock generation unit, and a level shifting unit. For example, when the multiplexer selected the cell voltage as described above, the state control unit can output a state control signal to control the clock generation unit to generate an initial clock signal. Furthermore, the clock generation unit can operate in the low-voltage domain. Thus, the initial clock signal from the clock generation unit can be directly provided to the successive approximation analog-to-digital converter (ADC) to drive the ADC, and the power consumption of the clock generation unit can be reduced. The level shifting unit can be used to shift the initial clock signal and provide the shifted clock signal to the feedforward integration and feedback circuit to control the operation of various devices (e.g., switches) in the feedforward integration and feedback circuit.

[0043] The feedforward integration and feedback circuit may include a first integrator and a second integrator. Further, in the nth cycle, under the control of the timing control circuit and the (n-1)th low-order digit code, the first integrator can obtain the nth target input voltage corresponding to the nth cycle based on the reference voltage and the input voltage. For example, the first integrator can perform differential operation on the input voltage using a positive or negative reference voltage to obtain the nth target input voltage. This nth target input voltage may correspond to the input voltage that has not yet been quantized in the nth cycle. Subsequently, the first integrator can integrate the nth target input voltage to obtain the nth intermediate integrated voltage. Specifically, the first integrator may include a digital-to-analog converter unit and a first switched-capacitor integration unit. The digital-to-analog converter unit can obtain the nth target input voltage corresponding to the nth cycle based on the reference voltage and the input voltage under the control of the timing control circuit and the (n-1)th low-order digit code in the nth cycle. The first switched-capacitor integration unit can integrate the nth target input voltage to obtain the nth intermediate integrated voltage. Further, the second integrator can integrate the nth intermediate integrated voltage to obtain the nth integrated voltage.

[0044] A successive approximation analog-to-digital converter (ADC) circuit may include a summing network, a feedback capacitor network, and an ADC unit. The summing network, feedback capacitor network, and ADC unit may be electrically connected via a summing node. Based on this, the summing network can provide the nth initial voltage to be quantized to the summing node according to the input voltage, the nth intermediate integral voltage, and the nth integral voltage. Specifically, the summing network can perform calculations on the input voltage, the nth intermediate integral voltage, and the nth integral voltage, and provide the resulting nth initial voltage to be quantized to the summing node.

[0045] The feedback capacitor network, under the control of the (n-1)th least significant bit, provides the nth feedback voltage to the summing node, thus processing the nth initial voltage to be quantized into the nth voltage to be quantized. For example, the feedback capacitor network can change its capacitance value under the control of the (n-1)th least significant bit to provide the nth feedback voltage. Based on a pre-set successive approximation method, the feedback capacitor network can adjust its capacitance value to provide the nth feedback voltage. It should be understood that when the feedback capacitor network provides the nth feedback voltage to the summing node, the voltage of the summing node will change, thereby obtaining the nth voltage to be quantized. Based on this, the analog-to-digital converter can quantize the nth voltage to be quantized, obtaining the nth least significant bit corresponding to the input voltage that has not yet been quantized in the nth cycle. By repeating this process, the input voltage can be quantized for M1 cycles, generating the corresponding M1 least significant bits. It should be noted that the least significant bit can be a 5-bit wide digital signal, including 5 binary bits from bit 0 (least significant bit) to bit 4 (most significant bit).

[0046] Furthermore, under the control of the M1 least significant digit, the feedback capacitor network can adjust its capacitance value to provide the M1th feedback voltage to the summing node, thus initially adjusting the node voltage. Simultaneously, the feedforward integrator and feedback circuit can store the residual voltage that has not yet been quantized. Based on this, under the control of the timing control circuit, the summing network can amplify the residual voltage based on a predetermined gain over M2 cycles and provide the amplified residual voltage to the summing node, further adjusting its node voltage. This allows the analog-to-digital converter (ADC) to output the high-order digit based on the further adjusted node voltage. Furthermore, the filtering unit in the filter can filter the least significant digit, and the summing unit can calculate the target quantized value from the high-order digit and the filtered least significant digit.

[0047] Figure 4 A schematic diagram of an analog-to-digital converter according to yet another embodiment of the present invention is shown. Figure 5 The present invention is shown Figure 4 The embodiment shows the timing diagram of the analog-to-digital converter.

[0048] like Figure 4 and Figure 5As shown, the digital-to-analog conversion unit may include multiple conversion sub-units, each of which may include a first sampling capacitor CI1, a sampling switch PR1, a positive reference switch Pp, and a negative reference switch Pn, etc. It should be understood that in this embodiment of the invention, there may be 31 groups of conversion sub-units (corresponding to 5-bit quantization precision), but this embodiment is not limited to this. The digital-to-analog conversion unit may be electrically connected to a first switched-capacitor integration unit via a first connection switch K1. The first switched-capacitor integration unit may include a first operational transconductance amplifier OTA1 and a first integration capacitor C11 electrically connected between the first input terminal and the output terminal of the first operational transconductance amplifier OTA1, etc. In other words, the first terminal of the first integration capacitor C11 is electrically connected to the first input terminal of the first operational transconductance amplifier OTA1, and the second terminal is electrically connected to the output terminal of the first operational transconductance amplifier OTA1. The first input terminal of the first operational transconductance amplifier OTA1 may be electrically connected to the first connection switch K1. The second input terminal of the first operational transconductance amplifier OTA1 may be configured to be connected to virtual ground. Specifically, in this embodiment of the invention, the input voltage Vin may be a differential voltage. Based on this, the second input terminal of the first operational transconductance amplifier OTA1 may be electrically connected to the common-mode terminal of the differential voltage. The common-mode signal of the differential voltage provided at this common-mode terminal can be used as a ground signal. It should be noted that... Figure 4 The grounding terminals shown are all virtual grounds, and the others are similar, so they will not be elaborated further.

[0049] The first switched-capacitor integration unit can be electrically connected to the second integrator via the second connection switch K2, the second sampling capacitor CI2, and the third connection switch K3. The second integrator may include the second switched-capacitor integration unit, etc. The second switched-capacitor integration unit may include the second operational transconductance amplifier OTA2 and the second integrating capacitor C12 electrically connected between the first input terminal and the output terminal of the second operational transconductance amplifier OTA2, etc. In other words, the first terminal of the second integrating capacitor C12 is electrically connected to the first input terminal of the second operational transconductance amplifier OTA2, and the second terminal is electrically connected to the output terminal of the second operational transconductance amplifier OTA2. The first input terminal of the second operational transconductance amplifier OTA2 is also electrically connected to the third connection switch K3. The second input terminal of the second operational transconductance amplifier OTA2 can also be configured to be connected to virtual ground, which will not be elaborated here.

[0050] Further, in this embodiment of the invention, the first terminal of the first sampling capacitor CI1 can be electrically connected to the voltage input terminal via the sampling switch PR1, and can be electrically connected to the positive reference terminal and the negative reference terminal via the positive reference switch Pp and the negative reference switch Pn, respectively. Taking the nth cycle as an example, under the control of the timing control circuit, the sampling switch PR1 can be closed to provide the input voltage Vin to the first sampling capacitor CI1. Further, under the control of the (n-1)th low-order digital code, the positive reference switch Pp or the negative reference switch Pn of each of the multiple conversion sub-units is closed, and the closed positive reference switch Pp and negative reference switch Pn of the multiple conversion sub-units correspond to the (n-1)th low-order digital code. In this way, the multiple conversion sub-units provide the positive reference voltage Vrefp or the negative reference voltage Vrefn to the corresponding first sampling capacitor CI1. Thus, the first sampling capacitor CI1 of each of the multiple conversion sub-units can be charged using either the corresponding positive reference voltage Vrefp or negative reference voltage Vrefn and the input voltage Vin, thereby performing a differential operation between the positive reference voltage Vrefp or negative reference voltage Vrefn and the input voltage Vin, and storing the voltage corresponding to the operation result. Based on this, the voltage jointly stored by the first sampling capacitors CI1 of the multiple conversion sub-units can be the nth target input voltage.

[0051] It should be further noted that during this period, the first connection switch K1, the second connection switch K2, and the third connection switch K3 can also be closed. In this way, the first integrating capacitor C11 can integrate the nth target input voltage. Alternatively, it can be described as using the nth target input voltage for integration and charging, thereby obtaining the nth intermediate integrated voltage. Thus, the first operational transconductance amplifier OTA1 can generate a first output current corresponding to the nth intermediate integrated voltage based on the voltage between the first and second input terminals of the first operational transconductance amplifier OTA1, to charge the second sampling capacitor CI2.

[0052] Simultaneously, the first output current can also flow through the second integrating capacitor C12. Thus, the second integrating capacitor C12 can also be charged by integration using the first output current, thereby obtaining the nth integrating voltage. Based on this, the second operational transconductance amplifier OTA2 can generate a second output current corresponding to the nth integrating voltage based on the voltage between its first and second input terminals. The output terminal of the second operational transconductance amplifier OTA2 can be electrically connected to a summing network. Thus, the second output current can be provided to the summing network. The summing network can provide the nth initial voltage to be quantized to the summing node based on the input voltage Vin, the voltage of the second sampling capacitor CI2 charged by the first output current, and the voltage charged by the second output current.

[0053] It should be further noted that the feedforward integration and feedback circuit also includes a first reset switch RST1 connected in parallel with the first integrating capacitor C11, a second reset switch RST2 connected in parallel with the second integrating capacitor C12, a first grounding switch R1 electrically connected between the first terminal and the common-mode terminal of the first connecting switch K1, a second grounding switch R2 electrically connected between the second terminal and the common-mode terminal of the second connecting switch K2, and a third grounding switch R3 electrically connected between the first terminal and the common-mode terminal of the third connecting switch K3. It should be understood that when the first connecting switch K1, the second connecting switch K2, and the third connecting switch K3 are closed, the first reset switch RST1, the second reset switch RST2, the first grounding switch R1, the second grounding switch R2, and the third grounding switch R3 can be opened. With the first connection switch K1, the second connection switch K2, and the third connection switch K3 open, the first reset switch RST1, the second reset switch RST2, the first grounding switch R1, the second grounding switch R2, and the third grounding switch R3 can be closed to reset the feedforward integrator and feedback circuit, for example, clearing the energy of the first sampling capacitor CI1 and the second sampling capacitor CI2, etc., which will not be elaborated here. Furthermore, the successive approximation analog-to-digital converter circuit can also be reset under the control of the reset signal RST, which will not be elaborated here either.

[0054] Specifically, the summing network may include a first capacitor C21, a second capacitor C22, a third capacitor C23, a first switch P1, a second switch P2, and a third switch P3. It should be noted that in this embodiment of the invention, the first switch P1, the second switch P2, and the third switch P3 are all closed at a high level ("1") and open at a low level ("0"), which will not be elaborated further here.

[0055] The first capacitor C21, the second capacitor C22, and the third capacitor C23 are each electrically connected to the summing node at their first terminals. The first switch P1 is electrically connected between the voltage input terminal and the second terminal of the first capacitor C21. The second switch P2 is electrically connected between the second integrator and the second terminal of the second capacitor C22. The third switch P3 is electrically connected between the first integrator and the second terminal of the third capacitor C23.

[0056] Based on this, during the target time period of the nth period, the first switch P1 is closed, so that the input voltage Vin is provided to the first terminal of the first capacitor C21, thereby allowing the first capacitor C21 to store the input voltage Vin. Furthermore, the second switch P2 is closed, so that the nth integral voltage is provided to the first terminal of the second capacitor C22, thereby allowing the second capacitor C22 to store the nth integral voltage. The third switch P3 is closed, so that the nth intermediate integral voltage is provided to the first terminal of the third capacitor C23, thereby allowing the third capacitor C23 to store the nth intermediate integral voltage. Thus, the summing network can provide the nth initial voltage to be quantized to the summing node based on the input voltage Vin stored in the first capacitor C21, the nth integral voltage stored in the second capacitor C22, and the nth intermediate integral voltage stored in the third capacitor C23.

[0057] The feedback capacitor network, under the control of the (n-1)th least significant bit, provides the nth feedback voltage to the summing node, processing the nth initial voltage to be quantized into the nth voltage to be quantized. The analog-to-digital converter (ADC) unit quantizes the nth voltage to be quantized, obtaining the nth least significant bit. It should be understood that after M1 cycles have been completed, the second integrating capacitor C12 can store a residual voltage. Thus, the successive approximation ADC circuit can further quantize this residual voltage to generate the digital code Dout, which can be either a least significant bit or a most significant bit.

[0058] Specifically, with M1 cycles completed, the input voltage can be expressed as:

[0059] (1)

[0060] (2)

[0061] Where Vin represents the input voltage. G1 represents the gain coefficient. M1 represents the total number of low-order quantization cycles described above. Dout1[M1] represents the M1th low-order digit code. Vres1 represents the residual voltage. k=1,……, -1, =2, ...,M1-1. M1-1 means subtracting "1" from the value M1.

[0062] In this embodiment of the invention, the feedforward path from the voltage input terminal to the summing node can eliminate signal components in the residual voltage. The remaining amount in the residual voltage can be considered as quantization error introduced by a finite-bit quantizer. For example, for an L-level quantizer, the range of the residual voltage can be expressed as:

[0063] (3)

[0064] Where Vres1 represents the residual voltage. L represents the number of quantizer levels. L can be an integer greater than 1, such as 3. Vref represents the predetermined reference voltage. In this embodiment of the invention, quantizing the residual voltage after M1 cycles can reduce quantization error and improve the accuracy of the analog-to-digital converter.

[0065] Figure 6 The present invention is shown Figure 4 The embodiment shows a schematic diagram of the successive approximation analog-to-digital converter circuit and the feedback capacitor network.

[0066] Reference Figure 4 , Figure 5 and Figure 6 The summing network may also include a fourth capacitor C24 and a fourth switch P4. The first terminal of the fourth capacitor C24 may also be electrically connected to the summing node N. The fourth switch P4 may be electrically connected between the second terminal of the fourth capacitor C24 and the second terminal of the second integrating capacitor C12. Furthermore, the capacitance value of the fourth capacitor C24 and the capacitance value of the second capacitor C22 have a multiple relationship related to a predetermined gain. It should be noted that the fourth switch P4 is open for M1 cycles, which will not be elaborated further here.

[0067] Within M2 cycles, the first switch P1 and the third switch P3 are open, while the second switch P2 and the fourth switch P4 are closed, so that the node voltage of the summing node N is adjusted to be the amplified node voltage based on the residual voltage stored in the second integrating capacitor C12. For example, the first capacitor C21 and the second capacitor C22 have the same capacitance value, and the third capacitor C23 has twice the capacitance value of the second capacitor C22. For example, the capacitance values ​​of the first capacitor C21 and the second capacitor C22 can be unit capacitance, denoted by Cu. The capacitance value of the third capacitor C23 can be 2Cu. The capacitance value of the fourth capacitor C24 can be (G-1)·Cu, where G represents the predetermined gain. It should be further noted that the summing network may also include a fourth grounding switch R4 electrically connected between the first terminal and the common-mode terminal of the first capacitor C21, a fifth grounding switch R5 electrically connected between the first terminal and the common-mode terminal of the second capacitor C22, a sixth grounding switch R6 electrically connected between the first terminal and the common-mode terminal of the third capacitor C23, a seventh grounding switch R7 electrically connected between the first terminal and the common-mode terminal of the fourth capacitor C24, and an eighth grounding switch R8 electrically connected between the first input terminal and the common-mode terminal of the dynamic comparator. It should be understood that when the first switch P1, the second switch P2, the third switch P3, and the fourth switch P4 are closed, the fourth grounding switch R4, the fifth grounding switch R5, the sixth grounding switch R6, the seventh grounding switch R7, and the eighth grounding switch R8 can be opened. With the first switch P1, second switch P2, third switch P3, and fourth switch P4 open, the fourth grounding switch R4, fifth grounding switch R5, sixth grounding switch R6, seventh grounding switch R7, and eighth grounding switch R8 can be closed to reset the voltages of the first capacitor C21, second capacitor C22, third capacitor C23, fourth capacitor C24, and the first input terminal of the dynamic comparator. It should be noted that in this embodiment of the invention, the first input terminals described above are all negative input terminals, and the second input terminals are all positive input terminals, which will not be elaborated further.

[0068] Based on this, the feedback capacitor network is electrically connected to the summing node N via the bridge capacitor Cb, so that the analog-to-digital converter (ADC) can initially adjust the node voltage of the summing node N by controlling the capacitance value of the feedback capacitor network, thereby ensuring that the initially adjusted node voltage is between the adjacent voltages corresponding to the least significant bit of the M1 digit code. It should be understood that these adjacent voltages are the two predetermined reference voltages adjacent to each other corresponding to the least significant bit of the M1 digit code, which will not be elaborated further here. This reduces the quantization noise introduced by the successive approximation ADC circuit. Furthermore, the parallel structure allows the coefficients of the feedback capacitor network and the ADC unit to be independent, providing greater configuration flexibility, while avoiding the introduction of at least one of the following parasitic capacitances, inductances, or resistances in the main signal path based on the feedforward integration and feedback circuit and the successive approximation ADC circuit. For example, the ADC unit may include a dynamic comparator and a successive approximation logic control unit. The first input of the dynamic comparator may be electrically connected to the summing node N, and the second input may be electrically connected to the common-mode input. The output of the dynamic comparator may be electrically connected to the successive approximation logic control unit. Wherein, Φ COMP This represents the clock signal terminal of the dynamic comparator. Thus, the successive approximation logic control unit can control the capacitance value of the feedback capacitor network (e.g., by controlling the closing of switches connected to capacitors in the feedback capacitor network so that the corresponding capacitors form a loop with the bridge capacitor Cb) based on a pre-set successive approximation method, to initially adjust the voltage of the summing node N. For example, the feedback capacitor network may include a binary weighted capacitor array, etc. Specifically, the feedback capacitor network may include capacitors with values ​​of 16Cu, 8Cu, and 2Cu. However, it should be understood that the embodiments of the present invention are not limited to this, and the feedback capacitor network may also include capacitors with a capacitance value of Cu, etc. The capacitance value of the bridge capacitor Cb may be Cu.

[0069] For example, after the approximation logic control unit initially adjusts the voltage of the summing node N, the voltage V of the summing node N... SAR_FB It can be represented as:

[0070] (4)

[0071] Among them, D i The value represents the weighting coefficient, which can be +1 or -1 based on the high-order or low-order digital code output by the dynamic comparator. i = 1, 2, 3, 4, but it should be understood that the invention is not limited thereto. A represents the voltage divider coefficient, which can be the same as the voltage divider coefficient of the digital-to-analog converter unit described above. Vref represents the predetermined reference voltage. Cu corresponds to the previous description, representing the capacitance value per unit capacitance.

[0072] Based on this, under the control of the timing control circuit, the residual voltage is amplified based on the predetermined gain during M2 cycles, and the amplified residual voltage is provided to the summing node N to further adjust the node voltage of the summing node N, so that the analog-to-digital conversion unit outputs digital code Vout based on the further adjusted node voltage. This digital code can be a high-order digital code.

[0073] Based on this, the analog-to-digital converter of the present invention can reduce the number of quantization cycles while maintaining the same accuracy by only adding timing control circuitry and a small number of capacitors, compared with analog-to-digital converters in related technologies.

[0074] Figure 7 The present invention is shown Figure 4 A block diagram of the analog-to-digital converter in the embodiment. Wherein, Let z denote the z-domain transfer function, which in this embodiment refers to the integrator. z represents the complex frequency variable. -1 This indicates a delay of one cycle.

[0075] like Figure 7 As shown, in the analog-to-digital converter of this embodiment, under the control of the timing control circuit, in the first quantization step 1, the input voltage Vin and the low-order digital code Dout1 can be differentially calculated, and the nth target input voltage is provided to the first integrator 301. The first integrator 301 integrates the target input voltage to obtain the nth intermediate integrated voltage. The second integrator 302 integrates the nth intermediate integrated voltage to obtain the nth integrated voltage. The summing network 303 can integrate the input voltage Vin, the nth intermediate integrated voltage after doubling the gain (corresponding to...) Figure 7 The summation of the 2nd voltage in the middle trigonometric function (and others similarly) and the nth integral voltage generates the nth initial voltage to be quantized. A 5-bit analog-to-digital converter 304 quantizes the nth initial voltage to obtain the nth least significant bit code. In the second quantization step 2, the summing network 303 amplifies the residual voltage Vres by a factor of G (in... Figure 7 The G in the triangle is used as the identifier, and the others are similarly represented. It should be understood that, for ease of illustration, the summing network 303 is not connected to the corresponding identifier. The amplified residual voltage is provided to the analog-to-digital conversion unit 304 for quantization, generating the high-order digital code Dout2. The filtering unit of the filter can filter the low-order digital code Dout1. Subsequently, the filter can amplify the high-order digital code Dout2 and the filtered low-order digital code Dout1 by G2 and G1 times respectively, and sum the amplified low-order digital code Dout1 and high-order digital code Dout2 to obtain the target quantized value. The filtering unit can be an integral comb decimation filter unit.

[0076] In this embodiment of the invention, when M1 cycles have been completed, the residual voltage amplified by a factor of G via the summing network can be expressed as:

[0077] (5)

[0078] (6)

[0079] Where Vres1 represents the aforementioned residual voltage. Dout2 represents the high-order digital code. G represents the predetermined gain. Vres2 represents the error voltage between the aforementioned residual voltage and the high-order digital code after M2 cycles have been completed. Vref represents the predetermined reference voltage.

[0080] The target quantization value can be expressed as:

[0081] (7)

[0082] Where Vtq represents the target quantization value. Dout1[k] represents the k-th least significant bit. k=1,……, -1, =2,……,M1-1. Dout2 represents the high-order digital code. G represents the predetermined gain. G1 represents the gain of the filter on the filtered low-order digital code. Vres2 represents the error voltage between the aforementioned residual voltage and the high-order digital code after M2 cycles have been completed. Vref represents the predetermined reference voltage.

[0083] With M2 cycles completed, the residual voltage of the feedforward integrator and feedback circuit can be expressed as:

[0084] (8)

[0085] Where Vres represents the residual voltage of the feedforward integrator and feedback circuit after M2 cycles have been completed. G represents the predetermined gain. M1 represents the total number of low-order quantization cycles described above. Vref represents the predetermined reference voltage.

[0086] In addition, refer to Figure 4 In the analog-to-digital converter of this embodiment, a data weighted averaging module (DWA) may also be included. This DWA can be used to suppress harmonic distortion caused by capacitor mismatch in the digital-to-analog converter. Specifically, the DWA can select capacitors from the feedback capacitor network in a predetermined order to participate in the digital-to-analog conversion process of the feedforward integration and feedback circuit, thereby suppressing capacitor mismatch. It should be noted that the output voltage of the data weighted averaging module can be a 31-bit wide digital signal, including 31 binary bits from bit 0 to bit 30, corresponding to higher precision, which will not be elaborated here.

[0087] In this embodiment of the invention, the offset voltage of the analog-to-digital converter (ADC) originates from the first integrator of the feedforward and feedback circuits. In some schemes, offset voltage can be suppressed using chopper modulation techniques. However, the suppression effect of this chopper modulation technique decreases when the oversampling rate of the ADC is low. Therefore, in this embodiment of the invention, the chopper timing is specifically improved to further eliminate residual voltage and optimize the overall offset voltage of the ADC. The offset voltage can be a DC voltage.

[0088] Figure 8A A schematic diagram of the output time-domain waveform of an analog-to-digital converter with a DC input according to an embodiment of the present invention is shown. Figure 8B A schematic diagram of the output power spectral density of an analog-to-digital converter with AC input according to an embodiment of the present invention is shown.

[0089] Specifically, refer to Figure 8A The time-domain waveforms of the analog-to-digital converter in the first and second quantization steps of this embodiment can be seen. (See reference...) Figure 8B It can be seen that the total quantization period, the first quantization step, and the output power spectral density of the second quantization step are all present in the embodiments of the present invention. Here, SNR represents the signal-to-noise ratio, dBFS is a unit used to measure amplitude, and dB represents decibels.

[0090] For the analog-to-digital converter in this embodiment of the invention, the output resolution of the first step of quantization (i.e., coarse quantization) can reach 13 bits, and the output resolution of the second step of quantization (i.e., fine quantization) can exceed 16 bits.

[0091] Figure 9 The present invention is shown Figure 4 A schematic diagram of the first integrator in the embodiment.

[0092] refer to Figure 4 and Figure 9 The first integrator can be used as a loop filter. The first integrator may also include a first chopper and a second chopper. The first chopper is electrically connected between the first switched-capacitor integrator (specifically, a first operational transconductance amplifier OTA1) and the digital-to-analog converter. The second chopper is electrically connected between the first switched-capacitor integrator and the second integrator (specifically, a second operational transconductance amplifier OTA2). It should be noted that in... Figure 9 In this context, Voffset=σ indicates that the fluctuation range of the offset voltage Voffset is σ. CH represents the signal path of the reference signal for the first and second choppers. It should be understood that this reference signal can be the reference signal used by the first and second choppers for signal modulation, which will not be elaborated further.

[0093] The first chopper can operate in the latter half of the M1 cycles (corresponding to...) Figure 9 The rightmost osr / 2 (osr represents the oversampling rate) will be used to represent the first half of the period (corresponding to...). Figure 9 The target input voltage (osr / 2) on the left side of the first integrator is used as the original frequency. The original frequency of the target input voltage is modulated, and the modulated target input voltage is provided to the first switched-capacitor integrator. For example, when M1 is even, the target input voltage can be modulated in the M1 / 2 cycle; when M1 is odd, the target input voltage can be modulated in the (1+M1) / 2 cycle. The modulated target input voltage includes the voltage at the chopper frequency and the voltage at odd harmonic frequencies. The second chopper modulates the frequency of the effective voltage of the intermediate integrated voltage received from the first switched-capacitor integrator to the original frequency, modulates the frequencies of the offset voltage and the target noise voltage in the intermediate integrated voltage to the target frequency, and provides the modulated intermediate integrated voltage to the second integrator. The target frequency represents the frequency that can be filtered out by the filter. Thus, when using a filter to filter the low-order digital code, the offset voltage and target noise voltage in the low-order digital code can be filtered out. The target noise voltage can be a 1 / f noise voltage. 1 / f noise voltage can refer to flicker noise voltage. f represents the frequency.

[0094] In the above process, the mismatch voltage sequence of the first integrator can be V1=σ,0,σ,……,σ,-σ,……,-σ,0, and the mismatch voltage sequence of the second integrator can be V2=0,σ,σ,2σ,2σ,…… , ,……,2σ,σ,σ,0. Based on this, the above method can reduce the impact of offset voltage and target noise voltage on the DC voltage output of the first and second integrators when the oversampling rate is low.

[0095] Based on the above, the analog-to-digital converter provided in this embodiment of the invention can significantly reduce the number of clock cycles required to achieve the same precision. For example, to achieve 16-bit precision, the number of clock cycles is reduced from 360 cycles in some other schemes to 16 cycles, and the single-cycle quantization time is significantly reduced at the same clock frequency. Furthermore, this analog-to-digital converter achieves the above effects by adding only a small number of capacitors and digital control circuitry (i.e., the timing control circuit mentioned above) to a second-order Δ-Σ loop, retaining its advantages of stability and simplicity.

[0096] Figure 10 A schematic diagram of a voltage quantization method according to an embodiment of the present invention is shown.

[0097] like Figure 10 As shown, the voltage quantization method of this embodiment can be applied to any of the analog-to-digital converters described above. Specifically, the voltage quantization method of this embodiment may include operations S1010 to S1040.

[0098] During operation S1010, the feedforward integration and feedback circuit generates the nth integrated voltage in the nth cycle of M1 cycles, under the control of the timing control circuit and the (n-1)th low-order digital code, based on the reference voltage and the input voltage received from the battery.

[0099] During operation of S1020, the successive approximation analog-to-digital converter circuit generates the nth least significant digital code based on the nth integral voltage in the nth cycle under the control of the timing control circuit.

[0100] In operation S1030, the successive approximation analog-to-digital converter circuit quantizes the residual voltage that was not quantized in the M1st integral voltage for M2 cycles, resulting in M2 high-order digital codes with a higher number of bits than the low-order digital codes.

[0101] In operation S1040, the filter generates the target quantized value based on M1 low-order digit codes and M2 high-order digit codes.

[0102] It should be understood that the voltage quantization method of the embodiments of the present invention is not limited to this, and may also include other methods performed by the analog-to-digital converter described above, which will not be elaborated here.

[0103] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0104] Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0105] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. An analog-to-digital converter for a battery management system, characterized in that, include: Timing control circuit; The feedforward integration and feedback circuit is used to generate the nth integrated voltage in the nth cycle of M1 cycles, under the control of the timing control circuit and the (n-1)th low-order digital code, based on the reference voltage and the input voltage received from the battery, where M1 is an integer greater than 1 and n is a positive integer less than or equal to M1. Successive approximation analog-to-digital converter circuits are used for: In the nth cycle, under the control of the timing control circuit, the nth low-order digital code is generated based on the nth integral voltage; wherein, when the M1 cycles have been completed, the M1th integral voltage generated by the feedforward integration and feedback circuit is not fully quantized. The residual voltage that was not quantized by the M1th integral voltage is quantized for M2 cycles to obtain M2 high-order digit codes with a higher number of bits than the low-order digit codes; where M2 is a positive integer less than M1. A filter is used to generate a target quantized value based on M1 low-order digit codes and M2 high-order digit codes.

2. The analog-to-digital converter according to claim 1, characterized in that, The successive approximation analog-to-digital converter circuit includes: Analog-to-digital conversion unit; A feedback capacitor network is used to adjust the capacitance value of the feedback capacitor network under the control of the low-order digital code of the M1 coarse quantization value, so as to provide the M1 feedback voltage to the summing node, so as to initially adjust the node voltage of the summing node. A summing network is used, under the control of the timing control circuit, to amplify the residual voltage based on a predetermined gain during the M2 cycles, and to provide the amplified residual voltage to the summing node to further adjust the node voltage of the summing node, thereby enabling the analog-to-digital conversion unit to output high-order digital code based on the further adjusted node voltage.

3. The analog-to-digital converter according to claim 2, characterized in that, The feedback capacitor network is electrically connected to the summing node via a bridge capacitor, so that the analog-to-digital conversion unit can initially adjust the node voltage by controlling the capacitance value of the feedback capacitor network, thereby making the node voltage between adjacent voltages corresponding to the low-order bits of the M1 digital code.

4. The analog-to-digital converter according to claim 2, characterized in that, The feedforward integration and feedback circuit includes: The first integrator is used, in the nth cycle, under the control of the timing control circuit and the (n-1)th low-order digital code, to obtain the nth target input voltage corresponding to the nth cycle based on the reference voltage and the input voltage, and to integrate the nth target input voltage to obtain the nth intermediate integrated voltage; The second integrator is used to integrate the nth intermediate integrated voltage to obtain the nth integrated voltage; The summing network is also configured to provide the nth initial voltage to be quantized to the summing node based on the input voltage, the nth intermediate integral voltage, and the nth integral voltage; The feedback capacitor network is also used to provide the nth feedback voltage to the summing node under the control of the (n-1)th low-order digital code, so as to process the nth initial voltage to be quantized into the nth voltage to be quantized. The analog-to-digital conversion unit is also used to quantize the nth voltage to be quantized to obtain the nth low-order digital code.

5. The analog-to-digital converter according to claim 4, characterized in that, The first integrator includes: A digital-to-analog converter is used, in the nth cycle, under the control of the timing control circuit and the (n-1)th low-order digital code, to obtain the nth target input voltage corresponding to the nth cycle based on the reference voltage and the input voltage; The first switched capacitor integration unit is used to integrate the nth target input voltage to obtain the nth intermediate integrated voltage; The first chopper is electrically connected between the first switched capacitor integration unit and the digital-to-analog converter unit; The second chopper is electrically connected between the first switched capacitor integration unit and the second integrator; The first chopper is used to modulate the target input voltage at the original frequency in the latter half of the M1 cycles, and to provide the modulated target input voltage to the first switched capacitor integration unit; wherein the modulated target input voltage includes the voltage of the chopper frequency and the odd harmonic frequency. The second chopper is used to modulate the frequency of the effective voltage of the intermediate integrated voltage received from the first switched capacitor integrator to the original frequency, modulate the frequencies of the offset voltage and the target noise voltage in the intermediate integrated voltage to the target frequency, and provide the modulated intermediate integrated voltage to the second integrator; the target frequency represents the frequency that can be filtered out by the filter.

6. The analog-to-digital converter according to claim 4, characterized in that, The summation network includes: The first terminal of each of the first, second, and third capacitors is electrically connected to the summing node. The first switch is electrically connected between the voltage input terminal and the second terminal of the first capacitor; The second switch is electrically connected between the second integrator and the second terminal of the second capacitor; The third switch is electrically connected between the first integrator and the second terminal of the third capacitor; Specifically, during the target time period of the nth cycle: the first switch is closed so that the input voltage is provided to the first terminal of the first capacitor, thereby causing the first capacitor to store the input voltage; the second switch is closed so that the nth integral voltage is provided to the first terminal of the second capacitor, thereby causing the second capacitor to store the nth integral voltage; the third switch is closed so that the nth intermediate integral voltage is provided to the first terminal of the third capacitor, thereby causing the third capacitor to store the nth intermediate integral voltage.

7. The analog-to-digital converter according to claim 6, characterized in that, The input voltage is a differential voltage; The second integrator includes: The second operational transconductance amplifier has a first input terminal that receives the nth intermediate integrated voltage and a second input terminal that is electrically connected to the common-mode terminal of the differential voltage. The second integrating capacitor has its first end electrically connected to the first input terminal of the second operational transconductance amplifier, and its second end electrically connected to the output terminal of the second operational transconductance amplifier; wherein, the second integrating capacitor stores the residual voltage after the M1 cycles have been completed; The summation network also includes: A fourth capacitor, with its first terminal electrically connected to the summing node; the capacitance value of the fourth capacitor has a multiple relationship with the capacitance value of the second capacitor, which is related to the predetermined gain. The fourth switch is electrically connected between the second terminal of the fourth capacitor and the second terminal of the second integrating capacitor; During the M2 cycles, the second switch and the fourth switch are closed so that the node voltage of the summing node is adjusted to the amplified node voltage based on the residual voltage stored in the second integrating capacitor, the M1th integrating voltage stored in the second capacitor, and the M1th intermediate integrating voltage stored in the third capacitor.

8. The analog-to-digital converter according to claim 7, characterized in that, The first capacitor and the second capacitor have the same capacitance value, and the third capacitor has twice the capacitance value of the second capacitor.

9. The analog-to-digital converter according to any one of claims 1 to 8, characterized in that, The successive approximation analog-to-digital converter circuit is further configured to, under the control of the timing control circuit, quantize the initial abnormal voltage and generate an abnormal quantization value when an initial abnormal voltage is received within a prequantization period prior to the M1 periods; the abnormal quantization value is used to detect the abnormal state of the battery.

10. The analog-to-digital converter according to any one of claims 1 to 8, characterized in that, With the analog-to-digital converter having a resolution of 16 bits, M1=14 and M2=1.

11. A battery management system, characterized in that, include: Battery; And an analog-to-digital converter as described in any one of claims 1 to 10; The feedforward integration and feedback circuit of the analog-to-digital converter operates in a high-voltage domain that matches the cell voltage of the battery, while the successive approximation analog-to-digital converter operates in a low-voltage domain that is lower than the high-voltage domain.

12. A voltage quantization method, characterized in that, Applied to any one of the analog-to-digital converters as described in claims 1 to 10, the voltage quantization method includes: In the nth cycle of M1 cycles, the feedforward integration and feedback circuit, under the control of the timing control circuit and the (n-1)th low-order digital code, generates the nth integrated voltage based on the reference voltage and the input voltage received from the battery. M1 is an integer greater than 1, and n is a positive integer less than or equal to M1. In the nth cycle, under the control of the timing control circuit, the successive approximation analog-to-digital converter circuit generates the nth least significant digital code based on the nth integral voltage; wherein, when the M1 cycles have been completed, the M1th integral voltage generated by the feedforward integration and feedback circuit is not fully quantized. The successive approximation analog-to-digital converter circuit quantizes the residual voltage that was not quantized in the M1th integral voltage for M2 cycles to obtain M2 high-order digit codes with a higher number of bits than the low-order digit codes; where M2 is a positive integer less than M1. The filter generates the target quantization value based on the M1 low-order digits and the M2 high-order digits.

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