Reference circuit and chip

Abstract

The invention provides a reference circuit and a chip, the reference circuit comprises a start and turn-off module, a first reference module, a bias module, a second reference module and a current output module, the start and turn-off module outputs a first node voltage and a second node voltage in the power-on process of the reference circuit; the first reference module outputs a first current according to the first node voltage, the second node voltage, the first signal and the second signal; the bias module pulls down the first signal and the second signal according to the second node voltage; the start and turn-off module is also turned off according to the pulled-down first signal and the pulled-down second signal after the start of the first reference module and the bias module is completed; the second reference module outputs a first voltage according to the first current, the first signal and the second signal; the current output module outputs target current according to the first voltage, the first signal and the second signal. According to the reference circuit, the starting and shutoff module is additionally arranged, so that the starting reliability and the overall working stability of the reference circuit are greatly improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to a reference circuit and chip. Background Technology

[0002] Bandgap reference circuits, as core modules in integrated circuits, are widely used in various electronic systems such as power management, analog-to-digital conversion, and industrial control. Their core function is to provide a stable reference voltage or current independent of process technology, power supply voltage, and temperature, which is crucial for ensuring the high-precision operation of electronic equipment. However, in the present technology, most reference circuits, in order to simplify design and reduce layout area, rely solely on the circuit's own device characteristics or simple bias structures to achieve power-on startup. This makes the reference circuit highly susceptible to getting stuck at the power-on degenerate bias point during the startup phase, leading to startup failure and greatly reducing the reliability of the reference circuit. Summary of the Invention

[0003] This application provides a reference circuit and chip that can solve the problem of high cost that is common in existing single-stage filter topologies.

[0004] In a first aspect, embodiments of this application provide a reference circuit, including a start-up and shutdown module, a first reference module, a bias module, a second reference module, and a current output module. The start-up and shutdown module is electrically connected to the first reference module and the bias module, respectively. The first reference module is electrically connected to the bias module, and the second reference module is electrically connected to the first reference module and the current output module, respectively. The start-up and shutdown module is used to output a first node voltage and a second node voltage during the power-on process of the reference circuit; the first reference module is used to output a first current to the second reference module according to the first node voltage, the second node voltage, a first signal, and a second signal; the bias module is used to pull down the first signal and the second signal according to the second node voltage; the start-up and shutdown module is also used to shut down according to the pulled-down first signal and the second signal after the first reference module and the bias module have started up; the second reference module is used to output a first voltage according to the first current, the first signal, and the second signal; the current output module is used to output a target current according to the first voltage, the first signal, and the second signal.

[0005] In one possible implementation of the first aspect, the start-up and shutdown module includes a start-up unit, a shutdown unit, and an output unit, wherein the start-up unit is electrically connected to the shutdown unit, the output unit, and the bias module, and the output unit is electrically connected to the shutdown unit and the first reference module. The startup unit is used to output the second node voltage during the power-on process of the reference circuit, and to output the third node voltage to the shutdown unit and the output unit; the output unit is used to output the first node voltage according to the third node voltage; the shutdown unit is used to pull down the third node voltage according to the first signal and the second signal after the first reference module and the bias module have been started.

[0006] In one possible implementation of the first aspect, the startup unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor. A first terminal of the first resistor, the source of the second transistor, the source of the third transistor, and a first terminal of the fourth resistor are all electrically connected to a power supply. The gate of the first transistor is electrically connected to a second terminal of the second resistor, a first terminal of the third resistor, and the gate of the fourth transistor. The source of the first transistor is electrically connected to the drain of the first transistor and a second terminal of the first resistor. The gate of the third transistor is electrically connected to the gate of the second transistor, the drain of the second transistor, and a first terminal of the second resistor. The drain of the third transistor is electrically connected to the bias module. The source of the fourth transistor is electrically connected to a second terminal of the fourth resistor. The drain of the fourth transistor is electrically connected to both the shutdown unit and the output unit. The second terminal of the third resistor is grounded. In one possible implementation of the first aspect, the shutdown unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a fifth resistor. The first terminal of the fifth resistor is electrically connected to both the startup unit and the output unit. The second terminal of the fifth resistor is electrically connected to the drain of the fifth transistor. The gate of the sixth transistor is electrically connected to the drain of the sixth transistor, the source of the fifth transistor, and the gate of the eighth transistor. The sources of the sixth and eighth transistors are both grounded. The gate of the seventh transistor is electrically connected to the drain of the seventh transistor, the gate of the fifth transistor, and the drain of the ninth transistor. The source of the seventh transistor is electrically connected to the drain of the eighth transistor. The gate of the ninth transistor is used to receive the second signal. The source of the ninth transistor is electrically connected to the drain of the tenth transistor. The gate of the tenth transistor is used to receive the first signal. The source of the tenth transistor is used to be electrically connected to a power supply. In one possible implementation of the first aspect, the output unit includes an eleventh transistor, a sixth resistor, and a seventh resistor. The gate of the eleventh transistor is electrically connected to the startup unit and the shutdown unit, respectively. The drain of the eleventh transistor is electrically connected to the second terminal of the sixth resistor and the first reference module, respectively. The source of the eleventh transistor is electrically connected to the first terminal of the seventh resistor and the first reference module, respectively. The first terminal of the sixth resistor is used to be electrically connected to the power supply, and the second terminal of the seventh resistor is grounded. In one possible implementation of the first aspect, the first reference module includes an adjustment unit and a current generating unit, both of which are electrically connected to the start-up and shutdown module, and the current generating unit is electrically connected to both the adjustment unit and the bias module. The current generating unit is used to output a first current to the second reference module based on the first node voltage, the second node voltage, the first signal, and the second signal, and to output a fourth node voltage to the adjustment unit; the adjustment unit is used to raise the first node voltage based on the first signal, the second signal, and the fourth node voltage after the pull-down. In one possible implementation of the first aspect, the regulating unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The gate of the twelfth transistor is electrically connected to the drain of the fourteenth transistor and the source of the fifteenth transistor, respectively. The drain of the twelfth transistor is electrically connected to the start-up and shutdown module. The source of the twelfth transistor is electrically connected to both the start-up and shutdown module and the current generating unit, respectively. The gate of the thirteenth transistor is used to receive the first signal. The source of the thirteenth transistor is used to be electrically connected to a power supply. The drain of the thirteenth transistor is electrically connected to the source of the fourteenth transistor. The gate of the fourteenth transistor is used to receive the second signal. The gate of the fifteenth transistor is electrically connected to the current generating unit. The drain of the fifteenth transistor is grounded. In one possible implementation of the first aspect, the current generating unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a first transistor, a second transistor, and an eighth resistor. The gate of the sixteenth transistor is electrically connected to the gate of the nineteenth transistor, the drain of the twentyth transistor, and the drain of the twenty-first transistor, respectively, for receiving the first signal. The sources of the sixteenth transistor and the nineteenth transistor are both electrically connected to a power supply. The drain of the sixteenth transistor is electrically connected to the source of the seventeenth transistor, and the gate of the twentyth transistor is electrically connected to the gate of the seventeenth transistor, for receiving the first signal. Two signals are present. The source of the twentieth transistor is electrically connected to the drain of the nineteenth transistor. The gate of the eighteenth transistor is electrically connected to the gate of the twenty-first transistor and the bias module. The drain of the eighteenth transistor is electrically connected to the drain of the seventeenth transistor and the adjustment unit. The source of the eighteenth transistor is electrically connected to the collector of the first transistor. The base of the first transistor is electrically connected to the base of the second transistor. The transistor is used to receive the first node voltage. The emitter of the first transistor and the second terminal of the eighth resistor are both grounded. The collector of the second transistor is electrically connected to the source of the twenty-first transistor. The emitter of the second transistor is electrically connected to the first terminal of the eighth resistor. In one possible implementation of the first aspect, the bias module includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, a 26th transistor, and a third transistor. The gate of the 22nd transistor is used to receive the first signal. The sources of the 22nd transistor and the 25th transistor are both electrically connected to a power supply. The drain of the 22nd transistor is electrically connected to the source of the 23rd transistor. The gates of the 25th transistor and the 23rd transistor are both used to receive the second signal. The drain of the 25th transistor is electrically connected to the gate of the 25th transistor and the drain of the 26th transistor, respectively. The base of the third transistor is electrically connected to the collector of the third transistor, the drain of the 23rd transistor, the start-up and shutdown module, and the first reference module, respectively. The emitter of the third transistor is electrically connected to the gate of the 24th transistor, the gate of the 26th transistor, and the drain of the 24th transistor, respectively. The sources of the 24th transistor and the 26th transistor are both grounded. In one possible implementation of the first aspect, the second reference module includes a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor, a thirty-second transistor, a fourth transistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor. The source of the twenty-seventh transistor, the first terminal of the tenth resistor, and the source of the thirtieth transistor are all electrically connected to a power supply. The gates of the twenty-seventh transistor and the thirtieth transistor are both used to receive the first signal. The drain of the twenty-seventh transistor is electrically connected to the source of the twenty-eighth transistor. The gates of the thirty-first transistor and the twenty-eighth transistor are both used to receive the second signal. The source of the thirty-first transistor is electrically connected to the source of the thirtieth transistor. The drains of the tenth transistor are electrically connected. The drain of the thirty-first transistor is electrically connected to the first terminal of the twelfth resistor and the current output module. The gate of the twenty-ninth transistor is electrically connected to the drain of the twenty-eighth transistor and the collector of the fourth transistor. The source of the twenty-ninth transistor is electrically connected to the first terminal of the eleventh resistor and the gate of the thirty-second transistor. The drain of the twenty-ninth transistor is electrically connected to the second terminal of the tenth resistor. The source of the thirty-second transistor is electrically connected to the base of the fourth transistor and the second terminal of the twelfth resistor. The drain of the thirty-second transistor, the second terminal of the ninth resistor, and the second terminal of the eleventh resistor are all grounded. The first terminal of the ninth resistor is electrically connected to the emitter of the fourth transistor.

[0007] In one possible implementation of the first aspect, the current output module includes a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, a 37th transistor, a 38th transistor, a 39th transistor, a 40th transistor, a 41st transistor, and a 13th resistor. The gate of the 33rd transistor is used to receive the first signal. The sources of the 33rd transistor, the 36th transistor, and the 40th transistor are all electrically connected to a power supply. The drain of the 33rd transistor is electrically connected to the source of the 34th transistor. The gate of the 34th transistor is used to receive the second signal. The drain of the 34th transistor is connected to the gate of the 35th transistor, the drain of the 35th transistor, and the 39th transistor. The gates of the transistors are electrically connected. The sources of the thirty-ninth transistor and the thirty-fifth transistor are both grounded. The drain of the thirty-ninth transistor is electrically connected to the source of the thirty-eighth transistor. The gate of the thirty-eighth transistor is electrically connected to the second reference module. The drain of the thirty-eighth transistor is electrically connected to the gate of the thirty-seventh transistor, the gate of the forty-first transistor, and the second terminal of the thirteenth resistor. The gate of the thirty-sixth transistor is electrically connected to the gate of the fortieth transistor, the drain of the thirty-seventh transistor, and the first terminal of the thirteenth resistor. The drain of the thirty-sixth transistor is electrically connected to the source of the thirty-seventh transistor. The source of the forty-first transistor is electrically connected to the drain of the fortieth transistor. The drain of the forty-first transistor is used to output the target current.

[0008] Secondly, embodiments of this application provide a chip including the reference circuit described in any one of the first aspects.

[0009] The beneficial effects of the embodiments in this application compared with the prior art are: The reference circuit provided in this application includes a startup and shutdown module, a first reference module, a bias module, a second reference module, and a current output module. During the power-on process of the reference circuit, the startup and shutdown module is in a startup state and can output a first node voltage and a second node voltage. The first node voltage is used to supply bias power to the first reference module, and the second node voltage is used to supply power to the bias module. The first reference module outputs a first current to the second reference module based on the first node voltage, the second node voltage, a first signal, and a second signal. The bias module pulls down the first and second signals based on the second node voltage. The pulled-down first and second signals are transmitted to the startup and shutdown module. The startup and shutdown module can also shut down based on the pulled-down first and second signals after the first reference module and the bias module have started up, entering a low-power state. The second reference module outputs a first voltage based on the first current, the first signal, and the second signal. The first voltage is further converted into a target current by the current output module to ensure the realization of the core functions of the reference circuit. Therefore, the reference circuit provided in this application embodiment, by adding a start-up and shutdown module, can provide accurate initial excitation during the power-on stage, effectively ensuring that the subsequent first reference module gets rid of the power-on degenerate bias point, solving the problem of startup failure that is prone to occur in traditional reference circuits due to the lack of a dedicated startup mechanism. At the same time, the automatic shutdown after startup optimizes the working state, greatly improving the startup reliability and overall working stability of the reference circuit. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic block diagram of a reference circuit provided in one embodiment of this application; Figure 2 This is a circuit connection diagram of a startup and shutdown module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the startup and shutdown paths of a startup and shutdown module provided in an embodiment of this application; Figure 4 This is a circuit connection diagram of the first reference module and the bias module provided in an embodiment of this application; Figure 5 This is a circuit connection diagram of the second reference module provided in an embodiment of this application; Figure 6 This is a circuit connection diagram of a current output module provided in an embodiment of this application; Figure 7 This is a schematic diagram of total dose effect hardening design on the device process layout provided in one embodiment of this application; Figure 8 This is a schematic diagram of the structure of a chip provided in one embodiment of this application.

[0012] In the diagram: 10. Reference circuit; 101. Start-up and shutdown module; 1011. Start-up unit; 1012. Shut-down unit; 1013. Output unit; 102. First reference module; 1021. Adjustment unit; 1022. Current generation unit; 103. Bias module; 104. Second reference module; 105. Current output module. Detailed Implementation

[0013] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0014] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0015] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0016] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0017] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0018] Bandgap reference circuits, as core modules in integrated circuits, are widely used in various electronic systems such as power management, analog-to-digital conversion, and industrial control. Their core function is to provide a stable reference voltage or current independent of process technology, power supply voltage, and temperature, which is crucial for ensuring the high-precision operation of electronic equipment. However, in the present technology, most reference circuits, in order to simplify design and reduce layout area, rely solely on the circuit's own device characteristics or simple bias structures to achieve power-on startup. This makes the reference circuit highly susceptible to getting stuck at the power-on degenerate bias point during the startup phase, leading to startup failure and greatly reducing the reliability of the reference circuit.

[0019] To address the aforementioned issues, the reference circuit provided in this application includes a startup and shutdown module, a first reference module, a bias module, a second reference module, and a current output module. During power-up of the reference circuit, the startup and shutdown module is in a startup state and can output a first node voltage and a second node voltage. The first node voltage is used to supply bias power to the first reference module, and the second node voltage is used to supply power to the bias module. The first reference module outputs a first current to the second reference module based on the first node voltage, the second node voltage, a first signal, and a second signal. The bias module pulls down the first and second signals based on the second node voltage. The pulled-down first and second signals are transmitted to the startup and shutdown module, which can also shut down based on the pulled-down first and second signals after the first reference module and the bias module have finished startup, entering a low-power state. The second reference module outputs a first voltage based on the first current, the first signal, and the second signal. The first voltage is further converted into a target current by the current output module to ensure the realization of the core functions of the reference circuit. Therefore, the reference circuit provided in this application embodiment, by adding a start-up and shutdown module, can provide accurate initial excitation during the power-on stage, effectively ensuring that the subsequent first reference module gets rid of the power-on degenerate bias point, solving the problem of startup failure that is prone to occur in traditional reference circuits due to the lack of a dedicated startup mechanism. At the same time, the automatic shutdown after startup optimizes the working state, greatly improving the startup reliability and overall working stability of the reference circuit.

[0020] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0021] Figure 1 A schematic block diagram of a reference circuit 10 provided in one embodiment of this application is shown. See also... Figure 1 As shown, the reference circuit 10 includes a start-up and shutdown module 101, a first reference module 102, a bias module 103, a second reference module 104, and a current output module 105. The start-up and shutdown module 101 is electrically connected to the first reference module 102 and the bias module 103, respectively. The first reference module 102 is electrically connected to the bias module 103, and the second reference module 104 is electrically connected to the first reference module 102 and the current output module 105, respectively.

[0022] Specifically, during the power-on process of the reference circuit 10, the start-up and shutdown module 101 is in the start-up state and can output a first node voltage VC and a second node voltage VD. The first node voltage VC is used to supply bias power to the first reference module 102, and the second node voltage VD is used to supply power to the bias module 103. The first reference module 102 outputs a first current IPTAT to the second reference module 104 according to the first node voltage VC, the second node voltage VD, the first signal VB1, and the second signal VB2. The bias module 103 pulls down the first signal VB1 and the second signal VB2 according to the second node voltage VD. The pulled-down first signal VB1 and the second signal VB2 are transmitted to the start-up and shutdown module 101. The start-up and shutdown module 101 can also shut down according to the pulled-down first signal VB1 and the second signal VB2 after the first reference module 102 and the bias module 103 have started up, entering a low-power state. The second reference module 104 outputs a first voltage VPTAT_O based on the first current IPTAT, the first signal VB1, and the second signal VB2. The first voltage VPTAT_O is further converted by the current output module 105 to output the target current IPTAT_O, thereby ensuring the realization of the core function of the reference circuit 10. Therefore, the reference circuit 10 provided in this embodiment, by adding a start-up and shutdown module 101, can provide accurate initial excitation during the power-on phase, effectively ensuring that the subsequent first reference module 102 is freed from the power-on degenerate bias point. This solves the startup failure problem that traditional reference circuits 10 are prone to due to the lack of a dedicated startup mechanism. Simultaneously, the automatic shutdown after startup optimizes the working state, greatly improving the startup reliability and overall working stability of the reference circuit 10.

[0023] It should be noted that after the bias module 103 pulls down the first signal VB1 and the second signal VB2, the pulled-down first signal VB1 and the second signal VB2 will also be synchronously fed back to the first reference module 102. The first reference module 102 will also raise the first node voltage VC according to the pulled-down first signal VB1 and the second signal VB2, thereby accelerating the establishment process of its own bias state and ensuring that the first reference module 102 quickly enters a stable working mode.

[0024] In one embodiment of this application, such as Figure 2 As shown, the start-up and shutdown module 101 includes a start-up unit 1011, a shutdown unit 1012, and an output unit 1013. The start-up unit 1011 is electrically connected to the shutdown unit 1012, the output unit 1013, and the bias module 103, respectively. The output unit 1013 is electrically connected to the shutdown unit 1012 and the first reference module 102, respectively.

[0025] Specifically, during the power-on process of the reference circuit 10, the startup unit 1011 outputs the second node voltage VD to power the bias module 103, and simultaneously outputs the third node voltage VA (i.e., the voltage at node A) to the shutdown unit 1012 and the output unit 1013. The output unit 1013 outputs the first node voltage VC to power the first reference module 102 based on the third node voltage VA. After the first reference module 102 and the bias module 103 have started up, the shutdown unit 1012 responds to the first signal VB1 and the second signal VB2 after being pulled down, actively pulling down the third node voltage VA. The output unit 1013 shuts down the output based on the pulled-down third node voltage VA, thereby triggering the startup and shutdown module 101 to enter a low-power state as a whole, avoiding continuous power consumption of redundant branches.

[0026] In one embodiment of this application, such as Figure 2As shown, the startup unit 1011 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first terminal of the first resistor R1, the source of the second transistor M2, the source of the third transistor M3, and the first terminal of the fourth resistor R4 are all electrically connected to the power supply VDD. The gate of the first transistor M1 is electrically connected to the second terminal of the second resistor R2, the first terminal of the third resistor R3, and the gate of the fourth transistor M4, respectively. The source of the first transistor M1 is electrically connected to the drain of the first transistor M1 and the second terminal of the first resistor R1, respectively. The gate of the third transistor M3 is electrically connected to the gate of the second transistor M2, the drain of the second transistor M2, and the first terminal of the second resistor R2, respectively. The drain of the third transistor M3 is electrically connected to the bias module 103. The source of the fourth transistor M4 is electrically connected to the second terminal of the fourth resistor R4, and the drain of the fourth transistor M4 is electrically connected to the shutdown unit 1012 and the output unit 1013, respectively. The second terminal of the third resistor R3 is grounded.

[0027] Specifically, the source-drain short circuit of the first transistor M1 acts as a capacitor. During power-on, the power supply VDD charges the first transistor M1 through the first resistor R1. The first resistor R1 limits the peak value of the charging current of the first transistor M1, preventing excessive instantaneous current from impacting the first transistor M1 and subsequent devices. Since the gate of the first transistor M1 is connected to the gate of the fourth transistor M4, the charging of the first transistor M1 provides an initial bias voltage for the gate of the fourth transistor M4. As the charging process of the first transistor M1 progresses, the fourth transistor M4 gradually turns on and is pulled up through the fourth resistor R4, raising the third node voltage VA and driving the output unit 1013 to output the first node voltage VC. Since the second transistor M2 and the third transistor M3 form a mirror current source structure, when the first transistor M1 is charged to a certain extent, a voltage drop is formed across the third resistor R3, generating a pull-down current. This current is mirrored through the second transistor M2 to the branch of the third transistor M3, driving the third transistor M3 to conduct and output the second node voltage VD at its drain, providing initial power to the bias module 103.

[0028] For example, designers can select the types of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 according to the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors or bipolar transistors. For instance, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 can all be selected as PMOS transistors.

[0029] In one embodiment of this application, such as Figure 2As shown, the shutdown unit 1012 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and a fifth resistor R5. The first terminal of the fifth resistor R5 is electrically connected to the startup unit 1011 and the output unit 1013, respectively. The second terminal of the fifth resistor R5 is electrically connected to the drain of the fifth transistor M5. The gate of the sixth transistor M6 is electrically connected to the drain of the sixth transistor M6, the source of the fifth transistor M5, and the gate of the eighth transistor M8, respectively. The source of the sixth transistor M6... The gate of the seventh transistor M7 and the source of the eighth transistor M8 are both grounded. The gate of the seventh transistor M7 is electrically connected to the drain of the seventh transistor M7, the gate of the fifth transistor M5, and the drain of the ninth transistor M9. The source of the seventh transistor M7 is electrically connected to the drain of the eighth transistor M8. The gate of the ninth transistor M9 is used to receive the second signal VB2. The source of the ninth transistor M9 is electrically connected to the drain of the tenth transistor M10. The gate of the tenth transistor M10 is used to receive the first signal VB1. The source of the tenth transistor M10 is used to be electrically connected to the power supply VDD.

[0030] Specifically, the fifth resistor R5 acts as a current-limiting and voltage-dividing element. One end is connected to the signal node between the startup unit 1011 and the output unit 1013, and the other end is connected to the drain of the fifth transistor M5. This limits the branch current to prevent overcurrent and provides a stable operating voltage for the fifth transistor M5. The ninth transistor M9 and the tenth transistor M10 serve as the signal receiving and driving core. They receive the second signal VB2 and the first signal VB1 through their gates, respectively. Based on the power supply VDD connected to the source of the tenth transistor M10, a driving branch is formed. After the first reference module 102 and the bias module 103 are started, the branch is triggered to conduct and provides a driving signal for the subsequent pull-down action, in conjunction with the mirror current pull-up effect of the Cascode structure ninth transistor M9 and tenth transistor M10. The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 form a complementary logic pull-down network. Driven by the ninth transistor M9 and the tenth transistor M10, this network works with the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 to achieve a strong pull-down function, pulling down the third node voltage VA, thereby lowering the third node voltage VA, causing the output unit 1013 to turn off the output, and finally prompting the start-up and shutdown module 101 to cut off the redundant start-up branch and enter a low-power state.

[0031] For example, designers can select the types of the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 according to the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar transistors (BPTs). For instance, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 can all be NMOS transistors, while the ninth transistor M9 and the tenth transistor M10 can both be PMOS transistors.

[0032] In one embodiment of this application, such as Figure 2 As shown, the output unit 1013 includes an eleventh transistor M11, a sixth resistor R6, and a seventh resistor R7. The gate of the eleventh transistor M11 is electrically connected to the start-up unit 1011 and the turn-off unit 1012, respectively. The drain of the eleventh transistor M11 is electrically connected to the second terminal of the sixth resistor R6 and the first reference module 102, respectively. The source of the eleventh transistor M11 is electrically connected to the first terminal of the seventh resistor R7 and the first reference module 102, respectively. The first terminal of the sixth resistor R6 is used to be electrically connected to the power supply VDD, and the second terminal of the seventh resistor R7 is grounded.

[0033] Specifically, the sixth resistor R6 acts as a current-limiting voltage divider, limiting the peak current flowing into the eleventh transistor M11 and the first reference module 102 to prevent overcurrent damage. It also works with the grounded seventh resistor R7 to form a voltage divider network, providing a stable voltage regulation range for the first reference module 102. The seventh resistor R7, acting as a grounded voltage divider resistor, together with the sixth resistor R6, forms a voltage regulation branch, ensuring that the eleventh transistor M11 operates within a suitable voltage range, while simultaneously providing a stable ground reference potential for the first reference module 102. The eleventh transistor M11 serves as the core switch and driver of the output unit 1013. Its gate receives the third node voltage VA. During the power-on startup phase, it is turned on by the startup unit 1011. Based on the voltage division effect of the sixth resistor R6 and the seventh resistor R7, it outputs the first node voltage VC at node C to provide bias power to the first reference module 102. After the subsequent modules have started up, the shutdown unit 1012 pulls down the third node voltage VA, and the eleventh transistor M11 turns off, cutting off the power supply transmission of the startup branch and causing the startup and shutdown module 101 to enter a low-power state.

[0034] For example, designers can select the type of the eleventh transistor M11 according to the actual situation, such as a metal-oxide-semiconductor field-effect transistor or a bipolar transistor. For instance, the eleventh transistor M11 can be selected as an NMOS transistor.

[0035] It should be noted that, as Figure 3As shown, the startup and shutdown module 101 integrates two startup paths and one shutdown path. The signal flow of startup path 1 is: power supply VDD, first resistor R1, first transistor M1, fourth transistor M4, fourth resistor R4, and eleventh transistor M11, providing initial bias power to the first reference module 102. The signal flow of startup path 2 is: power supply VDD, first resistor R1, first transistor M1, second resistor R2, third resistor R3, second transistor M2, and third transistor M3, establishing the initial operating voltage for the bias module 103. The signal flow of the shutdown path is: ninth transistor M9, tenth transistor M10, seventh transistor M7, eighth transistor M8, sixth transistor M6, fifth transistor M5, fifth resistor R5, and eleventh transistor M11, used to cut off redundant branches after subsequent modules complete startup, driving the startup and shutdown module 101 into a low-power state. That is, after startup, the eleventh transistor M11 must remain off.

[0036] It should be noted that the embodiments provided in this application only show one circuit structure as the start-up and shutdown module 101, and do not represent that only this one circuit structure can realize the function of the start-up and shutdown module 101. Other circuit structures that can realize this function can also be substituted, and are not limited to this. For example, in the variant design of the start-up and shutdown circuit module, the circuit start-up performance can be improved through two optimization schemes: First, a ramp generation circuit is added to make the bias voltage gradually increase over time, thereby suppressing the voltage overshoot phenomenon during the start-up stage and avoiding the impact of instantaneous high voltage on the device; Second, a comparator is introduced to monitor the reference voltage in real time, and realize intelligent start-up and shutdown control of the circuit based on the stable state, further reducing the standby power consumption of the module and improving the operational reliability.

[0037] In one embodiment of this application, such as Figure 4 As shown, the first reference module 102 includes an adjustment unit 1021 and a current generation unit 1022. Both the adjustment unit 1021 and the current generation unit 1022 are electrically connected to the start-up and shutdown module 101. The current generation unit 1022 is electrically connected to the adjustment unit 1021 and the bias module 103, respectively.

[0038] Specifically, the current generating unit 1022 generates a first current IPTAT based on the first node voltage VC, the second node voltage VD, the first signal VB1, and the second signal VB2, and outputs the first current IPTAT to the second reference module 104. It also generates a fourth node voltage VE and outputs the fourth node voltage VE to the adjustment unit 1021. The adjustment unit 1021 dynamically adjusts its own operating state based on the pulled-down first signal VB1, the second signal VB2, and the fourth node voltage VE to raise the first node voltage VC, accelerating the current generating unit 1022 away from the power-on degenerate bias point, and prompting the first reference module 102 to quickly establish a stable operating mode.

[0039] In one embodiment of this application, such as Figure 4 As shown, the adjustment unit 1021 includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The gate of the twelfth transistor M12 is electrically connected to the drain of the fourteenth transistor M14 and the source of the fifteenth transistor M15. The drain of the twelfth transistor M12 is electrically connected to the start-up and shutdown module 101. The source of the twelfth transistor M12 is electrically connected to the start-up and shutdown module 101 and the current generating unit 1022. The gate of the thirteenth transistor M13 is used to receive the first signal VB1. The source of the thirteenth transistor M13 is used to be electrically connected to the power supply VDD. The drain of the thirteenth transistor M13 is electrically connected to the source of the fourteenth transistor M14. The gate of the fourteenth transistor M14 is used to receive the second signal VB2. The gate of the fifteenth transistor M15 is electrically connected to the current generating unit 1022. The drain of the fifteenth transistor M15 is grounded.

[0040] Specifically, the thirteenth transistor M13 and the fourteenth transistor M14 act as signal response devices, receiving the first signal VB1 and the second signal VB2 through their gates, respectively. When both the first signal VB1 and the second signal VB2 are pulled down, the thirteenth transistor M13 and the fourteenth transistor M14 are synchronously turned on. Combined with the fifteenth transistor M15, this enables the pull-up adjustment of the voltage at node B. Since the voltage at node B directly serves as the gate drive voltage of the twelfth transistor M12, as the voltage at node B increases, the current flowing through the twelfth transistor M12 increases accordingly, thereby increasing the voltage drop across the seventh resistor R7, ultimately raising the voltage of the first node. The increase in the first node voltage VC effectively accelerates the current generating unit 1022 away from the power-on degenerate bias point, ensuring that the first reference module 102 quickly enters a stable operating state.

[0041] For example, designers can select the types of the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 according to the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors or bipolar transistors. For example, the twelfth transistor M12 can be selected as an NMOS transistor, and the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 can all be selected as PMOS transistors.

[0042] In one embodiment of this application, such as Figure 4 As shown, the current generating unit 1022 includes a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a first transistor Q1, a second transistor Q2, and an eighth resistor R8. The gate of the sixteenth transistor M16 is electrically connected to the gate of the nineteenth transistor M19, the drain of the twentieth transistor M20, and the drain of the twenty-first transistor M21, respectively, for receiving the first signal VB1. The sources of the sixteenth transistor M16 and the nineteenth transistor M19 are both electrically connected to the power supply VDD. The drain of the sixteenth transistor M16 is electrically connected to the source of the seventeenth transistor M17, and the gate of the twentieth transistor M20 is electrically connected to the gate of the seventeenth transistor M17. For receiving the second signal VB2, the source of the twentieth transistor M20 is electrically connected to the drain of the nineteenth transistor M19. The gate of the eighteenth transistor M18 is electrically connected to the gate of the twenty-first transistor M21 and the bias module 103, respectively. The drain of the eighteenth transistor M18 is electrically connected to the drain of the seventeenth transistor M17 and the adjustment unit 1021, respectively. The source of the eighteenth transistor M18 is electrically connected to the collector of the first transistor Q1. The base of the first transistor Q1 is electrically connected to the base of the second transistor Q2. For receiving the first node voltage VC, the emitter of the first transistor Q1 and the second terminal of the eighth resistor R8 are both grounded. The collector of the second transistor Q2 is electrically connected to the source of the twenty-first transistor M21. The emitter of the second transistor Q2 is electrically connected to the first terminal of the eighth resistor R8.

[0043] Specifically, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19, the twentieth transistor M20, and the twenty-first transistor M21 together constitute the Cascode current mirror bias clamp structure, which can generate and output the fourth node voltage VE according to the first signal VB1, the second signal VB2, and the second node voltage VD. It has the characteristics of simple structure, strong stability and small mismatch, and can effectively optimize power supply suppression performance.

[0044] In addition, in the selection and optimization of the current mirror structure, a folded CasCode current mirror or a Wilson current mirror can be used to replace the basic CasCode current mirror structure. Both can effectively improve the power supply rejection ratio of the circuit and enhance the ability of the reference signal to resist power supply voltage fluctuation interference. It should be noted that although this structural change can improve performance, it will correspondingly increase the topological complexity and design difficulty of the circuit.

[0045] The first transistor Q1, the second transistor Q2, and the eighth resistor R8 together constitute a positive temperature coefficient current generator. Utilizing the current-voltage characteristic and the positive temperature characteristic of the transistors (VT=kT / q, where k represents the Boltzmann constant; T represents the thermodynamic temperature; and q represents the magnitude of the charge), a first current IPTAT is generated based on the first node voltage VC. That is, the positive temperature coefficient current IPTAT=I1=I2=(VBE1-VBE2) / R8=VT*In(N2 / N1) / R8, where I1 is the current flowing through the first transistor Q1; I2 is the current flowing through the second transistor Q2; VBE1 is the voltage difference between the base and emitter of the first transistor Q1; VBE2 is the voltage difference between the base and emitter of the second transistor Q2; and N2 / N1 is the ratio of the emitter area of ​​the second transistor Q2 to that of the first transistor Q1.

[0046] It should be noted that the CasCode current mirror bias clamp structure and the positive temperature coefficient current generator constitute the feedback loop 1 of the first reference module 102. Considering stability issues, its loop gain is calculated. Considering that the voltage gain from node E to node C is approximately unity gain due to the two cascaded source followers M15 and M12, under small signal conditions, the voltage at node E can be set to approximately equal to the voltage at node C (i.e., the voltage at the fourth node VE is approximately equal to the voltage at the first node VC). The loop is to be broken between the bases of the first transistor Q1 and the second transistor Q2, and the excitation voltage source Vi is added to the base of the second transistor Q2. The voltage gain from Vi to the base Vo of the first transistor Q1 is then A(loop 1) = Vo / Vi.

[0047] If Q1 and Q2 are set to be the same type of device with transconductance of gmQ, and M17 and M16 are the same size, without considering the bulk effect and channel length modulation effect of CMOS transistors, A(loop 1) = Vo / Vi ≈ 1 / (1+gmQ*R8), and the open-loop gain of its feedback loop 1 is less than 1, that is, there is no stability problem and no compensation is required.

[0048] It should be noted that the first transistor Q1, the eighteenth transistor M18, the fifteenth transistor M15, the twelfth transistor M12, and the seventh resistor R7 together constitute the feedback loop 2 of the first reference module 102, forming a Beta-helper structure. This feedback loop 2 has a large loop gain and includes four poles: E, B, C, and F. Node E has a large output impedance and parasitic capacitance, making it the primary pole. Node F has a relatively large output resistance, and due to the large collector parasitic capacitance of the first transistor Q1, its contribution pole position is low, making it the second pole. Node C, due to the Miller effect of the collector-base coupling capacitance and its large impedance, is the third pole. Node B has relatively small output resistance and parasitic capacitance, therefore it is defined as a high-frequency pole.

[0049] It should be noted that the presence of the eighteenth transistor M18 increases the loop gain and introduces a second pole F, limiting the overall loop phase margin. Therefore, a compensation capacitor CC1 needs to be added at the dominant pole E in this loop to enhance loop stability.

[0050] In summary, addressing the issue of total dose effect (TDS) affecting bipolar junction transistors (BJTs), specifically the increase in carrier recombination rate and depletion region area due to the field oxide layer, leading to increased base current and ultimately a decrease in the current amplification factor (Beta), this application specifically designs feedback loop 2 as a damping suppression circuit against TDS. This circuit achieves its hardening effect through two core mechanisms: first, constructing a Beta-helper structure to reduce the sensitivity of the base currents of the first transistor Q1 and the second transistor Q2 to changes in the amplification factor (Beta); second, configuring independent bias power supply links for the base currents of the first transistor Q1 and the second transistor Q2, thereby reducing the dependence of the output voltage of the transient filter reference output module and the output current of the positive temperature coefficient current module on changes in the BJT amplification factor (Beta), thus improving the overall stability of the reference circuit 10 under radiation conditions. Simultaneously, feedback loop 2 designed in this application also has single-event transient immunity capabilities, adjusting the bias voltage of the stable output node C through the loop to further enhance the reliability of the reference circuit 10 under radiation conditions.

[0051] It should be noted that in conventional reference circuits 10, the core component of the positive temperature coefficient current generator, the BJT transistor, generally adopts a short-circuit connection between its collector and base. However, in the first reference module 102 of this application, the first transistor Q1 and the second transistor Q2 do not adopt a short-circuit connection between their collector and base. This reduces the dependence of the BJT transistor on the current amplification factor Beta, and reduces the impact of the total dose effect on the accuracy of the positive temperature coefficient current when Beta decays. In addition, the operating point of the transistor can be stabilized through the dynamic adjustment of the feedback loop 2, avoiding current fluctuations caused by single-event transient interference. At the same time, the Beta-helper structure further enhances the anti-radiation performance, ultimately improving the output stability and accuracy of the entire reference circuit 10 in complex radiation environments.

[0052] It should be noted that since the first node voltage VC directly acts on the base of the first transistor Q1 and the second transistor Q2, in order to ensure that the first transistor Q1 and the second transistor Q2 can conduct normally and establish a stable operating point, the first node voltage VC output by the start-stop module 10 to provide base bias power to the first transistor Q1 and the second transistor Q2 must be greater than the conduction voltage of the PN junction, and this is achieved through the current mirror feedback loop, namely VB1 and VB2.

[0053] In addition, in low-voltage process scenarios, MOSFET devices operating in the subthreshold region can be used to replace BJTs to simulate the electrical characteristics of BJTs. It should be noted that although this alternative can meet the application requirements of low-voltage processes, it will reduce the output accuracy of the reference circuit 10 to some extent.

[0054] For example, designers can select the types of the sixteenth transistor M16, seventeenth transistor M17, eighteenth transistor M18, nineteenth transistor M19, twentieth transistor M20, and twenty-first transistor M21 according to the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar transistors (BPTs). For example, the sixteenth transistor M16, seventeenth transistor M17, nineteenth transistor M19, and twentieth transistor M20 can all be PMOS transistors, and the eighteenth transistor M18 and twenty-first transistor M21 can both be NMOS transistors. Designers can also select the types of the first transistor Q1 and the second transistor Q2 according to the actual situation; for example, the first transistor Q1 and the second transistor Q2 can both be NPN transistors.

[0055] It should be noted that the embodiments provided in this application only show one circuit structure as the first reference module 102, and do not mean that only this one circuit structure can realize the function of the first reference module 102. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0056] In one embodiment of this application, such as Figure 4 As shown, the bias module 103 includes a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a twenty-sixth transistor M26, and a third transistor Q3. The gate of the twenty-second transistor M22 is used to receive the first signal VB1. The sources of both the twenty-second transistor M22 and the twenty-fifth transistor M25 are electrically connected to the power supply VDD. The drain of the twenty-second transistor M22 is electrically connected to the source of the twenty-third transistor M23. The gates of both the twenty-fifth transistor M25 and the twenty-third transistor M23 are used to receive the first signal VB1. The drain of the 25th transistor M25 is electrically connected to the gate of the 25th transistor M25 and the drain of the 26th transistor M26, respectively. The base of the 3rd transistor Q3 is electrically connected to the collector of the 3rd transistor Q3, the drain of the 23rd transistor M23, the start-up and shutdown module 101 and the first reference module 102, respectively. The emitter of the 3rd transistor Q3 is electrically connected to the gate of the 24th transistor M24, the gate of the 26th transistor M26 and the drain of the 24th transistor M24, respectively. The source of the 24th transistor M24 and the source of the 26th transistor M26 are both grounded.

[0057] Specifically, the twenty-second transistor M22 and the twenty-fifth transistor M25 serve as core driver devices, receiving the first signal VB1 and the second signal VB2 through their gates, respectively, and connecting their sources to the power supply VDD, providing a stable current input foundation for the module. The twenty-third transistor M23 receives the second signal VB2 through its gate, cooperating with the twenty-second transistor M22 to adjust the branch current distribution, and simultaneously forming a signal linkage with the third transistor Q3. The third transistor Q3 adopts a diode connection (base and collector short-circuited). During the power-on phase, it is forward-biased to the emitter junction by the node D voltage output from startup path 2, thereby triggering the twenty-fourth transistor M24 and the twenty-sixth transistor M26 to conduct, realizing the pull-down adjustment of the first signal VB1 and the second signal VB2. The pulled-down first signal VB1 and the second signal VB2 are transmitted to the first reference module 102, thereby raising the first voltage VPTAT_O, providing a larger current to the bases of the first transistor Q1 and the second transistor Q2, and promoting the rapid establishment of the first reference module 102.

[0058] It should be noted that, in terms of radiation hardening, in response to the protection requirements of single-event transient effects, the collector of the third transistor Q3 of the bias module 103 has been verified as a sensitive node under the bombardment of a single-event pulse excitation source. This branch is responsible for providing bias voltage to the gates of the eighteenth transistor M18 and the twenty-first transistor M21 of the first reference module 102, and its potential fluctuations will directly affect the working stability of the core module.

[0059] To achieve a ruggedized design, an RC single-event transient filter structure (composed of a first filter resistor RS1 and a first filter capacitor CS1) is added between the collector of the third transistor Q3 and the gate of the eighteenth transistor M18 and the twenty-first transistor M21. The parameters of RS1 and CS1 can be reasonably configured according to the filtering strength and effect requirements, which can effectively filter out transient interference signals generated by single-event pulse excitation source injection, limit the fluctuation range of critical signals within the design threshold, thereby improving the anti-interference capability of the bias module 103 output signal and ensuring the stable operation of the entire reference circuit 10 in a radiation environment.

[0060] It should be noted that in the verification stage of single-event transient response, this application uses a single-event pulse excitation source generated by TCAD device simulation for targeted testing. During the simulation, the excitation source traverses the core devices of each module of the circuit, implementing differentiated excitation strategies for different types of devices: applying a pull-up current excitation to the drain of the NMOS transistor, applying a sink current excitation to the drain of the PMOS transistor, and applying a pull-up current excitation to the collector of the BJT transistor. Simultaneously, the excitation source is injected while the entire reference circuit 10 is in normal operating condition. Furthermore, according to the actual application design requirements of the module, a threshold for the fluctuation range of the single-event pulse excitation effect can be set for the main critical signals in the circuit, thereby measuring and ensuring the radiation resistance performance of the circuit.

[0061] For example, designers can select the types of transistors M22 (22), M23 (23), M24 (24), M25 (25), and M26 (26) according to the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar transistors (BPTs). For instance, transistors M22, M23, and M25 can all be PMOS transistors, while transistors M24 and M26 can both be NMOS transistors. Designers can also select the type of transistor Q3 according to the actual situation; for example, transistor Q3 can be an NPN transistor.

[0062] It should be noted that the embodiments provided in this application only show one circuit structure as the bias module 103, and do not mean that only this one circuit structure can realize the function of the bias module 103. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0063] In one embodiment of this application, such as Figure 5As shown, the second reference module 104 includes a 27th transistor M27, a 28th transistor M28, a 29th transistor M29, a 30th transistor M30, a 31st transistor M31, a 32nd transistor M32, a 4th transistor Q4, a 9th resistor R9, a 10th resistor R10, an 11th resistor R11, and a 12th resistor R12. The source of the 27th transistor M27, the first terminal of the 10th resistor R10, and the source of the 30th transistor M30 are all electrically connected to the power supply VDD. The gates of the 27th transistor M27 and the 30th transistor M30 are both used to receive the first signal VB1. The drain of the 27th transistor M27 is electrically connected to the source of the 28th transistor M28. The gates of the 31st transistor M31 and the 28th transistor M28 are both used to receive the second signal VB2. The 31st transistor M30... The source of transistor M1 is electrically connected to the drain of transistor M30. The drain of transistor M31 is electrically connected to the first terminal of resistor R12 and current output module 105. The gate of transistor M29 is electrically connected to the drain of transistor M28 and collector of transistor Q4. The source of transistor M29 is electrically connected to the first terminal of resistor R11 and gate of transistor M32. The drain of transistor M29 is electrically connected to the second terminal of resistor R10. The source of transistor M32 is electrically connected to the base of transistor Q4 and second terminal of resistor R12. The drain of transistor M32, the second terminal of resistor R9, and the second terminal of resistor R11 are all grounded. The first terminal of resistor R9 is electrically connected to the emitter of transistor Q4.

[0064] Specifically, transistors M27 (27th), M28 (28th), M30 (30th), and M31 (31st) are current mirror transistors. The gates of both M27 and M30 receive the first signal VB1, and their sources are connected to the power supply VDD. Together with M28 and M31, whose gates receive the second signal VB2, they form a mirrored current path. The output branch current I5 can be precisely configured by adjusting the size ratio N5 / 1 between the transistors. Transistor Q4 (4th) and resistor R9 (9th) form the core bandgap branch, providing the basis for calculating the reference voltage and the first voltage VPTAT_O. The tenth resistor R10, the eleventh resistor R11, and the twelfth resistor R12 serve as voltage divider and current sampling elements. They work in conjunction with the twenty-ninth transistor M29 and the thirty-second transistor M32 to form a voltage regulation loop. The gate of the twenty-ninth transistor M29 receives the linkage signal between the drain of the twenty-eighth transistor M28 and the collector of the fourth transistor Q4. Its source drives the gate of the thirty-second transistor M32. The thirty-second transistor M32 stabilizes the base potential of the fourth transistor Q4 by adjusting the potential of its source and drain, thus ensuring the accuracy of voltage regulation.

[0065] Where the reference voltage VREF_O = VBE4 + I4*R9 = VBE4 + IPTAT*R9 = VBE4 + VT*In(N2 / N1)*R9 / R8; and combining I5 / I4 = 1 / N5, we can obtain the first voltage VPTAT_O = VREF_O + I5*R12 = VBE4 + VT*In(N2 / N1)*R9 / R8 + VT*In(N2 / N1)*R12 / (R8*N5) = VBE4 + VT*In(N2 / N1)*(R9 + R12 / N5) / R8. Where I4 is equal to the first current IPTAT; VBE4 is the voltage difference between the base and emitter of the fourth transistor Q4.

[0066] It should be noted that, in order to achieve a zero temperature coefficient for the first voltage VPTAT_O, the temperature partial derivative of the voltage expression needs to be performed and the derivative result needs to be set to zero. Based on this, the parameter solution equation is established, and then the theoretical design values ​​of the transistor emitter area ratios N1 and N2, as well as the eighth resistor R8 and the ninth resistor R9, are calculated.

[0067] It should be noted that a stability analysis was performed on the feedback loop 3 formed inside the second reference module 104. This feedback loop, composed of the fourth transistor Q4, the twenty-ninth transistor M29 (source follower), and the thirty-second transistor M32 (source follower), forms a current-sinking drive enhancement structure. Because the current mirrors M27 and M28 above point G and the common-emitter Q4 below provide a large output impedance, and because the parasitic capacitance from the collector to the substrate of Q4 is relatively large, it is defined as the primary pole. The current in the M29 branch is small, and the impedance is large, so point H is the secondary pole. Node J is the high-frequency pole. Since the impedance at node G is much greater than that at node H, there is only one pole within the feedback loop bandwidth, requiring no additional compensation. Furthermore, the reference voltage VREF_O is most sensitive to the transient excitation source response of the collector of Q4, exhibiting a large maximum fluctuation peak, but it can quickly recover to a relatively small amplitude. Therefore, a single-event transient filter capacitor, namely the second filter capacitor CS2, is added at node G. Similarly, the excitation traversal of the second reference module 104 is employed.

[0068] It should be noted that, in order to enhance the overall circuit's radiation resistance robustness, single-event transient filtering structures were added at both the first voltage VPTAT_O and the reference voltage VREF_O. Specifically, RS3 and CS3 were added at the first voltage VPTAT_O, and RS4 and CS4 were added at the reference voltage VREF_O.

[0069] For example, designers can select the types of transistors M27 (27th), M28 (28th), M29 (29th), M30 (30th), M31 (31st), and M32 (32nd) based on the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar transistors (BPTs). For instance, transistors M27, M28, M30, M31, and M32 can all be PMOS transistors, while transistor M29 can be an NMOS transistor. Designers can also select the type of transistor Q4 based on the actual situation; for example, transistor Q4 can be an NPN transistor.

[0070] It should be noted that the embodiments provided in this application only show one circuit structure as the second reference module 104, and do not mean that only this one circuit structure can realize the function of the second reference module 104. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0071] In one embodiment of this application, such as Figure 6As shown, the current output module 105 includes a 33rd transistor M33, a 34th transistor M34, a 35th transistor M35, a 36th transistor M36, a 37th transistor M37, a 38th transistor M38, a 39th transistor M39, a 40th transistor M40, a 41st transistor M41, and a 13th resistor R13. The gate of the 33rd transistor M33 is used to receive the first signal VB1. The sources of the 33rd transistor M33, the 36th transistor M36, and the 40th transistor M40 are all electrically connected to the power supply VDD. The drain of the 33rd transistor M33 is electrically connected to the source of the 34th transistor M34. The gate of the 34th transistor M34 is used to receive the second signal VB2. The drain of the 34th transistor M34 is connected to the gate of the 35th transistor M35, the drain of the 35th transistor M35, and the 39th transistor M41. The gate of M39 is electrically connected. The source of the thirty-ninth transistor M39 and the source of the thirty-fifth transistor M35 are both grounded. The drain of the thirty-ninth transistor M39 is electrically connected to the source of the thirty-eighth transistor M38. The gate of the thirty-eighth transistor M38 is electrically connected to the second reference module 104. The drain of the thirty-eighth transistor M38 is electrically connected to the gate of the thirty-seventh transistor M37, the gate of the forty-first transistor M41, and the second terminal of the thirteenth resistor R13. The gate of the thirty-sixth transistor M36 is electrically connected to the gate of the fortieth transistor M40, the drain of the thirty-seventh transistor M37, and the first terminal of the thirteenth resistor R13. The drain of the thirty-sixth transistor M36 is electrically connected to the source of the thirty-seventh transistor M37. The source of the forty-first transistor M41 is electrically connected to the drain of the fortieth transistor M40. The drain of the forty-first transistor M41 is used to output the target current IPTAT_O.

[0072] Specifically, transistors M33 (33rd) and M34 (34th) receive the first signal VB1 and the second signal VB2 through their gates, respectively, and their sources are connected to the power supply VDD. Together with transistors M35 (35th) and M39 (39th), whose sources are grounded, they form a current drive and bias branch, providing a stable base bias for the subsequent current mirror structure. Transistors M36 (36th) and M40 (40th) serve as core current mirror transistors, with their sources connected to the power supply VDD. Together with transistors M37 (37th) and M41 (41st), they construct a multi-stage current mirror path, achieving accurate current replication and transmission. Transistor M38 (38th) has its gate connected to the second reference module 104 and receives the first voltage VPTAT_O to adjust the branch current, ensuring the stability of current transmission. Resistor R13 serves as a current sampling and current limiting element, working with each transistor to optimize the branch current characteristics. The various devices work together to calculate the target current IPTAT_O based on the first voltage VPTAT_O output by the second reference module 104, and output it from the drain of the forty-first transistor M41 to provide a reliable bias current for subsequent circuits (such as ADC / DAC, power management modules, etc.). The target current IPTAT_O is a positive temperature current, and its value is determined by the size ratio of the image transistors M35 and M39, and the size ratio of M36 / M37 to M40 / M41, according to the required design. Similarly, the excitation traversal current output module 105 circuit is used.

[0073] It should be noted that, Figure 6 The drain terminals of transistors M36, M37, M38, and M39 are all sensitive points. Therefore, in the actual design and application of the target current IPTAT_O, the sensitivity of the subsequent circuit to the current fluctuation caused by single-event transient pulses should be fully considered, so as to increase its robustness in a targeted manner.

[0074] For example, designers can select the types of transistors M33 (33), M34 (34), M35 (35), M36 (36), M37 (37), M38 (38), M39 (39), M40 (40), and M41 (41) based on the actual situation; that is, they can use devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or bipolar transistors (BPS). For instance, transistors M33, M34, M36, M37, M37, M40, and M41 can all be PMOS transistors, while transistors M35, M38, and M39 can all be NMOS transistors.

[0075] It should be noted that the embodiments provided in this application only show one circuit structure as the current output module 105, and do not mean that only this one circuit structure can realize the function of the current output module 105. Other circuit structures that can realize this function can also be substituted, and are not limited to this.

[0076] In addition to the radiation hardening design considerations mentioned above, for the proposed radiation hardening design of the reference circuit 10 and its overall chip to resist single-event effects, a large bias current is used to address the current bias of the current mirror under the CasCode transistor, in accordance with design specifications, to cope with the fluctuations caused by the excitation source. In the layout design, node splitting technology is applied, with multiple sub-unit transistors Q1, Q2, Q3, and Q4 connected in parallel to distribute the circuit performance from the impact of single-event transient pulses.

[0077] It should be noted that for hardening designs to resist total dose effects, the emitter area should be as large as possible under layout specifications. Additionally, addressing the field oxide trapping charge caused by total dose effects in standard processes is crucial compared to... Figure 7 Regarding the conventional BJT layout structure in (a), this application utilizes a thin gate oxide layer (POLY) with stronger suppression of total dose effects to replace the thicker field oxide layer around the implantation region. Figure 7 As shown in (b), a thin gate oxide layer POLY was added.

[0078] like Figure 8 As shown in the illustration, this application also discloses a chip including the aforementioned reference circuit 10. The chip employing the reference circuit 10 can effectively improve its operational stability and output accuracy under radiation environments. Its dual-start path and closed-loop shutdown mechanism can quickly eliminate the power-on degenerate bias point, reducing power consumption during startup. Through multiple anti-radiation designs including a Beta-helper structure, independent bias power supply, and RC filter circuit, the Beta value attenuation caused by the total dose effect of the BJT transistor can be weakened, suppressing signal fluctuations caused by single-event transients. Simultaneously, based on the precise design of the emitter area ratio and resistance parameters, stable output of zero-temperature coefficient reference voltage and positive temperature coefficient voltage is achieved, providing reliable bias voltage and current for core functional modules such as the ADC, DAC, and power management within the chip, thereby improving the overall environmental adaptability and long-term operational reliability of the chip.

[0079] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A reference circuit, characterized in that, It includes a start-up and shutdown module, a first reference module, a bias module, a second reference module, and a current output module. The start-up and shutdown module is electrically connected to the first reference module and the bias module, respectively. The first reference module is electrically connected to the bias module, and the second reference module is electrically connected to the first reference module and the current output module, respectively. The start-up and shutdown module is used to output a first node voltage and a second node voltage during the power-on process of the reference circuit; the first reference module is used to output a first current to the second reference module according to the first node voltage, the second node voltage, a first signal, and a second signal; the bias module is used to pull down the first signal and the second signal according to the second node voltage; the start-up and shutdown module is also used to shut down according to the pulled-down first signal and the second signal after the first reference module and the bias module have started up; the second reference module is used to output a first voltage according to the first current, the first signal, and the second signal; The current output module is used to output a target current based on the first voltage, the first signal, and the second signal.

2. The reference circuit according to claim 1, characterized in that, The start-up and shutdown module includes a start-up unit, a shutdown unit, and an output unit. The start-up unit is electrically connected to the shutdown unit, the output unit, and the bias module, respectively. The output unit is electrically connected to the shutdown unit and the first reference module, respectively. The startup unit is used to output the second node voltage during the power-on process of the reference circuit, and to output the third node voltage to the shutdown unit and the output unit; the output unit is used to output the first node voltage according to the third node voltage; the shutdown unit is used to pull down the third node voltage according to the first signal and the second signal after the first reference module and the bias module have been started.

3. The reference circuit according to claim 2, characterized in that, The startup unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor. The first terminal of the first resistor, the source of the second transistor, the source of the third transistor, and the first terminal of the fourth resistor are all electrically connected to a power supply. The gate of the first transistor is electrically connected to the second terminal of the second resistor, the first terminal of the third resistor, and the gate of the fourth transistor, respectively. The source of the first transistor is electrically connected to the drain of the first transistor and the second terminal of the first resistor, respectively. The gate of the third transistor is electrically connected to the gate of the second transistor, the drain of the second transistor, and the first terminal of the second resistor, respectively. The drain of the third transistor is electrically connected to the bias module. The source of the fourth transistor is electrically connected to the second terminal of the fourth resistor. The drain of the fourth transistor is electrically connected to the shutdown unit and the output unit, respectively. The second terminal of the third resistor is grounded.

4. The reference circuit according to claim 2, characterized in that, The shutdown unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a fifth resistor. The first terminal of the fifth resistor is electrically connected to both the startup unit and the output unit. The second terminal of the fifth resistor is electrically connected to the drain of the fifth transistor. The gate of the sixth transistor is electrically connected to the drain of the sixth transistor, the source of the fifth transistor, and the gate of the eighth transistor. The sources of the sixth and eighth transistors are both grounded. The gate of the seventh transistor is electrically connected to the drain of the seventh transistor, the gate of the fifth transistor, and the drain of the ninth transistor. The source of the seventh transistor is electrically connected to the drain of the eighth transistor. The gate of the ninth transistor is used to receive the second signal. The source of the ninth transistor is electrically connected to the drain of the tenth transistor. The gate of the tenth transistor is used to receive the first signal. The source of the tenth transistor is electrically connected to the power supply.

5. The reference circuit according to claim 2, characterized in that, The output unit includes an eleventh transistor, a sixth resistor, and a seventh resistor. The gate of the eleventh transistor is electrically connected to the startup unit and the shutdown unit, respectively. The drain of the eleventh transistor is electrically connected to the second terminal of the sixth resistor and the first reference module, respectively. The source of the eleventh transistor is electrically connected to the first terminal of the seventh resistor and the first reference module, respectively. The first terminal of the sixth resistor is used to be electrically connected to the power supply, and the second terminal of the seventh resistor is grounded.

6. The reference circuit according to claim 1, characterized in that, The first reference module includes an adjustment unit and a current generation unit. Both the adjustment unit and the current generation unit are electrically connected to the start-up and shutdown module. The current generation unit is electrically connected to both the adjustment unit and the bias module. The current generating unit is used to output a first current to the second reference module based on the first node voltage, the second node voltage, the first signal, and the second signal, and to output a fourth node voltage to the adjustment unit; the adjustment unit is used to raise the first node voltage based on the first signal, the second signal, and the fourth node voltage after the pull-down.

7. The reference circuit according to claim 6, characterized in that, The regulating unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The gate of the twelfth transistor is electrically connected to the drain of the fourteenth transistor and the source of the fifteenth transistor, respectively. The drain of the twelfth transistor is electrically connected to the start-up and shutdown module. The source of the twelfth transistor is electrically connected to both the start-up and shutdown module and the current generating unit, respectively. The gate of the thirteenth transistor is used to receive the first signal. The source of the thirteenth transistor is used to be electrically connected to the power supply. The drain of the thirteenth transistor is electrically connected to the source of the fourteenth transistor. The gate of the fourteenth transistor is used to receive the second signal. The gate of the fifteenth transistor is electrically connected to the current generating unit. The drain of the fifteenth transistor is grounded.

8. The reference circuit according to claim 6, characterized in that, The current generating unit includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a first transistor, a second transistor, and an eighth resistor. The gate of the sixteenth transistor is electrically connected to the gate of the nineteenth transistor, the drain of the twentieth transistor, and the drain of the twenty-first transistor, respectively, for receiving the first signal. The sources of the sixteenth and nineteenth transistors are both electrically connected to a power supply. The drain of the sixteenth transistor is electrically connected to the source of the seventeenth transistor, and the gate of the twentyth transistor is electrically connected to the gate of the seventeenth transistor, for receiving the second signal. The source of the transistor is electrically connected to the drain of the nineteenth transistor. The gate of the eighteenth transistor is electrically connected to the gate of the twenty-first transistor and the bias module. The drain of the eighteenth transistor is electrically connected to the drain of the seventeenth transistor and the adjustment unit. The source of the eighteenth transistor is electrically connected to the collector of the first transistor. The base of the first transistor is electrically connected to the base of the second transistor, for receiving the first node voltage. The emitter of the first transistor and the second terminal of the eighth resistor are both grounded. The collector of the second transistor is electrically connected to the source of the twenty-first transistor. The emitter of the second transistor is electrically connected to the first terminal of the eighth resistor.

9. The reference circuit according to claim 1, characterized in that, The bias module includes a 22nd transistor, a 23rd transistor, a 24th transistor, a 25th transistor, a 26th transistor, and a third transistor. The gate of the 22nd transistor is used to receive the first signal. The sources of the 22nd transistor and the 25th transistor are both electrically connected to the power supply. The drain of the 22nd transistor is electrically connected to the source of the 23rd transistor. The gates of the 25th transistor and the 23rd transistor are both used to receive the second signal. The drain of the 25th transistor is electrically connected to the gate of the 25th transistor and the drain of the 26th transistor, respectively. The base of the third transistor is electrically connected to the collector of the third transistor, the drain of the 23rd transistor, the start-up and shutdown module, and the first reference module, respectively. The emitter of the third transistor is electrically connected to the gate of the 24th transistor, the gate of the 26th transistor, and the drain of the 24th transistor, respectively. The sources of the 24th transistor and the 26th transistor are both grounded.

10. The reference circuit according to claim 1, characterized in that, The second reference module includes a 27th transistor, a 28th transistor, a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 4th transistor, a 9th resistor, a 10th resistor, an 11th resistor, and a 12th resistor. The source of the 27th transistor, the first terminal of the 10th resistor, and the source of the 30th transistor are all electrically connected to the power supply. The gates of the 27th transistor and the 30th transistor are both used to receive the first signal. The drain of the 27th transistor is electrically connected to the source of the 28th transistor. The gates of the 31st transistor and the 28th transistor are both used to receive the second signal. The source of the 31st transistor is electrically connected to the drain of the 30th transistor. The drain of the thirty-first transistor is electrically connected to the first terminal of the twelfth resistor and the current output module, the gate of the twenty-ninth transistor is electrically connected to the drain of the twenty-eighth transistor and the collector of the fourth transistor, the source of the twenty-ninth transistor is electrically connected to the first terminal of the eleventh resistor and the gate of the thirty-second transistor, the drain of the twenty-ninth transistor is electrically connected to the second terminal of the tenth resistor, the source of the thirty-second transistor is electrically connected to the base of the fourth transistor and the second terminal of the twelfth resistor, the drain of the thirty-second transistor, the second terminal of the ninth resistor and the second terminal of the eleventh resistor are all grounded, and the first terminal of the ninth resistor is electrically connected to the emitter of the fourth transistor.

11. The reference circuit according to claim 1, characterized in that, The current output module includes a 33rd transistor, a 34th transistor, a 35th transistor, a 36th transistor, a 37th transistor, a 38th transistor, a 39th transistor, a 40th transistor, a 41st transistor, and a 13th resistor. The gate of the 33rd transistor is used to receive the first signal. The sources of the 33rd transistor, the 36th transistor, and the 40th transistor are all electrically connected to the power supply. The drain of the 33rd transistor is electrically connected to the source of the 34th transistor. The gate of the 34th transistor is used to receive the second signal. The drain of the 34th transistor is electrically connected to the gate of the 35th transistor, the drain of the 35th transistor, and the gate of the 39th transistor. The sources of the thirty-ninth transistor and the thirty-fifth transistor are both grounded. The drain of the thirty-ninth transistor is electrically connected to the source of the thirty-eighth transistor. The gate of the thirty-eighth transistor is electrically connected to the second reference module. The drain of the thirty-eighth transistor is electrically connected to the gate of the thirty-seventh transistor, the gate of the forty-first transistor, and the second terminal of the thirteenth resistor. The gate of the thirty-sixth transistor is electrically connected to the gate of the fortyth transistor, the drain of the thirty-seventh transistor, and the first terminal of the thirteenth resistor. The drain of the thirty-sixth transistor is electrically connected to the source of the thirty-seventh transistor. The source of the forty-first transistor is electrically connected to the drain of the fortyth transistor. The drain of the forty-first transistor is used to output the target current.

12. A chip, characterized in that, Includes the reference circuit as described in any one of claims 1-11.

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