Layout design method and device for MEMS mask layout and storage medium

Abstract

The invention discloses a layout design method and equipment for an MEMS mask layout and a storage medium, and the layout design method for the MEMS mask layout comprises the steps: determining the sparse degree of a plurality of local regions in the photoetching mask layout, and filling the local regions with corresponding false patterns according to the sparse degree; according to the method, false patterns are adopted in a photoetching mask layout, corresponding false patterns are adopted for areas with different mask layout light penetration rates, the yield of the chemical mechanical polishing process in the manufacturing process of the tip of the MEMS probe is improved, and particularly the uniformity in a film plane of a wafer after CMP (Chemical Mechanical Polishing) is improved; the microcosmic load effect capability of the CMP process is improved, and the dished depression and lateral erosion depression defect degree in the CMP process is improved, so that the reliability of the tip of the MEMS probe and the yield in the corresponding assembling and bonding process can be improved.

Description

Technical Field

[0001] This invention relates to the field of 2D MEMS probe manufacturing technology, and specifically to a method, apparatus and storage medium for laying out a mask pattern for 2D MEMS probes. Background Technology

[0002] In MEMS manufacturing, chemical mechanical planarization (CMP) is a crucial planarization process. CMP, when polishing the wafer surface, essentially uses chemical etching combined with mechanical grinding to achieve directional removal with "high convexity and low segregation," aiming to make the wafer surface sufficiently flat to provide a suitable focal plane for the next photolithography step. Currently, the photolithographic mask layout used in the entire probe card does not employ a special dummy pattern, resulting in poor uniformity in the metal chemical mechanical polishing (CMP) process. This leads to: 1) dish-shaped depressions, where metal linewidth areas are "self-lost"; and 2) erosion, where high-density patterns "regionally collapse." This directly affects the yield in the integration process and the final yield of the MEMS probe. Common solutions and improvements include dummy fill, which involves adding filler to sparse areas to adjust the average density of the region by increasing physical materials, thus improving local density consistency. However, this approach carries risks to the reliability of the MEMS probe tip and its assembly with the ceramic substrate (MLC) required by the probe card. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this paper provides a layout design method, device, and storage medium for MEMS mask patterns. By employing a special dummy pattern during the design process of the photolithographic mask pattern, and using corresponding dummy patterns for areas with different light transmittance, the yield of chemical mechanical polishing (CMP) during the fabrication of MEMS probe tips is improved, especially the in-plane uniformity of the wafer. This enhances the micro-loading capability of CMP, mitigates dishing and erosion defects in the CMP process, and ultimately improves the reliability of MEMS probe tips and the yield during the corresponding assembly and bonding process.

[0004] To address the above problems, the present invention provides the following technical solution: In a first aspect, embodiments of this application provide a layout design method for a MEMS mask pattern, applied to a photolithographic mask pattern for manufacturing MEMS probe tips, including: determining the sparsity of multiple local regions in the photolithographic mask pattern; Based on the sparsity, fill the corresponding fake graphics into multiple local regions.

[0005] In some implementations, the sparsity of multiple local regions in the photomask layout is determined, and corresponding dummy patterns are filled into the multiple local regions according to the sparsity, including: The light transmittance of multiple local regions in the photolithographic mask pattern is determined. The light transmittance is positively correlated with the sparsity. The light transmittance is determined based on the light-transmitting area or the opaque area of ​​the local region. Based on the light transmittance of the local area, fill the corresponding fake shapes into multiple local areas.

[0006] In some embodiments, the local light transmittance of multiple local regions in the photolithographic mask pattern is determined, wherein the light transmittance is determined based on the light-transmitting area or the opaque area of ​​the local region, including: The entire area of ​​the photolithographic mask pattern is divided into multiple local areas. The light transmittance of the local area is the ratio of the light-transmitting area of ​​the local area to the total area of ​​the local area × 100%, or 1 minus the ratio of the area of ​​the opaque area to the total area of ​​the local area × 100%.

[0007] In some implementations, filling corresponding dummy graphics into multiple local areas includes: For at least one of the local regions, different shapes of dummy patterns are selected to fill multiple local regions based on their light transmittance.

[0008] In some implementations, for at least one of the said local regions, different dummy patterns of varying shapes are selected to fill multiple local regions based on their light transmittance, including: According to the preset light transmittance range, the light transmittance range includes a first light transmittance range, a second light transmittance range, and a third light transmittance range, sorted from high to low. When the light transmittance of the local area is within the first light transmittance range, a regular polygonal dummy shape is selected to fill the local area. When the light transmittance of the local area is within the second light transmittance range, a circular or elliptical dummy shape is selected to fill the local area; When the light transmittance of the local area is within the third light transmittance range, a long strip-shaped dummy graphic is selected to fill the local area.

[0009] In some embodiments, the first light transmittance range is [80%-95%), the second light transmittance range is [60%-80%), and the third light transmittance range is [40%-60%).

[0010] In some implementations, the entire area of ​​the photomask pattern is divided into multiple local regions, including: The entire area of ​​the photolithographic mask pattern is a two-dimensional planar region, and the area of ​​a single local region is 10μm×10μm, 50μm×50μm, or 100μm×100μm.

[0011] In some implementations, based on a preset light transmittance range, which includes a first light transmittance range, a second light transmittance range, and a third light transmittance range ordered from high to low, a pseudo-shape is selected to fill the local area according to the light transmittance range in which the local area is located, including: The first light transmittance interval is divided into multiple sub-intervals. For the sub-intervals with light transmittance from high to low, regular N-gon pseudo-shapes are selected in sequence, where N is a positive integer and the initial value of N is 4. The second light transmittance range is divided into multiple sub-ranges. For sub-ranges with light transmittance from high to low, fake patterns and elliptical fake patterns sorted from low to high eccentricity are selected in sequence. The third light transmittance range is divided into multiple sub-ranges. For each sub-range with light transmittance from high to low, long strip-shaped pseudo-figures are selected in descending order of aspect ratio.

[0012] Secondly, embodiments of this application provide a layout design apparatus for MEMS mask patterns, the MEMS mask layout design apparatus comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the MEMS mask layout design method as described in the first aspect.

[0013] Thirdly, embodiments of this application provide a computer-readable storage medium storing an executable program, which is executed by a processor to implement the MEMS mask layout design method as described in the first aspect.

[0014] This application provides a layout design method, device and storage medium for MEMS mask patterns. In the design process of the photolithographic mask pattern of MEMS probe tips, this application adopts a special dummy pattern. For local areas with different light transmittance, the corresponding dummy pattern is filled into multiple local areas to improve the reliability of the finished MEMS probe tips and the yield in the corresponding assembly and bonding process. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the layout design method for MEMS mask patterns provided in the embodiments of this application.

[0016] Figure 2 This is a schematic diagram of the layout of the MEMS mask provided in the embodiments of this application.

[0017] Figure 3 This is a schematic diagram of the structure of a MEMS mask layout design device provided in an embodiment of this application.

[0018] Figure 4 This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] The layout design method of the MEMS mask pattern provided in this application will be described in detail below with reference to the accompanying drawings.

[0022] Please see Figure 1 , Figure 1 This is a flowchart illustrating the layout design method for MEMS mask patterns provided in an embodiment of this application. Figure 1 As shown, the layout design method of the MEMS mask pattern includes steps S100 to S200.

[0023] Step S100: Determine the sparsity of multiple local regions in the photomask pattern.

[0024] For example, Figure 2The diagram illustrates the structure of a photolithographic mask layout. In this embodiment, the photolithographic mask layout serves as the design for manufacturing MEMS probe tips. It is crucial that the photolithographic mask layout creates a uniform polishing environment to mitigate defects such as dishing and erosion in subsequent CMP processes, thereby improving the yield of MEMS probe tips. The CMP process on the wafer involves two steps: rough grinding to remove large copper areas and light polishing for fine-tuning. The polishing effect of CMP depends on the pattern design of the photolithographic mask layout. Therefore, it is essential to guide the CMP equipment beforehand using methods such as virtual filling to achieve a better, more uniform polishing effect. However, existing technologies only fill sparse areas with dummy patterns without selecting appropriate dummy patterns for different sparseness levels, resulting in an uneven polishing environment during the CMP process and affecting the yield of MEMS probe tips after the CMP process.

[0025] In some implementations, the entire area of ​​the photomask layout is a two-dimensional planar region, including the device pattern. The photomask layout is divided into multiple local regions, and the area of ​​a single local region is 10μm×10μm, 50μm×50μm, or 100μm×100μm. In this embodiment, the area of ​​a single local region is 10μm×10μm.

[0026] In some implementations, the sparsity of multiple local regions in the photomask pattern is determined by calculating the light transmittance of the multiple local regions in the photomask pattern. The light transmittance is positively correlated with the sparsity. The light transmittance is determined based on the light-transmitting area or the opaque area of ​​the local region. Specifically, the light transmittance is the ratio of the light-transmitting area of ​​the local region to the total area of ​​the local region × 100%, or 1 minus the ratio of the area of ​​the opaque area to the total area of ​​the local region × 100%.

[0027] Step S200: Based on the light transmittance of the local region, fill the multiple local regions with corresponding dummy patterns that are independent of the device pattern.

[0028] In some implementations, for at least one of the local regions, different shapes of dummy patterns are selected to fill multiple local regions based on their light transmittance.

[0029] In some implementations, based on a preset light transmittance range, if the light transmittance of the current local area falls into a certain light transmittance range, a dummy shape of the corresponding shape is selected to fill the local area. The dummy shape includes at least one of a regular polygonal dummy shape, a circular or elliptical dummy shape, and a strip-shaped dummy shape.

[0030] The light transmittance range includes a first light transmittance range, a second light transmittance range, and a third light transmittance range, ordered from high to low. In this embodiment, the first light transmittance range is [80%-95%]. Local areas with light transmittance higher than 95% are not considered because the photomask layout has a Pad layer with a transmittance as high as 95%-97%. The second light transmittance range is [60%-80%]. The third light transmittance range is [40%-60%]. When the light transmittance of a local area falls within the first light transmittance range, a regular polygonal dummy shape is selected to fill the local area. When the light transmittance of a local area falls within the second light transmittance range, a circular or elliptical dummy shape is selected to fill the local area. When the light transmittance of a local area falls within the third light transmittance range, a long strip dummy shape is selected to fill the local area.

[0031] In some embodiments, the first light transmittance range is divided into multiple sub-ranges. For sub-ranges with light transmittance from high to low, regular N-gon pseudo-shapes are selected sequentially, where N is a positive integer and the initial value of N is 4. The second light transmittance range is divided into multiple sub-ranges. For sub-ranges with light transmittance from high to low, circular pseudo-figures and elliptical pseudo-figures sorted by eccentricity from low to high are selected in sequence. The third light transmittance range is divided into multiple sub-ranges. For each sub-range with light transmittance from high to low, long strip-shaped pseudo-figures are selected in descending order of aspect ratio.

[0032] In this embodiment, regular polygonal pseudo-shapes are used to fill local areas within the first light transmittance range. These local areas have high transmittance and high sparseness; using regular polygonal pseudo-shapes provides greater support. Regular polygons have good structural stability. Specifically, the regular polygon structure can be a regular polygon with a number of sides other than a square. As the number of sides increases, the support and structural stability of a regular polygon decreases, but its support and structural stability are still greater than that of a circle. The first light transmittance range can be further refined by dividing it into multiple sub-ranges. For example, for the sub-range [90%-95%), a square pseudo-shape with optimal support and structural stability can be used; for the sub-range [85%-90%), a regular pentagonal pseudo-shape with slightly lower support and structural stability can be used; for the sub-range [80%-85%), a regular hexagonal pseudo-shape can be used, and so on, with different choices made as needed. By further refining the first light transmittance range, a better uniform polishing effect is achieved.

[0033] Regular polygons have better support and structural stability than circles because if a regular polygon has an infinite number of sides, it will approach a circle. However, the stress distribution of a regular polygon is more concentrated than that of a circle.

[0034] In this embodiment, circular or elliptical pseudo-patterns are used to fill local areas within the second light transmittance range. These local areas have moderate transmittance and moderate sparsity. Circular or elliptical patterns provide moderate support because they have no sharp corners, allowing stress to be evenly distributed along smooth edges. This provides a uniform transition to the moderately sparse local areas, preventing stress concentration. Specifically, the greater the eccentricity of the ellipse, the higher its flatness. The second light transmittance range can be divided into multiple sub-ranges. For sub-ranges with higher light transmittance, circular or similar elliptical pseudo-patterns can be used; for sub-ranges with lower light transmittance, more flattened elliptical pseudo-patterns can be used, and so on, allowing for different selections as needed. By further refining the division of the second light transmittance range, a better uniform polishing effect is achieved.

[0035] In this embodiment, elongated dummy patterns are used to fill local areas within the third light transmittance range. These elongated dummy patterns possess a certain degree of deformation capability. In this embodiment, they are mainly distributed at the edges of the wafer, and their positions can be redistributed through elastic deformation. Local areas within the third light transmittance range have a larger opaque area and are sparser in terms of light transmission compared to opaque areas, resulting in lower stiffness and greater flexibility. When elongated dummy patterns are placed in these local areas, they undergo elastic deformation upon contact with harder, opaque areas, thus redistributing their positions and moving towards the softer, more transparent areas. Specifically, the larger the aspect ratio of the elongated pattern, the higher its deformation capability. The third light transmittance range can be divided into multiple sub-ranges, and elongated dummy patterns with different aspect ratios can be selected according to requirements. The lower the light transmittance, the larger the aspect ratio of the required elongated shape. By further refining the division of the third light transmittance range, a better uniform polishing effect is achieved. It should be noted that the elongated shape in this embodiment can be other shapes such as wavy or spring-like.

[0036] refer to Figure 2 , Figure 2The diagram shows the photomask layout after filling with corresponding dummy patterns. The photomask layout is composed of many photomask layers. Different colors in the diagram represent different photomask layers. Square dummy patterns are marked in magenta, circular dummy patterns are marked in red, and elongated dummy patterns are marked in green. When the CMP equipment performs polishing operations based on this photomask layout, the photomask layout provided in this embodiment offers the CMP equipment a uniform environment, meaning the pattern density tends to be consistent, thus improving the yield of MEMS probe tips.

[0037] In summary, the MEMS mask layout design method provided in this application has the following advantages: 1. By determining the sparsity of multiple local regions in the photomask layout, and then filling the multiple local regions with corresponding dummy patterns according to the sparsity, targeted filling of regions with different sparsity can be performed to achieve the effect of making the pattern structure density of the entire photomask layout more consistent.

[0038] 2. By setting the shapes of the dummy patterns to three types—regular polygons, circles, and rectangles—and setting three light transmittance ranges, the method utilizes the characteristics of regular polygons having better support than circles, circles having moderate support and being able to uniformly distribute stress, and rectangles being able to deform. For areas with high light transmittance, regular polygonal dummy patterns are filled first; for areas with medium light transmittance, circular dummy patterns are filled first; and for areas with low light transmittance, rectangles are used to utilize their deformation ability to dissipate stress, making the pattern structure density of the entire photolithography mask layout tend to be consistent.

[0039] 3. Furthermore, the three light transmittance ranges can be further refined. For the sub-ranges of the first light transmittance range, which is from high to low, regular N-gonal pseudo-patterns are selected sequentially, where N is a positive integer and its initial value is 4. For the sub-ranges of the second light transmittance range, which is from high to low, circular and elliptical pseudo-patterns with eccentricity sorted from low to high are selected sequentially. For the sub-ranges of the third light transmittance range, which is from high to low, long strip pseudo-patterns with aspect ratio sorted from large to small are selected sequentially. This allows for refinement as needed to achieve a more uniform pattern density across the entire photolithography mask layout.

[0040] The MEMS mask layout design method of this embodiment is used to fill the photolithographic mask layout with a fake pattern. Then, based on the photolithographic mask layout, the CMP process is used to planarize the surface of multiple wafers. After that, the multiple wafers are photolithographically etched and deeply etched to finally process multiple probe tips. Multiple residual films that have not been completely removed are left on each wafer.

[0041] Multiple residual films are inspected, and the parameters to be inspected include in-wafer uniformity (WIW), wafer-to-wafer uniformity (WTW), and batch-to-batch uniformity (LTL). WIW refers to whether the thickness of multiple residual films on a single wafer is consistent; WTW refers to whether the thickness of residual films on multiple wafers processed in the same batch is consistent based on the photolithography mask layout of this embodiment; LTL refers to whether the thickness of residual films on multiple wafers processed in different batches is consistent based on the photolithography mask layout of this embodiment.

[0042] Furthermore, defects on the wafer surface are detected, and the actual results are verified. Through the MEMS mask layout design method of this embodiment, the process parameters are further adjusted based on the detection results, and the range of experimental conditions (DOE) of the design process parameters is optimized, ultimately improving the yield of the probe tip by more than 15%.

[0043] After assembling 2D probe tips onto a ceramic substrate (MLC) and soldering them, the yield of good and bad probe tips is statistically analyzed, and reliability testing is performed to determine the yield. Based on the collected actual data, the yield of each wafer can be improved by 10% through the MEMS mask layout design method of this embodiment.

[0044] Please see Figure 3 , Figure 3 This is a schematic diagram of a MEMS mask layout design device provided in an embodiment of this application. Figure 3 As shown, the MEMS mask layout design device 400 includes: one or more processors 410 and a memory 420. Figure 3 Take a processor 410 as an example.

[0045] In some implementations, the processor 410 and the memory 420 may be connected via a bus or other means. Figure 3 Taking the example of a connection between China and Israel via a bus.

[0046] In some implementations, the processor 410 is configured to determine the sparsity of multiple local regions in the photomask layout and, based on the sparsity, fill the multiple local regions with corresponding dummy patterns.

[0047] In some implementations, memory 420 serves as a non-volatile computer-readable storage medium, used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules of the MEMS mask layout design method in the embodiments of this application. Processor 410 executes the various functional applications and data processing of the MEMS mask layout design device 400 by running the non-volatile software programs, instructions, and modules stored in memory 420, thereby implementing the MEMS mask layout design method of the above-described method embodiments.

[0048] In some embodiments, memory 420 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created by using the MEMS mask layout design device 400, etc. Furthermore, memory 420 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 420 may optionally include memory remotely located relative to processor 410, and this remote memory may be connected to the controller via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0049] In some implementations, one or more modules are stored in memory 420 and, when executed by one or more processors 410, perform the MEMS mask layout design method in any of the above method embodiments, for example, performing the above-described... Figure 1 The method steps S100 to S200.

[0050] In some implementations, the MEMS mask layout design device 400 can be a chip, such as a data processing unit (DPU) chip used in a data center. Alternatively, the MEMS mask layout design device can be a network interface card that includes a chip and multiple interfaces (such as PCI / PCIE interfaces, UART interfaces, USB interfaces, etc.). Or, the MEMS mask layout design device 400 can also be a traditional server, or a server that includes a network interface card or a chip. The server includes a host and a data processor. The data processor is used to schedule packets to the host or the data processor itself for processing. The host is used to process the packets scheduled by the data processor.

[0051] Please refer to Figure 4 , Figure 4This is a structural block diagram of a computer-readable storage medium provided in an embodiment of this application. The computer-readable storage medium 500 stores program code 510, which can be called by a processor to execute the MEMS mask layout design method described in the above method embodiments.

[0052] The computer-readable storage medium 500 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium 500 has storage space for program code that performs any of the method steps of the layout design method for the MEMS mask pattern described above. This program code can be read from or written to one or more computer program products. The program code may be compressed, for example, in a suitable form.

[0053] In summary, this application provides a layout design method, a layout design device, and a storage medium for MEMS mask patterns. The layout design method includes determining the sparsity of multiple local regions in the photolithographic mask pattern; filling corresponding dummy patterns into the multiple local regions according to the sparsity, which can reduce the computational load and thus improve the yield of chemical mechanical polishing (CMP) during the fabrication of MEMS probe tips, especially the in-plane uniformity of the wafer; improving the micro-loading effect of CMP, and mitigating dishing and erosion defects in the CMP process, thereby improving the reliability of MEMS probe tips and the yield of the corresponding assembly bonding process.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A layout design method for MEMS mask patterns, characterized in that, In a photolithographic mask layout used for fabricating MEMS probe tips, the method includes: Determine the pattern density sparsity of multiple local regions in the photomask layout; Based on the density of the graphic, fill the corresponding fake graphics into multiple local areas.

2. The MEMS mask layout design method according to claim 1, characterized in that, Determine the sparsity of multiple local regions in the photolithographic mask layout, and fill the multiple local regions with corresponding dummy patterns according to the sparsity, including: The light transmittance of multiple local regions in the photolithographic mask pattern is determined. The light transmittance is positively correlated with the sparsity. The light transmittance is determined based on the light-transmitting area or the opaque area of ​​the local region. Based on the light transmittance of the local area, fill the corresponding fake shapes into multiple local areas.

3. The MEMS mask layout design method according to claim 2, characterized in that, Determining the local light transmittance of multiple local regions in the photolithographic mask pattern, wherein the light transmittance is determined based on the light-transmitting area or the opaque area of ​​the local region, including: The entire area of ​​the photolithographic mask pattern is divided into multiple local areas. The light transmittance of the local area is the ratio of the light-transmitting area of ​​the local area to the total area of ​​the local area × 100%, or 1 minus the ratio of the area of ​​the opaque area to the total area of ​​the local area × 100%.

4. The MEMS mask layout design method according to claim 2, characterized in that, Fill the corresponding fake shapes into multiple local areas, including: For at least one of the local regions, different shapes of dummy patterns are selected to fill multiple local regions based on their light transmittance.

5. The MEMS mask layout design method according to claim 4, characterized in that, For at least one of the local regions, different shapes of dummy patterns are selected to fill multiple local regions based on their light transmittance, including: According to the preset light transmittance range, which includes a first light transmittance range, a second light transmittance range, and a third light transmittance range sorted from high to low, a pseudo-shape is selected to fill the local area according to the light transmittance range in which the local area is located. When the light transmittance of the local area is within the first light transmittance range, a regular polygonal dummy shape is selected to fill the local area. When the light transmittance of the local area is within the second light transmittance range, a circular or elliptical dummy shape is selected to fill the local area; When the light transmittance of the local area is within the third light transmittance range, a long strip-shaped dummy graphic is selected to fill the local area.

6. The MEMS mask layout design method according to claim 5, characterized in that, The first light transmittance range is [80%-95%], the second light transmittance range is [60%-80%], and the third light transmittance range is [40%-60%].

7. The MEMS mask layout design method according to claim 3, characterized in that, The entire photolithographic mask pattern is divided into multiple local regions, including: The entire area of ​​the photolithographic mask pattern is a two-dimensional planar region, and the area of ​​a single local region is 10μm×10μm, 50μm×50μm, or 100μm×100μm.

8. The MEMS mask layout design method according to claim 5, characterized in that, According to a preset light transmittance range, which includes a first light transmittance range, a second light transmittance range, and a third light transmittance range sorted from high to low, a pseudo-shape is selected to fill the local area based on the light transmittance range in which the local area is located, including: The first light transmittance interval is divided into multiple sub-intervals. For the sub-intervals with light transmittance from high to low, regular N-gon pseudo-shapes are selected in sequence, where N is a positive integer and the initial value of N is 4. The second light transmittance range is divided into multiple sub-ranges. For sub-ranges with light transmittance from high to low, circular pseudo-figures and elliptical pseudo-figures sorted by eccentricity from low to high are selected in sequence. The third light transmittance range is divided into multiple sub-ranges. For each sub-range with light transmittance from high to low, long strip-shaped pseudo-figures are selected in descending order of aspect ratio.

9. A layout design device for MEMS mask patterns, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the MEMS mask layout design method as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an executable program, which is executed by a processor to implement the MEMS mask layout design method as described in any one of claims 1 to 8.

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