Semiconductor device

Abstract

Provided is a highly reliable semiconductor device in which an insulating circuit board on which a power semiconductor chip is mounted is sealed with a highly heat-resistant epoxy resin, the semiconductor device being capable of suppressing peeling between the highly heat-resistant epoxy resin and wiring of the insulating circuit board. The present invention is characterized by comprising: a power semiconductor chip; an insulating circuit board on which the power semiconductor chip is mounted; and a sealing resin that seals at least the power semiconductor chip and a bonding portion between the insulating circuit board and the power semiconductor chip, the insulating circuit board having a ceramic substrate and a surface wiring layer formed on a surface of the ceramic substrate. The surface wiring layer has a first roughened layer on a surface opposite to a bonding surface with the ceramic substrate.

Description

Technical Field

[0001] This invention relates to the structure of a semiconductor device, and more particularly to a power module in which an insulating circuit board carrying a power semiconductor chip is sealed with a high heat-resistant epoxy resin (resin) and a method for manufacturing the same. Background Technology

[0002] As an insulation and sealing method for power modules, a potting technology has been developed that enables sealing with high-heat-resistant epoxy resin without the need for molds. High-heat-resistant epoxy resin has an elastic modulus of over 100 GPa at room temperature. Through mechanical constraint, it can reduce thermal stress caused by the difference in the coefficients of linear expansion of the circuit formation portions formed on semiconductor chips and insulating substrates, thus promising a longer power cycle life.

[0003] As background technology in this field, there is, for example, technology like Patent Document 1. Patent Document 1 discloses "a power module comprising: semiconductor elements disposed on a substrate; a plate-shaped electrode plate having two or more connection portions for connecting the semiconductor elements to each other, the semiconductor elements to external terminals, or the substrate to the external terminals; a resin molding portion having an inclined, convex shape on the substrate surface side between adjacent connection portions of the electrode plate; and a sealing resin portion for sealing the periphery of the connection portions."

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2019-197842 Summary of the Invention

[0007] The problem that the invention aims to solve

[0008] The insulating substrate of the power module used in power devices is made of ceramics such as alumina (Al2O3), silicon nitride (Si3N4), and aluminum nitride (AlN). Additionally, the wiring uses copper (Cu) or aluminum (Al).

[0009] In the connection between the ceramic substrate and wiring of the insulating circuit board, the method of connection by silver solder has been used in the past. However, recently, DCB substrates (Direct Bonded Copper) with copper material directly bonded to the ceramic substrate and AMB substrates (Active Metal Braze) with active metals such as titanium (Ti) are developed, which have lower cost and higher temperature cycling reliability.

[0010] Regarding the coefficient of linear expansion of ceramics, alumina has a coefficient of 7.2 × 10⁻⁶.-6 / K, silicon nitride is 2.8×10 -6 / K, aluminum nitride is 4.6×10 -6 / K. On the other hand, the coefficient of linear expansion of copper is 16.5 × 10⁻⁶. -6 / K, the coefficient of linear expansion of aluminum is 23.9×10 -6 / K.

[0011] The coefficient of linear expansion of high heat-resistant epoxy resin sealant varies from 10 to 20 × 10⁻⁶ depending on the amount of resin material or added filler. -6 / K. Due to the difference in the coefficients of linear expansion between the high-heat-resistant epoxy sealant and the ceramic, thermal stress is generated between the high-heat-resistant epoxy and the wiring. This thermal stress can potentially cause delamination between the high-heat-resistant epoxy and the wiring. If delamination occurs, the mechanical binding force of the high-heat-resistant epoxy decreases, thereby increasing thermal stress and reducing power cycling performance.

[0012] However, silicon nitride (Si3N4) is used in the insulating substrate of power modules for power devices with withstand voltages of 750V and 1200V used in inverters of electric vehicles (EVs). This is because its thermal conductivity is lower than that of aluminum oxide (Al2O3), and it has high flexural strength (for this reason), allowing for a thinner substrate and thus reducing thermal resistance.

[0013] On the other hand, silicon nitride (Si3N4) has a smaller coefficient of linear expansion than other ceramics, and the thermal stress between the high heat-resistant epoxy resin and the wiring is relatively large.

[0014] In the aforementioned patent document 1, the thermal stress between the high heat-resistant epoxy resin and the wiring of the insulating circuit board was not considered, leaving room for improvement.

[0015] Therefore, the object of the present invention is to provide a highly reliable semiconductor device that, in a semiconductor device in which an insulating circuit board on which a power semiconductor chip is mounted is sealed with a high heat-resistant epoxy resin, can suppress the peeling between the high heat-resistant epoxy resin and the wiring of the insulating circuit board.

[0016] Methods for solving problems

[0017] To address the aforementioned issues, the present invention is characterized by comprising: a power semiconductor chip; an insulating circuit board on which the power semiconductor chip is mounted; and a sealing resin that at least seals the junction of the power semiconductor chip and the insulating circuit board with the power semiconductor chip, wherein the insulating circuit board has a ceramic substrate and a surface wiring layer formed on the surface of the ceramic substrate, and the surface wiring layer has a first roughening layer on the side opposite to the junction surface of the surface wiring layer and the ceramic substrate.

[0018] Invention Effects

[0019] According to the present invention, in a semiconductor device in which an insulating circuit board on which a power semiconductor chip is mounted is sealed using a high heat-resistant epoxy resin, a highly reliable semiconductor device can be realized that can suppress the peeling between the high heat-resistant epoxy resin and the wiring of the insulating circuit board.

[0020] This enables the power module to achieve a longer power cycle life.

[0021] Other issues, structures, and effects not mentioned above will be clarified through the following description of the implementation methods. Attached Figure Description

[0022] Figure 1 This is a perspective view of the power module of Embodiment 1 of the present invention.

[0023] Figure 2 It means Figure 1 The diagram shows the back and side of the power module.

[0024] Figure 3 It means Figure 1 A top view of the power module with the high heat-resistant epoxy resin 3 removed.

[0025] Figure 4 yes Figure 3 A sectional view of section A-A'.

[0026] Figure 5 It means to Figure 4 A diagram showing a portion sealed with high heat-resistant epoxy resin 3.

[0027] Figure 6A This is a diagram illustrating a portion of the manufacturing process of the power module according to Embodiment 2 of the present invention.

[0028] Figure 6B It means to continue Figure 6A A diagram of the manufacturing process.

[0029] Figure 7A This is a partial cross-sectional view of the power module involved in Embodiment 3 of the present invention.

[0030] Figure 7B yes Figure 7A The roughening layer 30 is viewed in the B-B' direction (top view). Detailed Implementation

[0031] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. Furthermore, the same reference numerals are used to denote the same structures in the drawings, and detailed descriptions of repeated parts are omitted.

[0032] Example 1

[0033] Reference Figures 1 to 5 The semiconductor device according to Embodiment 1 of the present invention will be described.

[0034] Figure 1 This is a perspective view of the power module 100 in this embodiment. Figure 2 It means Figure 1 The diagram shows the back and side of the power module 100. Figure 3 It means Figure 1 A top view of the power module 100 with the high heat-resistant epoxy resin 3 removed. Figure 4 yes Figure 3 A sectional view of section A-A'. Figure 5 It means to Figure 4 A diagram showing a portion sealed with high heat-resistant epoxy resin 3.

[0035] like Figure 1 As shown, in this embodiment, the power module 100 uses an adhesive to bond the housing 2 to the metal base 1. The housing 2 is filled with high heat-resistant epoxy resin 3 by potting.

[0036] In addition, such as Figure 2 As shown, the power module 100 of this embodiment has a plurality of fins 4 on the metal base 1. The fins 4 are disposed on the back side of the metal base 1, that is, on the side opposite to the surface side on which the power semiconductor chip is mounted. By installing a water cooling device such as a water jacket or an air cooling device on the back side of the metal base 1, the heat generated from the power semiconductor chip that accompanies the operation of the power module 100 is dissipated through the fins 4.

[0037] like Figure 3 As shown, this embodiment illustrates the use of an IGBT (Insulated Gate Bipolar Transistor) and a diode connected in parallel with the IGBT as power devices. Furthermore, this embodiment is a 6-inch integrated power module 100 with six arms (U, V, W phases and upper and lower arms) mounted on a single power module.

[0038] An insulating circuit board 10 is provided on a metal base 1. An IGBT 11 and a diode 12 are provided on the insulating circuit board 10, and the IGBT 11 and the diode 12 are connected by a lead frame 13.

[0039] like Figure 4As shown, an insulating circuit board 10 is disposed on a metal base 1 connected to fins 4. The insulating circuit board 10 is composed of a ceramic substrate 14, a back wiring layer 21, and a surface wiring layer 22. The insulating circuit board 10 is connected to the metal base 1 by solder 20 disposed between the back wiring layer 21 and the metal base 1. The back sides of the IGBT 11 and the diode 12 are respectively connected to the surface wiring layer 22 by solder 23.

[0040] Thus, the heat generated from IGBT11 and diode 12 is transferred through solder 23, surface wiring layer 22, ceramic substrate 14, back wiring layer 21, solder 20, metal base 1, and fins 4 to cooling media such as cooling water and air (not shown in this figure), thereby cooling IGBT11 and diode 12.

[0041] In addition, IGBT 11 and diode 12 are insulated from metal base 1 via ceramic substrate 14. The surfaces of IGBT 11 and diode 12 are connected to lead frame 13 via solder 24.

[0042] like Figure 5 As shown, the power module 100 of this embodiment has a roughening layer 30 on the surface wiring layer 22. By providing the roughening layer 30, the binding force between the high heat-resistant epoxy resin 3 and the surface wiring layer 22 can be mechanically improved by utilizing the anchoring effect, thereby preventing peeling caused by thermal stress.

[0043] The roughening layer 30 on the surface of the surface wiring layer 22 is formed, for example, by etching the surface of the surface wiring layer 22. Alternatively, in the case where the surface wiring layer 22 is formed of copper (Cu), a roughening nickel plating layer may also be formed on the surface wiring layer 22 as the roughening layer 30.

[0044] As described above, the power module 100 of this embodiment includes a power semiconductor chip (IGBT 11, diode 12), an insulating circuit board 10 on which the power semiconductor chip is mounted, and a sealing resin (high heat-resistant epoxy resin 3) that seals at least the junction of the power semiconductor chip and the insulating circuit board 10 with the power semiconductor chip. The insulating circuit board 10 has a ceramic substrate 14 and a surface wiring layer 22 formed on the surface of the ceramic substrate 14. The surface wiring layer 22 has a roughening layer 30 on the side opposite to the junction surface with the ceramic substrate 14.

[0045] In addition, the roughening layer 30 is formed on the contact surface of the surface wiring layer 22 with the sealing resin (high heat-resistant epoxy resin 3).

[0046] In addition, the ceramic substrate 14 may be a silicon nitride ceramic substrate, for example.

[0047] By setting a roughening layer 30, the high heat-resistant epoxy resin 3 enters the gaps between the roughening layer 30 during potting and cures there. As a result, the anchoring effect (also known as mechanical bonding, anchoring effect, fastener effect) of the hook sinking into it mechanically increases the binding force, thereby preventing peeling caused by thermal stress.

[0048] Example 2

[0049] Reference Figure 6A as well as Figure 6B The semiconductor device and its manufacturing method according to Embodiment 2 of the present invention will be described.

[0050] Figure 6A This is a diagram illustrating a portion of the manufacturing process of the power module 100 in this embodiment. Figure 6B It means to continue Figure 6A A diagram of the manufacturing process.

[0051] In the formation of the insulating circuit board 10, such as Figure 6A As shown, after the back wiring layer 21 and the surface wiring layer 22 are bonded to the ceramic substrate 14, each wiring layer is passed through an etching solution, thereby achieving the desired effect. Figure 6B As shown, a roughening layer 30 is formed on both the back wiring layer 21 and the surface wiring layer 22.

[0052] In the case where only the roughening layer 30 is formed on the surface wiring layer 22, a mask is required for the back wiring layer 21. However, in this embodiment, a mask is not required, and production can be carried out at low cost by reducing labor time.

[0053] In addition, the roughening layer 30 has no effect on the welding, and the bonding strength of the back wiring layer 21 and the metal base 1 by solder 20 is the same as that without the roughening layer 30.

[0054] In addition, when the back wiring layer 21 and the surface wiring layer 22 are copper (Cu), a roughening layer 30 can be formed by performing nickel plating on the surface to roughen it.

[0055] As described above, in the power module 100 of this embodiment, the insulating circuit board 10 has a back wiring layer 21 formed on the back side of the ceramic substrate 14, and the back wiring layer 21 has a roughening layer 30 on the side opposite to the bonding surface of the ceramic substrate 14.

[0056] Example 3

[0057] Reference Figure 7A as well as Figure 7B The semiconductor device according to Embodiment 3 of the present invention will be described.

[0058] Figure 7AThis is a partial cross-sectional view of the power module 100 in this embodiment, which is equivalent to Embodiment 1. Figure 5 The image. Figure 7B yes Figure 7A The roughening layer 30 is viewed in the B-B' direction (top view).

[0059] In Example 1 ( Figure 5 In the previous example, an example was described where a roughening layer 30 was provided on the entire surface of the surface wiring layer 22, including the interface with the IGBT 11. However, in this embodiment ( Figure 7A as well as Figure 7B In Example 1, Figure 5 The difference is that the roughening layer 30 is not provided on the interface between the surface wiring layer 22 and the IGBT 11, but only on the interface between the surface wiring layer 22 and the high heat-resistant epoxy resin 3.

[0060] As in this embodiment, by providing a roughening layer 30 in the area other than the junction of the surface wiring layer 22 and the IGBT 11, similar to Embodiment 1, the binding force between the high heat-resistant epoxy resin 3 and the surface wiring layer 22 can be mechanically improved through the anchoring effect, thus preventing peeling caused by thermal stress.

[0061] In addition to being applicable to power semiconductor chips using silicon substrates, this invention can also be applied to power modules using power semiconductor chips such as silicon carbide (SiC) and gallium nitride (GaN).

[0062] Furthermore, the present invention is not limited to the embodiments described above, and includes various modifications. For example, the embodiments described above are examples that have been explained in detail for the purpose of easily understanding the present invention, and are not necessarily limited to having all the structures described. In addition, a part of the structure of one embodiment can be replaced with the structure of another embodiment, and it is also possible to add the structure of another embodiment to the structure of one embodiment. Furthermore, with respect to a part of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0063] Symbol Explanation

[0064] 1: Metal base, 2: Housing, 3: High heat-resistant epoxy resin, 4: Fin, 10: Insulating circuit board, 11: IGBT, 12: Diode, 13: Lead frame, 14: Ceramic substrate, 20: Solder, 21: Back wiring layer, 22: Surface wiring layer, 23: Solder, 24: Solder, 30: Roughening layer, 100: Power module.

Claims

1. A semiconductor device, characterized in that, have: Power semiconductor chips; An insulating circuit board on which the power semiconductor chip is mounted; and A sealing resin that at least seals the junction of the power semiconductor chip and the insulating circuit board with the power semiconductor chip. The insulating circuit board has a ceramic substrate and a surface wiring layer formed on the surface of the ceramic substrate. The surface wiring layer has a first roughening layer on the side opposite to the bonding surface with the ceramic substrate.

2. The semiconductor device according to claim 1, characterized in that, The first roughening layer is formed on the contact surface between the surface wiring layer and the sealing resin.

3. The semiconductor device according to claim 1, characterized in that, The insulating circuit board has a back wiring layer formed on the back side of the ceramic substrate. The back wiring layer has a second roughening layer on the side opposite to the bonding surface of the ceramic substrate.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The sealing resin is a high heat-resistant epoxy resin.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The ceramic substrate is a silicon nitride ceramic substrate.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first roughening layer is formed by etching the surface of the surface wiring layer.

7. The semiconductor device according to claim 3, characterized in that, The second roughening layer is formed by etching the surface of the back wiring layer.

8. The semiconductor device according to any one of claims 1 to 3, characterized in that, The surface wiring layer is formed of copper. The first roughening layer is a roughened nickel plating layer formed on the surface wiring layer.

9. The semiconductor device according to claim 3, characterized in that, The back wiring layer is formed of copper. The second roughening layer is a roughened nickel plating layer formed on the back wiring layer.

10. The semiconductor device according to claim 1, characterized in that, The first roughening layer is formed in the area outside the junction of the surface wiring layer and the power semiconductor chip.

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