Preparation method of array substrate, array substrate and electronic equipment

Abstract

The invention provides a preparation method of an array substrate, the array substrate and electronic equipment. The preparation method comprises the following steps: sequentially forming a grid electrode and a grid electrode insulating layer on the surface of a substrate; forming an active layer and a source-drain electrode on the surface of the gate insulating layer; forming a protection structure on the surface of the thin film transistor, performing etching treatment on the protection structure to form a first through hole of the protection structure, and performing etching treatment on the gate insulation layer to form a second through hole of the gate insulation layer; forming a pixel electrode on the surface of the protection structure; the pixel electrode is electrically connected with the source-drain electrode through the first through hole and is electrically connected with the grid electrode through the first through hole and the second through hole; forming a cofferdam structure on the surface of the pixel region to obtain an array substrate; the cofferdam structure is arranged around the pixel area, and the projection of the cofferdam structure in the vertical direction can cover the first through hole and the second through hole, so that the convenience of establishing the electric connection between the grid electrode and the source drain electrode of the thin film transistor in the array substrate is improved, and the convenience of preparing the array substrate is improved.

Description

Fabrication method of array substrate, array substrate and electronic device Technical Field

[0001] This application relates to the field of display technology, and in particular to a method for fabricating an array substrate, the array substrate, and an electronic device. Background Technology

[0002] Electronic devices can include reflective paper-like display devices, liquid crystal display devices, and so on. Reflective paper-like display devices can include micro electric-cavity display (MED) devices, electronic paper (EPD) devices, and so on.

[0003] For example, an electronic device may have an array substrate. When displaying content, the electronic device needs to simultaneously drive the gate and source / drain terminals of the thin-film transistors (TFTs) in the array substrate via a display driver chip. At this time, an electrical connection needs to be established between the gate and source / drain terminals of the TFTs. However, in related technologies, establishing the electrical connection between the gate and source / drain terminals of the TFTs in the array substrate can be difficult, leading to complications in the fabrication process of the array substrate. Summary of the Invention

[0004] This application provides a method for fabricating an array substrate, an array substrate, and an electronic device, aiming to improve the ease of establishing the electrical connection between the gate and source / drain electrodes of the thin-film transistor in the array substrate, while also improving the ease of fabricating the array substrate.

[0005] In a first aspect, this application provides a method for fabricating an array substrate, the method comprising: sequentially forming a gate and a gate insulating layer on the surface of a substrate; forming an active layer and a source / drain electrode on the surface of the gate insulating layer facing away from the substrate to obtain a thin-film transistor; forming a protective structure on the surface of the thin-film transistor facing away from the substrate, and etching the protective structure to form a first via of the protective structure, and etching the gate insulating layer to form a second via of the gate insulating layer; forming a pixel electrode on the surface of the protective structure facing away from the substrate to obtain a pixel region; the pixel electrode being electrically connected to the source / drain electrode through the first via, and electrically connected to the gate through the first via and the second via; forming a dam structure on the surface of the pixel region facing away from the substrate to obtain an array substrate; the dam structure being disposed around the pixel region, and the projection of the dam structure in the vertical direction being able to cover the first via and the second via.

[0006] Secondly, this application provides an array substrate, which is prepared according to the above-described array substrate preparation method.

[0007] Thirdly, this application provides an electronic device, which includes the array substrate as described above.

[0008] The array substrate prepared in this application may include a pixel region, which includes a thin-film transistor, a protective structure, and a pixel electrode sequentially disposed on the substrate. The thin-film transistor includes a gate, a gate insulating layer, an active layer, and source / drain electrodes. The protective structure has a first via, and the gate insulating layer has a second via. Therefore, the pixel electrode can be electrically connected to the source / drain electrodes through the first via, and to the gate through both the first and second vias. This allows the gate and source / drain electrodes to be electrically connected via the pixel electrode, thus improving the ease of establishing the electrical connection between the gate and source / drain electrodes.

[0009] Furthermore, in the fabrication of the array substrate, this application allows for the initial formation of thin-film transistors and protective structures on the substrate, followed by etching of the protective structure and the gate insulating layer to form a first via in the protective structure and a second via in the gate insulating layer. This eliminates the need for additional etching of the gate insulating layer during the fabrication of the active layer and source / drain electrodes of the thin-film transistors, thus avoiding an additional increase in the number of photolithography steps in the array substrate fabrication process. Therefore, the fabrication process of the array substrate in this application significantly improves the ease of array substrate fabrication.

[0010] Correspondingly, if the array substrate includes a dam structure corresponding to the pixel area, the dam structure is arranged around the pixel area, and the projection of the dam structure in the vertical direction can cover the first through hole and the second through hole, the arrangement of the first through hole and the second through hole will not adversely affect the display performance of the pixel area, which is beneficial to improving the display performance of the pixel area included in the array substrate.

[0011] Therefore, the array substrate fabrication process in this application is beneficial to improving the ease of establishing electrical connections between the gate and the source / drain, while also improving the ease of fabricating the array substrate and enhancing the display performance of the pixel areas included in the array substrate. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 is a cross-sectional view of a through-hole in an array substrate related to the related technology; Figure 2 is a cross-sectional view of a GI through-hole in an array substrate related to the related technology; Figure 3 is another structural schematic diagram of an array substrate related to the related technology; Figure 4 is another structural schematic diagram of an array substrate related to the related technology; Figure 5 is a cross-sectional view of a through-hole in an array substrate provided in an embodiment of this application; Figure 6 is a structural schematic diagram of an array substrate related to an embodiment of this application; Figure 7 is a flowchart of a method for fabricating an array substrate provided in an embodiment of this application; Figure 8 is a structural schematic diagram of an electronic device provided in an embodiment of this application.

[0014] Explanation of reference numerals in the attached figures: 10, electronic device; 100, array substrate; 110, substrate; 120, pixel region; 121, thin-film transistor; 1211, gate; 1212, gate insulating layer; 1213, source / drain electrode; 122, protective structure; 1221, first insulating layer; 1222, second insulating layer; 1223, third insulating layer; 123, pixel electrode; 124, first via; 1241, first sub-via; 1242, second sub-via; 1243, third sub-via; 125, second via; 130, dike structure. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0016] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0017] As shown in Figure 1, the film layer architecture of the pixel region in the array substrate of electronic devices in related technologies is usually as follows: Film layer 1: Gate Electrode (GE) metal layer of Thin-Film Transistor (TFT).

[0018] Film 2: The active layer of the thin-film transistor.

[0019] Film 3: The gate insulator (GI) layer of the thin-film transistor, with GI vias. The GI vias allow for electrical connection between the gate and the source / drain, thereby enabling the switching between gate and source signals and meeting the requirements of metal wiring.

[0020] Film 4: Source-Drain (SD) metal layer of thin-film transistor.

[0021] Film layer 5: JAS insulating layer and Pas insulating layer, realizing JAS opening.

[0022] Film layer 6: Common Electrode (COM) layer, forming the common electrode.

[0023] Film layer 7: PV insulating layer, enabling PV openings.

[0024] Film layer 8: Reflective layer, forming pixel electrode.

[0025] Membrane 9: Cofferdam.

[0026] In related technologies, each film layer structure in the pixel region of the array substrate corresponds to a photolithography (mask) process.

[0027] As shown in Figure 1, in related technologies, the gate metal layer of the thin-film transistor in the array substrate controls the switching of the thin-film transistor. Data lines in the array substrate transmit the required signals to the source of the source-drain metal layer within the pixel region. The source connects the source signal to the pixel electrode through PV and JAS vias. Furthermore, as shown in Figure 2, the source needs to establish a direct electrical connection with the gate through a GI via formed in the gate insulating layer.

[0028] As shown in Figures 3 and 4, in related technologies, when an electronic device displays corresponding content, it needs to simultaneously drive the gate and source / drain terminals of the thin-film transistors in the array substrate through a display driver chip to simultaneously drive the gate signal and the source signal. At this time, the gate signal and the source signal are connected to the pixel area via fanout lines. The gate signal is transmitted through the gate metal layer, and the source signal is transmitted through the source / drain metal layer. If the gate metal layer is directly electrically connected to the display driver chip, it can easily lead to a widening of the bezels on both sides of the pixel area. Therefore, in related technologies, data lines are typically connected to the display driver chip within the pixel area, resulting in the existence of cross-line issues on the same layer. This necessitates that the data lines cross through the source / drain metal layers, and that electrical connections between the gate metal layer and the source / drain metal layer be established through vias between the gate metal layer and the source / drain metal layer. The vias between the gate metal layer and the source / drain metal layer include vias (GI holes) opened on the gate insulating layer.

[0029] However, based on the consideration of using GI vias to achieve electrical connection between the gate metal layer and the source / drain metal layers, related technologies require the fabrication of the active layer of the thin-film transistor (TFT) first, and then the GI vias to be formed on the gate insulating layer of the TFT during the array substrate fabrication process. Correspondingly, the source / drain electrodes can only be formed on the active layer of the TFT after the GI vias are formed. This can negatively impact the ease of establishing electrical connection between the gate metal layer and the source / drain metal layers of the array substrate, as well as the ease of fabrication of the gate metal layer and the source / drain metal layers, thus complicating the array substrate fabrication process and resulting in poor ease of array substrate fabrication.

[0030] Therefore, it is imperative to improve the array substrate to enhance the ease of establishing electrical connections between the gate and source / drain electrodes of the thin-film transistors in the array substrate, and to simplify the fabrication process of the array substrate, thereby improving the ease of fabrication.

[0031] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0032] Please refer to Figures 5 and 6. Figure 5 is a cross-sectional view of the through-hole of the array substrate 100 provided in an embodiment of this application, and Figure 6 is a structural schematic diagram of the array substrate 100 involved in an embodiment of this application.

[0033] As shown in Figures 5 and 6, the array substrate 100 is disposed on the substrate 110. The array substrate 100 includes a pixel region 120 and a dam structure 130 corresponding to the pixel region 120; in the vertical direction, the pixel region 120 is located between the substrate 110 and the dam structure 130, and the dam structure 130 is disposed around the pixel region 120.

[0034] The pixel region 120 includes a thin-film transistor 121, a protective structure 122, and a pixel electrode 123 sequentially disposed on the substrate 110.

[0035] The thin-film transistor 121 includes a gate 1211, a gate insulating layer 1212, an active layer, and a source drain 1213; the gate 1211 is located between the substrate 110 and the gate insulating layer 1212, the active layer is located between the gate insulating layer 1212 and the source drain 1213, and the source drain 1213 is located between the active layer and the protective structure 122.

[0036] The protective structure 122 is provided with a first through hole 124, and the gate insulating layer 1212 is provided with a second through hole 125; the projection of the cofferdam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0037] The pixel electrode 123 is electrically connected to the source and drain electrodes 1213 via the first via 124, and is electrically connected to the gate electrode 1211 via the first via 124 and the second via 125.

[0038] For example, the array substrate 100 may include a plurality of pixel regions 120 and a corresponding weir structure 130 for each of the pixel regions 120. For instance, a plurality of scan lines (not shown) and a plurality of data lines (not shown) are disposed on the substrate 110. The plurality of scan lines and the plurality of data lines intersect to define the plurality of pixel regions 120. Each pixel region 120 may have a corresponding weir structure 130. The scan lines may also be referred to as gate signal lines, and the data lines may also be referred to as source signal lines.

[0039] For example, based on the structural configuration of the array substrate 100, during the fabrication of the array substrate 100, a gate 1211, a gate insulating layer 1212, an active layer, and a source / drain electrode 1213 can be sequentially formed on the substrate 110 to form a thin-film transistor 121 on the substrate 110. Correspondingly, a protective structure 122 and a pixel electrode 123 can be sequentially formed on the substrate 110 where the thin-film transistor 121 is formed to form a pixel region 120 of the array substrate 100. After forming the protective structure 122, a first via 124 can be formed on the protective structure 122, and a second via 125 can be formed on the gate insulating layer 1212. The first via 124 allows the pixel electrode 123 to be electrically connected to the source / drain electrode 1213, and the first via 124 and the second via 125 allow the pixel electrode 123 to be electrically connected to the gate 1211. Based on the structural configuration of the array substrate 100, it is possible to eliminate the need for additional etching of the gate insulating layer 1212 during the fabrication of the active layer and source / drain electrodes 1213 of the thin-film transistor 121, thereby reducing the number of photolithography steps in the fabrication of the array substrate 100 and improving the ease of fabrication of the array substrate 100.

[0040] For example, when the dike structure 130 is arranged around the pixel region 120, the dike structure 130 can cover the non-opening area of ​​the pixel region 120 in the vertical direction, but will not cover the opening area of ​​the pixel region 120 in the vertical direction. The dike structure 130 may include a photowall (PW). A photowall can also be called a PW dike. Of course, it is not limited to this, and no limitation is made here. The dike structure 130 can serve as a physical separator between different pixel regions 120 to prevent crosstalk between pixel regions 120, ensure uniform brightness and color of pixel regions 120, and improve contrast and yield. For example, for a reflective paper-like display device, the dike structure 130 can be used to limit the flow range of plasma in the pixel region 120 to prevent uneven plasma between different pixel regions 120, thereby preventing crosstalk between pixel regions 120. For a liquid crystal display device, the dike structure 130 can be used to limit the flow range of liquid crystal in the pixel region 120, thereby preventing crosstalk between pixel regions 120. Of course, this is not the only limitation, and no restrictions are imposed here. Accordingly, when the dike structure 130 surrounds the pixel region 120, and the vertical projection of the dike structure 130 can cover the first through hole 124 and the second through hole 125, the situation of inconsistent color display in the opening area of ​​the pixel region 120 can be avoided, thereby improving the display performance of the pixel region 120 included in the array substrate 100. For example, since the first through hole 124 and the second through hole 125 can be covered by the dike structure 130 in the vertical direction, gray spots will not be formed at the first through hole 124 and the second through hole 125, and thus the arrangement of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the opening area of ​​the pixel region 120.

[0041] In an array substrate 100 including a pixel region 120, the pixel region 120 includes a thin-film transistor 121, a protective structure 122, and a pixel electrode 123 sequentially disposed on a substrate 110. The thin-film transistor 121 includes a gate 1211, a gate insulating layer 1212, an active layer, and a source / drain electrode 1213. The protective structure 122 is provided with a first via 124, and the gate insulating layer 1212 is provided with a second via 125. The pixel electrode 123 can be electrically connected to the source / drain electrode 1213 through the first via 124, and electrically connected to the gate 1211 through the first via 124 and the second via 125. This allows the gate 1211 and the source / drain electrode 1213 to be electrically connected through the pixel electrode 123, which is beneficial to improving the ease of establishing the electrical connection between the gate 1211 and the source / drain electrode 1213 in the array substrate 100.

[0042] Furthermore, based on the structural configuration of the array substrate 100 in this application, when fabricating the array substrate 100, the thin-film transistor 121 and the protective structure 122 can be formed on the substrate 110 first, and then the protective structure 122 and the gate insulating layer 1212 can be etched to form the first via 124 of the protective structure 122 and the second via 125 of the gate insulating layer 1212. This eliminates the need for additional etching of the gate insulating layer 1212 during the fabrication of the active layer and source / drain electrodes 1213 of the thin-film transistor 121, thus reducing the number of photolithography steps in the fabrication process of the array substrate 100. Compared to the photolithography steps required in related technologies, the fabrication process of the array substrate 100 in this application effectively combines the photolithography steps required for fabricating layers 2 to 4 in related technologies into one or two photolithography steps, thereby reducing at least one photolithography step in the fabrication process of the array substrate 100, which simplifies the fabrication process of the array substrate 100. Based on this, the process for preparing the array substrate 100 in this application can improve the ease of preparing the array substrate 100.

[0043] Correspondingly, when the array substrate 100 includes a dam structure 130 corresponding to the pixel region 120, the dam structure 130 is disposed around the pixel region 120, and the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, it can be ensured that the first through hole 124 and the second through hole 125 are disposed in the non-opening area of ​​the pixel region 120, rather than in the opening area of ​​the pixel region 120. Therefore, the disposal of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel region 120, thereby improving the display performance of the pixel region 120 included in the array substrate 100.

[0044] In some embodiments, the cofferdam structure 130 includes a plurality of cofferdam substructures; the plurality of cofferdam substructures are connected end to end in sequence, and the projection of at least one cofferdam substructure in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0045] The cofferdam structure 130 may include multiple cofferdam substructures. Each cofferdam substructure can be connected to two other cofferdam substructures, thereby connecting multiple cofferdam substructures end to end in sequence to form a closed cofferdam structure 130. As shown in Figure 6, the cofferdam structure 130 may include four cofferdam substructures, which are connected end to end in sequence. Of course, the number of cofferdam substructures included in the cofferdam structure 130 is not limited to this, and is not restricted here.

[0046] When setting up the cofferdam structure 130, the cofferdam substructures can be configured such that at least one cofferdam substructure's vertical projection covers the first through-hole 124 and the second through-hole 125. For example, a cofferdam substructure can have two connecting portions and a central region between the two connecting portions. The connecting portions of the cofferdam substructure can be used to connect with the connecting portions of another cofferdam substructure, thereby allowing multiple cofferdam substructures to be connected end-to-end sequentially. In the vertical direction, if the first through-hole 124 and the second through-hole 125 can be covered by the central region of a cofferdam substructure, then there is one cofferdam substructure in the cofferdam structure 130 whose vertical projection covers the first through-hole 124 and the second through-hole 125. In the vertical direction, if the first through-hole 124 and the second through-hole 125 can be covered by one of the connecting portions of a cofferdam substructure, then there are two cofferdam substructures in the cofferdam structure 130 whose vertical projections cover the first through-hole 124 and the second through-hole 125.

[0047] Based on this, it can be ensured that the first through hole 124 and the second through hole 125 are located in the non-opening area of ​​the pixel area 120, rather than in the opening area of ​​the pixel area 120. Therefore, the setting of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel area 120, thereby helping to improve the display performance of the pixel area 120 included in the array substrate 100.

[0048] In some embodiments, the vertical projection of the connection between at least two cofferdam substructures can cover the first through hole 124 and the second through hole 125.

[0049] For example, since the cofferdam structure 130 includes multiple cofferdam substructures connected end-to-end in sequence, a connecting portion of each cofferdam substructure can serve as a connecting portion between at least two cofferdam substructures. In the vertical direction, if the first through-hole 124 and the second through-hole 125 can be covered by one of the connecting portions of a certain cofferdam substructure, then that connecting portion can serve as a connecting portion between at least two cofferdam substructures, such that the projection of the connecting portion between at least two cofferdam substructures in the vertical direction can cover the first through-hole 124 and the second through-hole 125.

[0050] For example, as shown in FIG6, the shape, size, etc. of the connection between at least two cofferdam substructures can be designed so that the projection of the connection between at least two cofferdam substructures in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0051] Based on this, when the vertical projection of the connection between at least two cofferdam substructures can cover the first through hole 124 and the second through hole 125, it can be ensured that the first through hole 124 and the second through hole 125 are located in the non-opening area of ​​the pixel area 120, rather than in the opening area of ​​the pixel area 120. Therefore, the setting of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel area 120, thereby helping to improve the display performance of the pixel area 120 included in the array substrate 100.

[0052] In some implementations, the cofferdam structure 130 has a vertical dimension greater than or equal to 1 micrometer.

[0053] For example, the vertical dimensions of the cofferdam structure 130 include one of 1 micrometer, 1.2 micrometer, 1.5 micrometer, 2 micrometer, 2.6 micrometer, etc. Of course, it is not limited to this, and no limitation is made here.

[0054] Since the dike structure 130 has a vertical dimension greater than or equal to 1 micrometer, it can serve as a physical separator between different pixel regions 120 to prevent crosstalk between them, ensuring uniform brightness and color, and improving contrast and yield. Therefore, the dike structure 130 is beneficial for improving the display performance of the pixel regions 120 included in the array substrate 100.

[0055] In some implementations, the cofferdam structure 130 is made of insulating material.

[0056] For example, insulating materials are used to indicate materials with poor conductivity and high resistivity.

[0057] When the cofferdam structure 130 is arranged around the pixel region 120, and the projection of the cofferdam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, the cofferdam structure 130 can use the insulating properties of the insulating material to achieve electric field isolation between different pixel regions 120, so as to prevent electrical crosstalk between different pixel regions 120, thereby improving the display performance of the pixel region 120 included in the array substrate 100.

[0058] In some embodiments, the insulating material includes at least one of silicon dioxide and silicon nitride.

[0059] For example, the insulating material used in the cofferdam structure 130 may include one of silicon dioxide and silicon nitride, or it may include a multilayer stacked structure of silicon dioxide and silicon nitride.

[0060] When the insulating material used in the cofferdam structure 130 includes at least one of silicon dioxide and silicon nitride, the cofferdam structure 130 can utilize the insulating properties of at least one of silicon dioxide and silicon nitride to achieve electric field isolation between different pixel regions 120, so as to prevent electrical crosstalk between different pixel regions 120, thereby improving the display performance of the pixel regions 120 included in the array substrate 100.

[0061] In some embodiments, the protective structure 122 includes a first insulating layer 1221, a second insulating layer 1222, and a third insulating layer 1223; in the vertical direction, the first insulating layer 1221 is located between the source / drain electrode 1213 and the second insulating layer 1222, and the third insulating layer 1223 is located between the second insulating layer 1222 and the pixel electrode 123.

[0062] The first through hole 124 includes a first sub-through hole 1241, a second sub-through hole 1242, and a third sub-through hole 1243; the first insulating layer 1221 is provided with the first sub-through hole 1241, the second insulating layer 1222 is provided with the second sub-through hole 1242, and the third insulating layer 1223 is provided with the third sub-through hole 1243.

[0063] The pixel electrode 123 is electrically connected to the source and drain electrodes 1213 through the third sub-via 1243, the second sub-via 1242 and the first sub-via 1241, and is electrically connected to the gate electrode 1211 through the third sub-via 1243, the second sub-via 1242, the first sub-via 1241 and the second through-via 125.

[0064] As shown in Figure 5, the protective structure 122 may include a first insulating layer 1221, a second insulating layer 1222, and a third insulating layer 1223. For example, the first insulating layer 1221 may include a first PV insulating layer (referred to as PV1 layer). The second insulating layer 1222 may include a JAS insulating layer (referred to as JAS layer). The third insulating layer 1223 may include a second PV insulating layer (also referred to as P... V (2 layers). For example, a first sub-via 1241 is provided on the PV1 layer, a second sub-via 1242 is provided on the JAS layer, and a third sub-via 1243 is provided on the PV2 layer. Of course, it is not limited to this, and no limitation is made here.

[0065] The pixel electrode 123 can be electrically connected to the source / drain electrode 1213 through the third sub-via 1243, the second sub-via 1242, and the first sub-via 1241, and electrically connected to the gate electrode 1211 through the third sub-via 1243, the second sub-via 1242, the first sub-via 1241, and the second through-via 125. This allows the gate electrode 1211 and the source / drain electrode 1213 to be electrically connected through the pixel electrode 123, which helps to improve the ease of establishing the electrical connection between the gate electrode 1211 and the source / drain electrode 1213 in the array substrate 100.

[0066] Correspondingly, the projection of the cofferdam structure 130 in the vertical direction can cover the first sub-through hole 1241, the second sub-through hole 1242 and the third sub-through hole 1243. Therefore, the arrangement of the first sub-through hole 1241, the second sub-through hole 1242 and the third sub-through hole 1243 will not adversely affect the display performance of the opening area of ​​the pixel area 120 included in the array substrate 100, thereby helping to improve the display performance of the pixel area 120 included in the array substrate 100.

[0067] In some embodiments, the pixel region 120 also includes a common electrode located between the second insulating layer 1222 and the third insulating layer 1223.

[0068] When a common electrode is provided in the pixel region 120 and is located between the second insulating layer 1222 and the third insulating layer 1223, the third insulating layer 1223 can physically separate the common electrode and the pixel electrode 123, thereby forming a storage capacitor between them. The storage capacitor formed between the common electrode and the pixel electrode 123 can improve the voltage stability of the pixel electrode 123, thus contributing to improved stability of the display performance of the pixel region 120 in the array substrate 100. Correspondingly, the third insulating layer 1223 can be used to block impurities, protect the common electrode, and serve as the insulating medium in the storage capacitor.

[0069] In some embodiments, the projection of the third insulating layer 1223 in the vertical direction can cover the common electrode.

[0070] For example, when the vertical projection of the third insulating layer 1223 covers the common electrode, the third insulating layer 1223 can act as a physical separator, separating the common electrode from the pixel electrode 123 to prevent electrical connection between the common electrode and the pixel electrode 123, thus allowing a storage capacitor to be formed between the common electrode and the pixel electrode 123. The storage capacitor formed between the common electrode and the pixel electrode 123 can improve the voltage stability on the pixel electrode 123, thereby improving the stability of the display performance of the pixel region 120 in the array substrate 100.

[0071] Please refer to Figure 7, which is a schematic flowchart of a method for fabricating an array substrate 100 according to an embodiment of this application.

[0072] As shown in Figure 7, the method for fabricating the array substrate 100 includes steps S101 to S105.

[0073] S101, A gate 1211 and a gate insulating layer 1212 are sequentially formed on the surface of the substrate 110.

[0074] For example, the substrate 110 is subjected to one or more of the following processes in sequence: cleaning, physical film formation, resist coating, exposure, development, wet etching, stripping, resist removal, etc., to form a gate 1211 on the substrate 110. The gate 1211 can be used as a scan electrode, and can then be used to control the conduction and disconnection of the thin film transistor 121.

[0075] For example, when a gate 1211 is formed on the surface of a substrate 110, the substrate 110 on which the gate 1211 is formed may be subjected to one or more of the following processes: cleaning, chemical film formation, etc., so as to form a gate insulating layer 1212 on the surface of the gate 1211 facing away from the substrate 110.

[0076] S102, An active layer and source / drain electrodes 1213 are formed on the surface of the gate insulating layer 1212 on the side opposite to the substrate 110 to obtain a thin film transistor 121.

[0077] As shown in Figure 5, the thin-film transistor 121 may include a gate 1211, a gate insulating layer 1212, an active layer (not shown), and a source / drain electrode 1213. In the thin-film transistor 121, the gate 1211 is located between the substrate 110 and the gate insulating layer 1212, and the active layer is located between the gate insulating layer 1212 and the source / drain electrode 1213. The active layer can be equivalent to a switch in the array substrate 100 circuit. The source / drain electrode 1213 can be used as a data electrode, thereby providing a signal to charge the pixel region 120.

[0078] For example, an active layer and source / drain electrodes 1213 can be sequentially formed on the surface of the gate insulating layer 1212 facing away from the substrate 110. For instance, when the gate insulating layer 1212 is formed on the surface of the gate 1211 facing away from the substrate 110, one or more of the following processes can be performed on the substrate 110 where the gate insulating layer 1212 is formed: cleaning, chemical film deposition, resist coating, exposure, development, dry etching, stripping, resist removal, etc., so as to form an active layer on the surface of the gate insulating layer 1212 facing away from the substrate 110.

[0079] For example, when an active layer is formed on the surface of the gate insulating layer 1212 away from the substrate 110, one or more of the following processes can be performed on the substrate 110 where the active layer is formed: cleaning, physical film formation, coating, exposure, development, wet etching, dry etching, stripping, resist removal, etc., so as to form source and drain electrodes 1213 on the surface of the active layer away from the substrate 110.

[0080] For example, an active layer and source / drain electrodes 1213 may be formed simultaneously on the surface of the gate insulating layer 1212 facing away from the substrate 110.

[0081] In some embodiments, an active layer and source / drain electrodes 1213 are formed on the surface of the gate insulating layer 1212 facing away from the substrate 110, based on a halftone mask.

[0082] For example, the diffraction principle of ultraviolet light by a semi-transparent film or patterned slits on a halftone mask can be used to reduce local ultraviolet transmittance, thereby controlling the exposure level of the photoresist coated on the side of the gate insulating layer 1212 facing away from the substrate 110. This allows the source / drain patterns and silicon island patterns to be formed in a single photolithography process. The source / drain patterns are used to indicate the metal patterns of the source / drain electrodes 1213. The silicon island patterns are used to indicate the metal patterns of the active layer. Based on this, when the active layer and source / drain electrodes 1213 are formed on the side of the gate insulating layer 1212 facing away from the substrate 110 using a halftone mask, the active layer and source / drain electrodes 1213 can be formed in a single photolithography process, which simplifies the fabrication process of the thin-film transistor 121 in the array substrate 100.

[0083] In the fabrication of thin-film transistors (TFTs) on an array substrate, related technologies require first forming an active layer on the surface of the gate insulating layer facing away from the substrate, and then creating GI vias on the gate insulating layer. Consequently, these technologies require creating the GI vias before forming the source and drain electrodes on the surface of the active layer facing away from the substrate. Therefore, these technologies cannot skip the photolithography steps required to create the GI vias to fabricate the active layer and source / drain electrodes, which complicates the fabrication process of the TFTs on the array substrate.

[0084] In this application, during the formation of the active layer and source / drain electrode 1213 on the surface of the gate insulating layer 1212 facing away from the substrate 110, it is not necessary to open a GI via on the gate insulating layer 1212 of the thin-film transistor 121 during the fabrication of the active layer and source / drain electrode 1213 of the thin-film transistor 121. Therefore, the active layer and source / drain electrode 1213 can be formed sequentially on the surface of the gate insulating layer 1212 facing away from the substrate 110, or simultaneously on the surface of the gate insulating layer 1212 facing away from the substrate 110. This effectively skips the photolithography process required for opening the GI via, thus reducing at least one photolithography process (also known as a mask process) in the fabrication process of the array substrate 100, thereby simplifying the fabrication process of the thin-film transistor 121 in the array substrate 100. This simplification of the fabrication process of the thin-film transistor 121 in the array substrate 100 further simplifies the overall fabrication process of the array substrate 100.

[0085] S103. A protective structure 122 is formed on the surface of the thin film transistor 121 away from the substrate 110, and the protective structure 122 is etched to form a first through hole 124 of the protective structure 122, and the gate insulating layer 1212 is etched to form a second through hole 125 of the gate insulating layer 1212.

[0086] For example, when a thin film transistor 121 is formed on a substrate 110, the substrate 110 on which the thin film transistor 121 is formed may be subjected to one or more of the following processes: cleaning, chemical film formation, coating, exposure, development, annealing, dry etching, stripping or resist removal, etc., to form a protective structure 122 on the surface of the thin film transistor 121 away from the substrate 110.

[0087] The protective structure 122 serves to protect the array substrate 100. For example, the protective structure 122 can utilize its insulating properties to protect the thin-film transistor 121, thereby reducing the parasitic capacitance between the source / drain electrodes 1213 of the thin-film transistor 121 and the pixel electrodes 123 of the array substrate 100. For example, when a common electrode is provided in the array substrate 100, the protective structure 122 can utilize its insulating properties to block impurities, thereby protecting the common electrode.

[0088] For example, when a protective structure 122 is formed on the substrate 110, the protective structure 122 can be etched to form a first via 124. When the first via 124 is formed, the gate insulating layer 1212 can be further etched to form a second via 125. The first via 124 on the protective structure 122 and the second via 125 on the gate insulating layer 1212 allow for subsequent electrical connections between the pixel electrode 123 in the array substrate 100 and the source / drain electrode 1213 and gate electrode 1211 of the thin-film transistor 121 in the array substrate 100, respectively. This facilitates the subsequent establishment of electrical connections between the source / drain electrode 1213 and the gate electrode 1211 of the thin-film transistor 121 in the array substrate 100, thereby improving the ease of establishing electrical connections between the gate electrode 1211 and the source / drain electrode 1213 in the array substrate 100.

[0089] Accordingly, based on the formation of the protective structure 122 on the substrate 110, the protective structure 122 is then etched to form the first via 124 of the protective structure 122, and the gate insulating layer 1212 is etched to form the second via 125 of the gate insulating layer 1212. This eliminates the need for an additional step of creating the second via 125 in the gate insulating layer 1212 during the fabrication of the active layer and source / drain electrodes 1213 of the thin-film transistor 121. Essentially, the creation of the second via 125 is postponed, allowing the active layer and source / drain electrodes 1213 of the thin-film transistor 121 to be fabricated in a single photolithography step. Compared to the photolithography steps required in related technologies, the fabrication process of the array substrate 100 in this application combines the photolithography steps required for fabricating layers 2 to 4 in related technologies into one or two photolithography steps, thereby reducing at least one photolithography step in the fabrication process of the array substrate 100, which simplifies the fabrication process of the array substrate 100. Furthermore, the process of fabricating the array substrate 100 based on this application can achieve the opening of the first through hole 124 of the protective structure 122 and the second through hole 125 of the gate insulating layer 1212 with as few photolithography steps as possible, which helps to simplify the opening process of the first through hole 124 of the protective structure 122 and the second through hole 125 of the gate insulating layer 1212 in the array substrate 100, and thus helps to simplify the fabrication process of the array substrate 100.

[0090] S104. A pixel electrode 123 is formed on the surface of the protective structure 122 away from the substrate 110 to obtain a pixel region 120. The pixel electrode 123 is electrically connected to the source and drain electrodes 1213 through the first through hole 124, and electrically connected to the gate electrode 1211 through the first through hole 124 and the second through hole 125.

[0091] For example, when a protective structure 122 is formed on a substrate 110, the substrate 110 on which the protective structure 122 is formed can be subjected to one or more of the following processes: cleaning, physical film deposition, resist coating, exposure, development, wet etching, stripping, annealing, etc., to form a pixel electrode 123 on the surface of the protective structure 122 facing away from the substrate 110, thereby forming a pixel region 120. For example, a reflective layer can be formed on the surface of the protective structure 122 facing away from the substrate 110, and the pixel electrode 123 is formed on the reflective layer. The pixel electrode 123 disposed on the array substrate 100 can form a perpendicular electric field with the common electrode, reflect sunlight, and thus reduce power consumption.

[0092] In an array substrate 100 including a pixel region 120, the pixel region 120 includes a thin-film transistor 121, a protective structure 122, and a pixel electrode 123 sequentially disposed on a substrate 110. The thin-film transistor 121 includes a gate 1211, a gate insulating layer 1212, an active layer, and a source / drain electrode 1213. The protective structure 122 is provided with a first via 124, and the gate insulating layer 1212 is provided with a second via 125. The pixel electrode 123 can be electrically connected to the source / drain electrode 1213 through the first via 124, and electrically connected to the gate 1211 through the first via 124 and the second via 125. This allows the gate 1211 and the source / drain electrode 1213 to be electrically connected through the pixel electrode 123, which is beneficial to improving the ease of establishing the electrical connection between the gate 1211 and the source / drain electrode 1213 in the array substrate 100.

[0093] S105, a dam structure 130 is formed on the surface of the pixel region 120 away from the substrate 110 to obtain the array substrate 100; the dam structure 130 is disposed around the pixel region 120, and the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0094] For example, when a pixel region 120 is formed on a substrate 110, the substrate 110 on which the pixel region 120 is formed can be subjected to one or more of the following processes: cleaning, coating, pre-baking, exposure, development, post-baking, etc., to form a dam structure 130 on the surface of the pixel region 120 facing away from the substrate 110, thereby obtaining an array substrate 100. The dam structure 130 is arranged around the pixel region 120 so that the dam structure 130 can enclose the area around the pixel region 120, thereby physically separating different pixel regions 120, preventing crosstalk between pixel regions 120, ensuring uniform brightness and color of the pixel region 120, and improving contrast and yield.

[0095] Accordingly, when the dam structure 130 surrounds the pixel region 120, and the vertical projection of the dam structure 130 covers the first through-hole 124 and the second through-hole 125, inconsistent color display in the opening area of ​​the pixel region 120 can be avoided, thereby improving the display performance of the pixel region 120 included in the array substrate 100. For example, since the first through-hole 124 and the second through-hole 125 can be covered by the dam structure 130 in the vertical direction, gray spots will not be formed at the first through-hole 124 and the second through-hole 125, and thus the arrangement of the first through-hole 124 and the second through-hole 125 will not adversely affect the display performance of the opening area of ​​the pixel region 120.

[0096] In the case that the array substrate 100 includes a dam structure 130 corresponding to the pixel region 120, the dam structure 130 is arranged around the pixel region 120, and the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, it can be ensured that the first through hole 124 and the second through hole 125 are arranged in the non-opening area of ​​the pixel region 120, rather than in the opening area of ​​the pixel region 120. Therefore, the arrangement of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel region 120, thereby helping to improve the display performance of the pixel region 120 included in the array substrate 100.

[0097] In some embodiments, the protective structure 122 includes a first insulating layer 1221, a second insulating layer 1222, and a third insulating layer 1223.

[0098] A first insulating layer 1221 is formed on the surface of the thin-film transistor 121 facing away from the substrate 110; a second insulating layer 1222 is formed on the surface of the first insulating layer 1221 facing away from the substrate 110, and the second insulating layer 1222 is etched to form a second sub-via 1242; a third insulating layer 1223 is formed on the surface of the second insulating layer 1222 facing away from the substrate 110, and the first insulating layer 1221, the third insulating layer 1223, and the gate insulating layer 1212 are etched to form the first insulating layer 1222. The first sub-via 1241 of 21, the third sub-via 1243 of the third insulating layer 1223, and the second via 125 of the gate insulating layer 1212; the first via 124 includes the first sub-via 1241, the second sub-via 1242, and the third sub-via 1243; the pixel electrode 123 is electrically connected to the source and drain electrodes 1213 through the third sub-via 1243, the second sub-via 1242, and the first sub-via 1241, and is electrically connected to the gate 1211 through the third sub-via 1243, the second sub-via 1242, the first sub-via 1241, and the second via 125.

[0099] For example, when a thin-film transistor 121 is formed on a substrate 110, the substrate 110 on which the thin-film transistor 121 is formed may be subjected to one or more of the following processes: cleaning, chemical deposition, resist coating, exposure, development, annealing, etc., to form a first insulating layer 1221 on the surface of the thin-film transistor 121 facing away from the substrate 110, and a second insulating layer 1222 on the surface of the first insulating layer 1221 facing away from the substrate 110. When forming the second insulating layer 1222, the second insulating layer 1222 may be etched to form a second sub-via 1242 on the second insulating layer 1222.

[0100] When a second insulating layer 1222 is formed on a substrate 110, one or more of the following processes can be performed on the substrate 110 where the second insulating layer 1222 is formed: cleaning, chemical deposition, resist coating, exposure, development, dry etching, stripping, etc., to form a third insulating layer 1223 on the surface of the second insulating layer 1222 facing away from the substrate 110. When forming the third insulating layer 1223, the third insulating layer 1223 can be etched to form a third sub-via 1243. Accordingly, when the third insulating layer 1223 has a third sub-via 1243 and the second insulating layer 1222 has a second sub-via 1242, the first insulating layer 1221 and the gate insulating layer 1212 can be etched to form a first sub-via 1241 on the first insulating layer 1221 and a second via 125 on the gate insulating layer 1212. For example, if the third insulating layer 1223, the first insulating layer 1221 and the gate insulating layer 1212 are made of the same material, the same photolithography process can be used to open the third sub-via 1243 on the third insulating layer 1223, the first sub-via 1241 on the first insulating layer 1221 and the second via 125 on the gate insulating layer 1212, which helps to simplify the fabrication process of the array substrate 100.

[0101] In one exemplary embodiment, the first insulating layer 1221 may include a first PV insulating layer (referred to as PV1 layer). The second insulating layer 1222 may include a JAS insulating layer (referred to as JAS layer). The third insulating layer 1223 may include a second PV insulating layer (also referred to as PV2 layer). For example, the PV1 layer has a first sub-via 1241, the JAS layer has a second sub-via 1242, and the PV2 layer has a third sub-via 1243. However, this is not a limitation and is not intended to restrict the application of this method.

[0102] With a first sub-via 1241 on the first insulating layer 1221, a second sub-via 1242 on the second insulating layer 1222, a third sub-via 1243 on the third insulating layer 1223, and a second via 125 on the gate insulating layer 1212, the pixel electrode 123 in the array substrate 100 can be electrically connected to the source / drain electrode 1213 of the thin-film transistor 121 through the third sub-via 1243, the second sub-via 1242, and the first sub-via 1241, and electrically connected to the gate 1211 of the thin-film transistor 121 through the third sub-via 1243, the second sub-via 1242, the first sub-via 1241, and the second via 125. This allows the source / drain electrode 1213 and the gate 1211 of the thin-film transistor 121 to be electrically connected through the pixel electrode 123, which improves the ease of establishing the electrical connection between the gate 1211 and the source / drain electrode 1213 in the array substrate 100.

[0103] Furthermore, a dam structure 130 is formed on the surface of the pixel region 120 facing away from the substrate 110 to obtain the array substrate 100. The dam structure 130 is disposed around the pixel region 120, and when the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, the projection of the dam structure 130 in the vertical direction can also cover the first sub-through hole 1241, the second sub-through hole 1242 and the third sub-through hole 1243. Therefore, the arrangement of the first sub-through hole 1241, the second sub-through hole 1242 and the third sub-through hole 1243 will not adversely affect the display performance of the opening area of ​​the pixel region 120 included in the array substrate 100, thereby improving the display performance of the pixel region 120 included in the array substrate 100.

[0104] In some embodiments, after forming a second insulating layer 1222 on the surface of the first insulating layer 1221 away from the substrate 110 and etching the second insulating layer 1222 to form a second sub-via 1242, the fabrication method further includes forming a common electrode on the surface of the second insulating layer 1222 away from the substrate 110.

[0105] A third insulating layer 1223 is formed on the surface of the second insulating layer 1222 facing away from the substrate 110, including: forming the third insulating layer 1223 on the surface of the common electrode facing away from the substrate 110.

[0106] For example, when a second insulating layer 1222 and a second sub-via 1242 of the second insulating layer 1222 are formed on the substrate 110, one or more of the following processes can be performed on the substrate 110 on which the second insulating layer 1222 is formed: cleaning, physical film formation, coating, exposure, development, wet etching, stripping, annealing, etc., so as to form a common electrode on the surface of the second insulating layer 1222 away from the substrate 110.

[0107] Accordingly, when a common electrode is formed on the substrate 110, the substrate 110 on which the common electrode is formed can be subjected to one or more of the following processes: cleaning, chemical deposition, resist coating, exposure, development, dry etching, and stripping, so as to form a third insulating layer 1223 on the surface of the common electrode facing away from the substrate 110. The third insulating layer 1223 can be used to subsequently form a third sub-via 1243. Accordingly, after forming a second sub-via 1242 on the second insulating layer 1222 and a third sub-via 1243 on the third insulating layer 1223, a first sub-via 1241 can be formed on the first insulating layer 1221 and a second via 125 can be formed on the gate insulating layer 1212, so that the gate 1211 and the source / drain 1213 of the thin film transistor 121 can be electrically connected through the third sub-via 1243, the second sub-via 1242, the first sub-via 1241, the second via 125 and the pixel electrode 123.

[0108] The third insulating layer 1223 can physically separate the common electrode and the pixel electrode 123, so that a storage capacitor is formed between the common electrode and the pixel electrode 123. The storage capacitor formed between the common electrode and the pixel electrode 123 can improve the voltage stability of the pixel electrode 123, thereby improving the stability of the display performance of the pixel region 120 in the array substrate 100. Accordingly, the third insulating layer 1223 can be used to block impurities, protect the common electrode, and is the insulating medium in the storage capacitor.

[0109] In some embodiments, a plurality of dam substructures are formed on the surface of the pixel region 120 opposite to the substrate 110; the plurality of dam substructures are connected end to end in sequence, and the projection of at least one dam substructure in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0110] For example, when a pixel region 120 is formed on a substrate 110, the substrate 110 on which the pixel region 120 is formed can be subjected to one or more of the following processes: cleaning, coating, pre-baking, exposure, development, post-baking, etc., so as to form a plurality of sequentially connected dam substructures on the surface of the pixel region 120 away from the substrate 110.

[0111] As shown in Figure 6, the cofferdam structure 130 may include four cofferdam substructures, which are connected end to end in sequence. Of course, the number of cofferdam substructures included in the cofferdam structure 130 is not limited to this, and no limitation is made here.

[0112] When forming the cofferdam substructures included in the cofferdam structure 130, at least one cofferdam substructure can be configured such that its vertical projection can cover the first through hole 124 and the second through hole 125. This ensures that the first through hole 124 and the second through hole 125 are located in the non-opening area of ​​the pixel region 120, rather than in the opening area of ​​the pixel region 120. Therefore, the arrangement of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel region 120, thereby improving the display performance of the pixel region 120 included in the array substrate 100.

[0113] In some embodiments, the vertical projection of the connection between at least two cofferdam substructures can cover the first through hole 124 and the second through hole 125.

[0114] For example, since the cofferdam structure 130 includes multiple cofferdam substructures connected end-to-end in sequence, a connecting portion of each cofferdam substructure can serve as a connecting portion between at least two cofferdam substructures. In the vertical direction, if the first through-hole 124 and the second through-hole 125 can be covered by one of the connecting portions of a certain cofferdam substructure, then that connecting portion can serve as a connecting portion between at least two cofferdam substructures, such that the projection of the connecting portion between at least two cofferdam substructures in the vertical direction can cover the first through-hole 124 and the second through-hole 125.

[0115] For example, as shown in FIG6, the shape, size, etc. of the connection between at least two cofferdam substructures can be designed so that the projection of the connection between at least two cofferdam substructures in the vertical direction can cover the first through hole 124 and the second through hole 125.

[0116] Based on this, when the vertical projection of the connection between at least two cofferdam substructures can cover the first through hole 124 and the second through hole 125, it can be ensured that the first through hole 124 and the second through hole 125 are located in the non-opening area of ​​the pixel area 120, rather than in the opening area of ​​the pixel area 120. Therefore, the setting of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel area 120, thereby helping to improve the display performance of the pixel area 120 included in the array substrate 100.

[0117] For example, the cofferdam structure 130 has a vertical dimension greater than or equal to 1 micrometer.

[0118] For example, the vertical dimensions of the cofferdam structure 130 include one of 1 micrometer, 1.2 micrometer, 1.5 micrometer, 2 micrometer, 2.6 micrometer, etc. Of course, it is not limited to this, and no limitation is made here.

[0119] Since the dike structure 130 has a vertical dimension greater than or equal to 1 micrometer, it can serve as a physical separator between different pixel regions 120 to prevent crosstalk between them, ensuring uniform brightness and color, and improving contrast and yield. Therefore, the dike structure 130 is beneficial for improving the display performance of the pixel regions 120 included in the array substrate 100.

[0120] For example, the cofferdam structure 130 is made of insulating material.

[0121] For example, insulating materials are used to indicate materials with poor conductivity and high resistivity.

[0122] When the cofferdam structure 130 is arranged around the pixel region 120, and the projection of the cofferdam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, the cofferdam structure 130 can use the insulating properties of the insulating material to achieve electric field isolation between different pixel regions 120, so as to prevent electrical crosstalk between different pixel regions 120, thereby improving the display performance of the pixel region 120 included in the array substrate 100.

[0123] For example, insulating materials include at least one of silicon dioxide and silicon nitride.

[0124] For example, the insulating material used in the cofferdam structure 130 may include one of silicon dioxide and silicon nitride, or it may include a multilayer stacked structure of silicon dioxide and silicon nitride.

[0125] When the insulating material used in the cofferdam structure 130 includes at least one of silicon dioxide and silicon nitride, the cofferdam structure 130 can utilize the insulating properties of at least one of silicon dioxide and silicon nitride to achieve electric field isolation between different pixel regions 120, so as to prevent electrical crosstalk between different pixel regions 120, thereby improving the display performance of the pixel regions 120 included in the array substrate 100.

[0126] In one embodiment, the array substrate 100 is prepared according to the preparation method of the array substrate 100 provided in any of the above embodiments.

[0127] In an array substrate 100 including a pixel region 120, the pixel region 120 includes a thin-film transistor 121, a protective structure 122, and a pixel electrode 123 sequentially disposed on a substrate 110. The thin-film transistor 121 includes a gate 1211, a gate insulating layer 1212, an active layer, and a source / drain electrode 1213. The protective structure 122 is provided with a first via 124, and the gate insulating layer 1212 is provided with a second via 125. The pixel electrode 123 can be electrically connected to the source / drain electrode 1213 through the first via 124, and electrically connected to the gate 1211 through the first via 124 and the second via 125. This allows the gate 1211 and the source / drain electrode 1213 to be electrically connected through the pixel electrode 123, which is beneficial to improving the ease of establishing the electrical connection between the gate 1211 and the source / drain electrode 1213.

[0128] Furthermore, based on the structural configuration of the array substrate 100 in this application, when fabricating the array substrate 100, the thin-film transistor 121 and the protective structure 122 can be formed on the substrate 110 first, and then the protective structure 122 and the gate insulating layer 1212 can be etched to form the first via 124 of the protective structure 122 and the second via 125 of the gate insulating layer 1212. This eliminates the need for additional etching of the gate insulating layer 1212 during the fabrication of the active layer and source / drain electrodes 1213 of the thin-film transistor 121, thus reducing the number of photolithography steps in the fabrication process of the array substrate 100. Compared to the photolithography steps required in related technologies, the fabrication process of the array substrate 100 in this application effectively combines the photolithography steps required for fabricating layers 2 to 4 in related technologies into one or two photolithography steps, thereby reducing at least one photolithography step in the fabrication process of the array substrate 100, which simplifies the fabrication process of the array substrate 100. Based on this, the process for preparing the array substrate 100 in this application can improve the ease of preparing the array substrate 100.

[0129] Correspondingly, if the array substrate 100 includes a dam structure 130 corresponding to the pixel region 120, the dam structure 130 is disposed around the pixel region 120, and the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, the arrangement of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel region 120, which is beneficial to improving the display performance of the pixel region 120 included in the array substrate 100.

[0130] Please refer to Figure 8, which is a schematic diagram of the structure of an electronic device 10 provided in an embodiment of this application.

[0131] In one embodiment, the electronic device 10 includes an array substrate 100 as provided in any of the embodiments described above.

[0132] It should be understood that the array substrate 100 provided in any of the above embodiments can realize the electrical connection between the pixel electrode 123 and the source / drain electrode 1213 of the thin film transistor 121 by using the first through hole 124 provided on the protective structure 122, and realize the electrical connection between the pixel electrode 123 and the gate 1211 of the thin film transistor 121 by using the first through hole 124 provided on the protective structure 122 and the second through hole 125 provided on the gate insulating layer 1212 of the thin film transistor 121. In this way, the gate 1211 of the thin film transistor 121 and the source / drain electrode 1213 of the thin film transistor 121 can be electrically connected through the pixel electrode 123, which is beneficial to improving the ease of establishing the electrical connection between the gate 1211 and the source / drain electrode 1213.

[0133] Furthermore, based on the structural configuration of the array substrate 100 in this application, when fabricating the array substrate 100, the thin-film transistor 121 and the protective structure 122 can be formed on the substrate 110 first, and then the protective structure 122 and the gate insulating layer 1212 can be etched to form the first via 124 of the protective structure 122 and the second via 125 of the gate insulating layer 1212. This eliminates the need for additional etching of the gate insulating layer 1212 during the fabrication of the active layer and source / drain electrodes 1213 of the thin-film transistor 121, thereby reducing the number of photolithography steps in the fabrication process of the array substrate 100. Compared to the photolithography steps required in related technologies, the fabrication process of the array substrate 100 in this application effectively combines the photolithography steps required for fabricating layers 2 to 4 in related technologies into one or two photolithography steps, thus reducing at least one photolithography step in the fabrication process of the array substrate 100, which simplifies the fabrication process of the array substrate 100. Based on this, the process for preparing the array substrate 100 in this application can improve the ease of preparing the array substrate 100.

[0134] Correspondingly, if the array substrate 100 includes a dam structure 130 corresponding to the pixel region 120, the dam structure 130 is disposed around the pixel region 120, and the projection of the dam structure 130 in the vertical direction can cover the first through hole 124 and the second through hole 125, the arrangement of the first through hole 124 and the second through hole 125 will not adversely affect the display performance of the pixel region 120, which is beneficial to improving the display performance of the pixel region 120 included in the array substrate 100.

[0135] The specific structure, fabrication method and implementation principle of the array substrate 100 included in the electronic device 10 can be found in the previous text and will not be described again here.

[0136] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0137] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0138] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating an array substrate, characterized in that, The fabrication method includes: sequentially forming a gate and a gate insulating layer on the surface of a substrate; forming an active layer and a source / drain electrode on the surface of the gate insulating layer facing away from the substrate to obtain a thin-film transistor; forming a protective structure on the surface of the thin-film transistor facing away from the substrate, and etching the protective structure to form a first via of the protective structure, and etching the gate insulating layer to form a second via of the gate insulating layer; forming a pixel electrode on the surface of the protective structure facing away from the substrate to obtain a pixel region; the pixel electrode is electrically connected to the source / drain electrode through the first via, and electrically connected to the gate through the first via and the second via; forming a dam structure on the surface of the pixel region facing away from the substrate to obtain an array substrate; the dam structure is disposed around the pixel region, and the projection of the dam structure in the vertical direction can cover the first via and the second via.

2. The preparation method according to claim 1, characterized in that, The method of forming an active layer and source / drain electrodes on the surface of the gate insulating layer opposite to the substrate includes: forming the active layer and source / drain electrodes on the surface of the gate insulating layer opposite to the substrate based on a halftone mask.

3. The preparation method according to claim 1, characterized in that, The protective structure includes a first insulating layer, a second insulating layer, and a third insulating layer. The process of forming the protective structure on the surface of the thin-film transistor facing away from the substrate, etching the protective structure to form a first via of the protective structure, and etching the gate insulating layer to form a second via of the gate insulating layer includes: forming a first insulating layer on the surface of the thin-film transistor facing away from the substrate; forming a second insulating layer on the surface of the first insulating layer facing away from the substrate, and etching the second insulating layer to form a second sub-via of the second insulating layer; and etching the second insulating layer to form a second sub-via of the second insulating layer. A third insulating layer is formed on the surface of the insulating layer opposite to the substrate. The first insulating layer, the third insulating layer, and the gate insulating layer are etched to form a first sub-via of the first insulating layer, a third sub-via of the third insulating layer, and a second via of the gate insulating layer. The first via includes the first sub-via, the second sub-via, and the third sub-via. The pixel electrode is electrically connected to the source and drain electrodes through the third sub-via, the second sub-via, and the first sub-via, and is electrically connected to the gate electrode through the third sub-via, the second sub-via, the first sub-via, and the second via.

4. The preparation method according to claim 3, characterized in that, After forming a second insulating layer on the surface of the first insulating layer away from the substrate and etching the second insulating layer to form a second sub-via, the fabrication method further includes: forming a common electrode on the surface of the second insulating layer away from the substrate; the step of forming a third insulating layer on the surface of the second insulating layer away from the substrate includes: forming a third insulating layer on the surface of the common electrode away from the substrate.

5. The preparation method according to any one of claims 1 to 4, characterized in that, Forming a dam structure on the surface of the pixel region away from the substrate includes: forming multiple dam substructures on the surface of the pixel region away from the substrate; the multiple dam substructures are connected end to end in sequence, and the projection of at least one of the dam substructures in the vertical direction can cover the first through hole and the second through hole.

6. The preparation method according to claim 5, characterized in that, The vertical projection of the connection between at least two of the cofferdam substructures can cover the first through hole and the second through hole.

7. The preparation method according to any one of claims 1 to 4, characterized in that, The cofferdam structure has a vertical dimension greater than or equal to 1 micrometer.

8. The preparation method according to any one of claims 1 to 4, characterized in that, The materials used in the cofferdam structure include insulating materials.

9. An array substrate, characterized in that, The array substrate is prepared by the method for preparing the array substrate according to any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes the array substrate as described in claim 9.

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