Integrated circuit device

Abstract

An integrated circuit device includes: a substrate; and a metal oxide semiconductor capacitor (MOSCAP) on the substrate. The MOSCAP includes: a lower semiconductor device on a substrate, the lower semiconductor device including a pair of lower source / drain regions and a lower gate structure between the pair of lower source / drain regions; and an upper semiconductor device on the lower semiconductor device, the upper semiconductor device including a pair of upper source / drain regions and an upper gate structure between the pair of upper source / drain regions. A lower gate structure is electrically connected to both of the pair of upper source / drain regions.

Description

Technical Field

[0001] This disclosure generally relates to the field of integrated circuit devices, and more specifically, to integrated circuit devices including high-density capacitors. Background Technology

[0002] The size of transistors in integrated circuit (IC) devices has continued to shrink in order to miniaturize logic elements. This has led to gate-all-around (GAA) structures, such as multi-bridge channel FETs (field-effect transistors) (MBCFETs). TM The development of nanosheet FETs (NSFETs) and other similar technologies is also underway. Furthermore, as technologies for increasing transistor density continue to evolve, three-dimensional (3D) device structures (such as stacked transistors) are being considered.

[0003] A stacked transistor (or “transistor stack”) may include a first transistor and a second transistor. The first transistor may be a first type of transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and the second transistor may be a second type of transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). The first-type transistor and the second-type transistor may be complementary to each other and may therefore be part of a complementary metal-oxide-semiconductor (CMOS) structure. The first and second transistors may be stacked in any order (e.g., the first on top of the second, or the second on top of the first), thereby creating a stack comprising an upper transistor and a lower transistor. Summary of the Invention

[0004] An integrated circuit device according to some embodiments herein may include: a substrate; and a metal-oxide-semiconductor capacitor (MOSCAP), on the substrate, the MOSCAP including: a lower semiconductor device, on the substrate, the lower semiconductor device including a pair of lower source / drain regions and a lower gate structure between the pair of lower source / drain regions; and an upper semiconductor device, on the lower semiconductor device, the upper semiconductor device including a pair of upper source / drain regions and an upper gate structure between the pair of upper source / drain regions. The lower gate structure is electrically connected to both of the pair of upper source / drain regions.

[0005] An integrated circuit device according to some embodiments herein may include: a substrate; a front-side metal-oxide-semiconductor capacitor (MOMCAP) on a first surface of the substrate; and a back-side MOMCAP capacitor on a second surface of the substrate opposite to the first surface, the back-side MOMCAP being electrically connected to the front-side MOMCAP.

[0006] An integrated circuit device according to some embodiments herein may include: a substrate; a metal-oxide-semiconductor capacitor (MOSCAP) on a first surface of the substrate; and a back-side metal-oxide-metal capacitor (MOMCAP) on a second surface of the substrate opposite to the first surface, the back-side MOMCAP being electrically connected to the MOSCAP.

[0007] The exemplary embodiments of this application are partly derived from the understanding that providing one or more high-density capacitors in an integrated circuit device can be advantageous by modifying existing architectures used to form three-dimensional (3D) stacked transistors (such as 3D stacked field-effect transistors (3DSFETs)) in the integrated circuit device, thereby simplifying the manufacturing process for the high-density capacitors and reducing the associated manufacturing costs. For example, high-density capacitors can be used as decoupling capacitors to help provide a stable voltage supply and / or filter out noise within the integrated circuit device. Attached Figure Description

[0008] Figure 1 It is a schematic cross-sectional view of a traditional integrated circuit device.

[0009] Figure 2A This is a schematic block diagram of a transistor stack of an integrated circuit device according to some embodiments.

[0010] Figure 2B This is a schematic plan view of an integrated circuit device according to some embodiments.

[0011] Figure 2C It is along Figure 2B A schematic cross-sectional view taken by line A-A'.

[0012] Figure 2D It is along Figure 2B A schematic cross-sectional view taken by line B-B'.

[0013] Figure 3A This is a schematic block diagram of a metal-oxide-semiconductor capacitor (MOSCAP) for an integrated circuit device according to some embodiments.

[0014] Figure 3B This is a schematic plan view of an integrated circuit device according to some embodiments.

[0015] Figure 3C It is along Figure 3B A schematic cross-sectional view taken by line B-B'.

[0016] Figure 3D It is along Figure 3B A schematic cross-sectional view taken by line C-C'.

[0017] Figure 3E It is along Figure 3B A schematic cross-sectional view taken by line D-D'.

[0018] Figure 3F This is a schematic plan view of a front-side metal oxide metal capacitor (MOMCAP) according to some embodiments.

[0019] Figure 3G According to some embodiments, including Figure 3F A schematic plan view of the front side of the MOMCAP integrated circuit device.

[0020] Figure 3H This is a schematic plan view of the rear-side MOMCAP according to some embodiments.

[0021] Figure 3I According to some embodiments, including Figure 3H A schematic plan view of the integrated circuit device on the back side of MOMCAP.

[0022] Figure 3J According to some embodiments Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A schematic circuit diagram of MOSCAP.

[0023] Figure 3K According to some embodiments Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E A schematic circuit diagram of an integrated circuit device.

[0024] Figure 4 This illustrates some embodiments. Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E The graph of the CV curve of MOSCAP.

[0025] Figure 5A This is a schematic plan view of the front MOMCAP according to some other embodiments.

[0026] Figure 5B This is a schematic plan view of the back-side MOMCAP according to some other embodiments.

[0027] Figure 6A It is according to some other embodiments along Figure 3B A schematic cross-sectional view taken by line C-C'.

[0028] Figure 6BIt is according to some other embodiments along Figure 3B A schematic cross-sectional view taken by line D-D'. Detailed Implementation

[0029] According to the exemplary embodiments herein, an integrated circuit device including high-density capacitors is provided. The exemplary embodiments of this application are partly derived from the understanding that existing architectures for forming three-dimensional (3D) stacked transistors (such as 3D stacked field-effect transistors (3DSFETs)) in an integrated circuit device can be modified to provide one or more high-density capacitors in the integrated circuit device. For example, these capacitors can be used as decoupling capacitors to help provide a stable voltage supply and / or filter noise within the integrated circuit device, but the exemplary embodiments are not limited thereto. By modifying existing 3D stacked transistor architectures, capacitors can be seamlessly implemented in the integrated circuit device while operating in conjunction with 3D stacked transistors.

[0030] The exemplary embodiments will be described in more detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic cross-sectional view of a conventional integrated circuit device. (Refer to...) Figure 1 A conventional integrated circuit device 1 may include a substrate 10, a planar transistor 2 on the substrate 10, and a metal-oxide-semiconductor capacitor (MOSCAP) 3 on the substrate 10. For example, as Figure 1 As shown, the planar transistor 2 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), but the embodiments of this disclosure are not limited thereto.

[0032] The planar transistor 2 may include a source / drain region 6, a body region 7, and a well region 8. The planar transistor 2 may be a p-type transistor (e.g., a p-type metal-oxide-semiconductor (PMOS) transistor). However, it will be understood that, according to embodiments of this disclosure, the conductivity type (i.e., p-type and n-type) of the regions and / or layers may be reversed. In other embodiments, the planar transistor 2 may be an n-type transistor (e.g., an n-type metal-oxide-semiconductor (NMOS) transistor), and the conductivity type of the source / drain region 6, body region 7, and well region 8 may be reversed. Figure 1 The conductivity types of the source / drain region 6, the body region 7, and the well region 8 shown are reversed. The source / drain region 6, the body region 7, the well region 8, and the substrate 10 are part of the semiconductor layer structure 13 of the conventional integrated circuit device 1.

[0033] The planar transistor 2 may further include a gate electrode 11 and a gate insulator 12. The gate electrode 11 and the gate insulator 12 are located on the upper surface of the semiconductor layer structure 13. The gate insulator 12 insulates the gate electrode 11 from the semiconductor layer structure 13 (i.e., isolates it). The gate electrode 11 is electrically connected to the gate terminal G, the source / drain region 6 is electrically connected to the drain terminal D and the source terminal S, respectively, and the body region 7 is electrically connected to the body terminal B. In some embodiments, the source terminal S may be electrically short-circuited (i.e., electrically connected) to the body terminal B. The current flow between the source / drain regions 6 of the planar transistor 2 can be controlled based on the voltage applied to the gate terminal G.

[0034] like Figure 1 As shown, MOSCAP 3 may include a first MOSCAP 4 and a second MOSCAP 5. As used herein, MOSCAP 3 may also be referred to as a "MOS varactor diode". The first MOSCAP 4 may be an n-type capacitor, and the second MOSCAP 5 may be a p-type capacitor.

[0035] The first MOSCAP 4 includes a source / drain region 6, a well region 8, a gate electrode 11, and a gate insulator 12. The source / drain region 6 and the well region 8 are portions of the semiconductor layer structure 13. The source / drain region 6 is electrically connected to the drain terminal D and the source terminal S, respectively, and the gate electrode 11 is electrically connected to the gate terminal G. Figure 1 As shown, the drain terminal D can be electrically shorted to the source terminal S. For example, the drain terminal D and the source terminal S can be electrically connected together to the input signal.

[0036] The first MOSCAP 4 can operate as a voltage-controlled capacitor dependent on the capacitance between the gate electrode 11 and the underlying semiconductor layer structure 13. More specifically, the gate electrode 11 and the semiconductor layer structure 13 can form a capacitor, while the gate insulator 12 serves as the dielectric between the gate electrode 11 and the semiconductor layer structure 13. The gate electrode 11 and the semiconductor layer structure 13 can be considered as the conductive plates of the capacitor, and the gate insulator 12 serves as the dielectric between the gate electrode 11 and the semiconductor layer structure 13. In some embodiments, the gate electrode 11 comprises a metallic material, the gate insulator 12 comprises an oxide insulating material (e.g., silicon oxide, but embodiments of this disclosure are not limited thereto), and the semiconductor layer structure 13 comprises a semiconductor material, hence the designation Metal-Oxide-Semiconductor Capacitor (MOSCAP). The capacitance of the first MOSCAP 4 can vary based on the voltage applied to the gate terminal G.

[0037] The second MOSCAP 5 includes a source / drain region 6, a well region 8, a deep well region 9, a gate electrode 11, and a gate insulator 12. The source / drain region 6, well region 8, and deep well region 9 are portions of the semiconductor layer structure 13. The source / drain region 6 is electrically connected to the drain terminal D and the source terminal S, respectively, and the gate electrode 11 is electrically connected to the gate terminal G. Figure 1 As shown, the drain terminal D can be electrically shorted to the source terminal S. For example, the drain terminal D and the source terminal S can be electrically connected together to an input signal. The second MOSCAP 5 can operate as a voltage-controlled capacitor that depends on the capacitance between the gate electrode 11 and the underlying semiconductor layer structure 13. The capacitance of the second MOSCAP 5 can vary based on the voltage applied to the gate terminal G.

[0038] Still refer to Figure 1 The capacitance values ​​of the first MOSCAP 4 and the second MOSCAP 5 can vary depending on whether the first MOSCAP 4 and the second MOSCAP 5 are operating in the accumulation region, depletion region, or inversion region. The first MOSCAP 4 and the second MOSCAP 5 can each operate in the accumulation region, depletion region, or inversion region based on the voltage applied to the respective gate terminal G of the first MOSCAP 4 and the second MOSCAP 5. The well region 8 and the deep well region 9 of the semiconductor layer structure 13 can be configured such that they have (i.e., they exhibit) maximum capacitance values ​​when the first MOSCAP 4 and the second MOSCAP 5 are operating in the accumulation region.

[0039] As described above, the first MOSCAP 4 and the second MOSCAP 5 can each operate as a voltage-controlled capacitor whose capacitance value can vary based on the voltage applied to the respective gate terminal G. Therefore, MOSCAP 3, including the first MOSCAP 4 and the second MOSCAP 5, can operate as a MOS varactor diode.

[0040] Figure 2A This is a schematic block diagram of a transistor stack of an integrated circuit device according to some embodiments.

[0041] Reference Figure 2A The integrated circuit device 100 includes a substrate 110 and a transistor stack 101 on a first surface S1 (i.e., the front side) of the substrate 110. The substrate 110 may extend in a first direction X (also referred to as a first horizontal direction) and a second direction Y (also referred to as a second horizontal direction). The first direction X and the second direction Y may be parallel to the surfaces of the substrate 110 (e.g., the first surface S1 and / or the second surface S2). For example, the first direction X may intersect the second direction Y. In some embodiments, the first direction X may be perpendicular to the second direction Y.

[0042] A first surface S1 of substrate 110 is opposite a second surface S2 (i.e., the back side) of substrate 110 in a third direction Z (also referred to as the vertical direction). For example, the third direction Z may intersect a first direction X and a second direction Y. In some embodiments, the third direction Z may be perpendicular to the first direction X and / or the second direction Y. The third direction Z may be perpendicular to the surfaces of substrate 110 (e.g., the first surface S1 and / or the second surface S2). As used herein, the first surface S1 may also be referred to as the “upper surface” of substrate 110, and the second surface S2 may also be referred to as the “lower surface” of substrate 110.

[0043] In some embodiments, the substrate 110 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride, and / or low-k dielectric materials) or may be formed of insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride, and / or low-k dielectric materials). Low-k dielectric materials may include, for example, fluorine-doped silicon oxide, organosilicon glass, carbon-doped oxides, porous silicon dioxide, porous organosilicon glass, spin-on organic polymer dielectrics, and / or spin-on silicon-based polymer dielectrics. The thickness of the substrate 110 in the third direction Z may be, for example, in the range of (about) 50 nanometers (nm) to 100 nm, but is not limited thereto.

[0044] The transistor stack 101 includes a lower transistor Tb of the stack having a lower channel layer 120b and an upper transistor Ta of the stack having an upper channel layer 120a. The channel layers 120a and 120b may comprise, for example, one or more semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the channel layers 120a and 120b may be nanosheets having a thickness in the third-direction Z-axis, for example, in the range of (about) 1 nm to 100 nm, or may be nanowires having a circular cross-section with a diameter in the range of (about) 1 nm to 100 nm.

[0045] In the third direction Z, the lower transistor Tb lies between the upper transistor Ta and the substrate 110. For example, the upper transistor Ta may be stacked with the lower transistor Tb in the third direction Z. As used herein, "element A is stacked with element B in one direction" (or similar language) means that there exists at least one straight line extending in that direction and intersecting both element A and element B. The transistor stack 101 may also include an isolation region 130 (such as an intermediate dielectric isolation (MDI) region). In some embodiments, the isolation region 130 may serve as a spacer between the upper transistor Ta and the lower transistor Tb. Therefore, the isolation region 130 may also be referred to herein as a "spacer".

[0046] In the first direction X, the lower channel layer 120b of the lower transistor Tb lies between a pair of lower source / drain (S / D) regions 140 electrically connected to the lower channel layer 120b. Similarly, in the first direction X, the upper channel layer 120a of the upper transistor Ta lies between a pair of upper source / drain regions 150 electrically connected to the upper channel layer 120a. In the third direction Z, the lower source / drain regions 140 may lie between the upper source / drain regions 150 and the substrate 110.

[0047] The lower source / drain region 140 and the upper source / drain region 150 may each include a semiconductor layer (e.g., a silicon (Si) layer, a silicon carbide (SiC) layer, and / or a silicon-germanium (SiGe) layer), and may additionally include dopants in the semiconductor layers. For example, each of the lower source / drain region 140 and the upper source / drain region 150 may include an epitaxial semiconductor layer having dopants (i.e., impurities) therein. In some embodiments, the upper source / drain region 150 may include a semiconductor material different from the semiconductor material of the lower source / drain region 140. As an example, the upper source / drain region 150 may include silicon-germanium, and the lower source / drain region 140 may include silicon carbide, or vice versa. In other embodiments, the upper source / drain region 150 may include the same semiconductor material as the lower source / drain region 140.

[0048] In some embodiments, the lower source / drain region 140 has a first conductivity type, and the upper source / drain region 150 has a second conductivity type. As used herein, the terms "first conductivity type" and "second conductivity type" are used to indicate n-type or p-type, wherein the first conductivity type and the second conductivity type are different from each other. Thus, if a first region of the device has a first conductivity type and a second region of the device has a second conductivity type, it means that the first region has n-type conductivity and the second region has p-type conductivity, or alternatively, the first region has p-type conductivity and the second region has n-type conductivity. For example, the lower source / drain region 140 may include n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), and the upper source / drain region 150 may include p-type impurities (e.g., boron (B), gallium (Ga), indium (In), etc.), or vice versa.

[0049] The lower transistor Tb and the upper transistor Ta may have complementary conductivity types (e.g., to provide a complementary metal-oxide-semiconductor (CMOS) device). For example, the lower transistor Tb may have a first conductivity type, while the upper transistor Ta may have a second conductivity type. Furthermore, although shown with reference to the lower transistor Tb and the upper transistor Ta, it will be understood that, according to some embodiments, the transistor stack 101 is not limited to a dual-transistor arrangement and may include additional transistors vertically stacked on the substrate 110.

[0050] To simplify the explanation, Figure 2A Only one transistor stack 101 is shown in the diagram. However, it will be understood that, according to some embodiments, the integrated circuit device 100 may include two, three, four or more transistor stacks 101.

[0051] Figure 2B This is a schematic plan view of an integrated circuit device according to some embodiments. For the sake of simplicity, Figure 2B Only some components of the integrated circuit device 100 are shown. For example... Figure 2B As shown, the integrated circuit device 100 includes one or more gate structures 170 on the upper channel layer 120a of the upper transistor Ta and the lower channel layer 120b of the lower transistor Tb. An upper gate contact 148 is electrically connected to the gate structure 170. In some embodiments, the integrated circuit device 100 also includes a dummy gate structure 171. Line A-A' extends along the channel width of the upper channel layer 120a of the upper transistor Ta in a first direction X. Line B-B' extends longitudinally (i.e., lengthwise) through the gate structure 170 in a second direction Y.

[0052] Figure 2C yes Figure 2B A schematic cross-sectional view taken along line A-A'. (Refer to...) Figure 2B and Figure 2C The gate structure 170 may include an upper gate structure 170a and a lower gate structure 170b. A pair of upper source / drain regions 150, an upper channel layer 120a, and an upper gate structure 170a partially form an upper transistor Ta. A pair of lower source / drain regions 140, a lower channel layer 120b, and a lower gate structure 170b partially form a lower transistor Tb. The lower transistor Tb and the upper transistor Ta include the transistor stack 101 of the integrated circuit device 100 (see...). Figure 2A As used herein, the upper trench layer 120a may also be referred to as the "upper trench region", and the lower trench layer 120b may also be referred to as the "lower trench region".

[0053] A pair of upper source / drain regions 150 may be spaced apart from each other (e.g., in the first direction X), and an upper gate structure 170a is located between the pair of upper source / drain regions 150. A pair of lower source / drain regions 140 may be spaced apart from each other (e.g., in the first direction X), and a lower gate structure 170b is located between the pair of lower source / drain regions 140. An upper channel layer 120a may be located between the pair of upper source / drain regions 150 (e.g., in the first direction X). The source / drain regions 150 are electrically connected to the upper channel layer 120a. Figure 2C As shown, the upper channel layers 120a are spaced apart from each other in the third direction Z, and the upper gate structure 170a is located between the upper channel layers 120a. Although Figure 2CThree upper channel layers 120a are shown, but this disclosure is not limited thereto. In other embodiments, the integrated circuit device 100 may include more than three upper channel layers 120a or fewer than three upper channel layers 120a. A lower channel layer 120b may be located between a pair of lower source / drain regions 140 (e.g., in a first direction X). The source / drain regions 140 are electrically connected to the lower channel layer 120b. Figure 2C As shown, the lower channel layers 120b are spaced apart from each other in the third direction Z, and the lower gate structure 170b is located between the lower channel layers 120b. Although Figure 2C Two lower channel layers 120b are shown, but this disclosure is not limited thereto. In other embodiments, the integrated circuit device 100 may include more than two lower channel layers 120b or only one lower channel layer 120b.

[0054] An upper gate structure 170a may be located on the upper channel layer 120a of the upper transistor Ta, and a lower gate structure 170b may be located on the lower channel layer 120b of the lower transistor Tb. The upper gate structure 170a includes an upper conductive gate 174a. The upper conductive gate 174a may be located between the upper channel layers 120a (e.g., in the third direction Z) and may be spaced apart from the upper source / drain region 150 in the first direction X by an inner spacer 172. In the third direction Z, the inner spacer 172 may be located on the sidewalls of the upper conductive gate 174a and between the upper channel layers 120a. The inner spacer 172 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials).

[0055] The lower gate structure 170b may include a lower conductive gate 174b (e.g., in the third direction Z) between lower channel layers 120b. The lower conductive gate 174b may be spaced apart from the lower source / drain region 140 in the first direction X by an inner spacer 172, which may be on the sidewalls of the lower conductive gate 174b and between the lower channel layers 120b in the third direction Z. In some embodiments, the inner spacer 172 may contact the lower source / drain region 140, the upper source / drain region 150, the sidewalls of the lower conductive gate 174b, and the sidewalls of the upper conductive gate 174a. The sidewalls of the lower channel layer 120b may contact the lower source / drain region 140, and the sidewalls of the upper channel layer 120a may contact the upper source / drain region 150.

[0056] The upper conductive gate 174a and the lower conductive gate 174b may each comprise a metallic material (e.g., tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru)) and / or a semiconductor material. In some embodiments, the upper conductive gate 174a and the lower conductive gate 174b may each comprise a metal layer and one or more work function layers (e.g., TiN layer, TaN layer, TiAl layer, TiC layer, TiAlC layer, TiAlN layer, and / or WN layer). For example, one or more work function layers may be disposed between the metal layer and the gate insulating layer (not shown). In some embodiments, one or more work function layers may separate the metal layer from the gate insulating layer.

[0057] In some embodiments, the upper conductive gate 174a and the lower conductive gate 174b may each comprise different metals or metallic materials. In other embodiments, the upper conductive gate 174a and the lower conductive gate 174b may comprise the same metallic material.

[0058] To simplify the explanation, from Figure 2C The view in the diagram omits the gate insulating layer. However, it will be understood that each gate structure 170 may include a gate insulating layer extending between channel layers 120a, 120b and conductive gates 174a, 174b. The gate insulating layer may surround the conductive gates 174a, 174b and may separate (i.e., insulate) the conductive gates 174a, 174b from the channel layers 120a, 120b. In some embodiments, the gate insulating layer may be thinner than the isolation region 130 (e.g., on the third direction Z). The gate insulating layer may include a single layer or multiple layers (e.g., a silicon oxide layer and / or a high-k material layer). For example, the high-k material layer may include Al2O3, HfO2, ZrO2, HfZrO4, TiO2, Sc2O3, Y2O3, La2O3, Lu2O3, Nb2O5, and / or Ta2O5. It will be understood that, as used herein, “element A surrounds element B” (or similar language) means that element A is at least partially around element B, but does not necessarily mean that element A completely surrounds element B.

[0059] The isolation region 130 may be a spacer separating the lower channel layer 120b of the lower transistor Tb from the upper channel layer 120a of the upper transistor Ta. The isolation region 130 may be located between the upper gate structure 170a and the lower gate structure 170b (e.g., on the third direction Z). The isolation region 130 may include, for example, one or more isolation layers comprising one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron carbonitride (SiBCN), and / or low-k materials). Although Figure 2C The isolation region 130 is shown as a single layer, but in some embodiments, the isolation region 130 may include multiple layers.

[0060] In some embodiments, an intermediate layer 122 may be disposed on a first surface S1 of the substrate 110. For example, the intermediate layer 122 may extend between the substrate 110 and the lower transistor Tb. The intermediate layer 122 may contact the first surface S1 of the substrate 110 and the lower transistor Tb (e.g., the lower source / drain region 140 and the lower gate structure 170b). For example, the intermediate layer 122 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). In other embodiments, the intermediate layer 122 may be omitted.

[0061] The upper spacer 138 may be located on the opposite sidewall of the upper portion of the upper gate structure 170a. The insulating liner 136 may be located between the upper spacer 138 and the upper portion of the upper gate structure 170a. The upper spacer 138 and the insulating liner 136 may include, for example, one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron carbonitride (SiBCN) and / or low-k materials).

[0062] On the third-party Z-direction, the integrated circuit device 100 may further include a first insulating layer 152 between the lower source / drain region 140 and the upper source / drain region 150. The first insulating layer 152 separates the lower source / drain region 140 from the upper source / drain region 150. The first insulating layer 152 may also be on the upper surface of each of the upper source / drain regions 150. For example, the first insulating layer 152 may surround the lower source / drain region 140 and the upper source / drain region 150. The first insulating layer 152 may include, for example, one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron carbonitride (SiBCN), and / or low-k materials). Although the first insulating layer 152 is shown as a single layer, in some embodiments, the first insulating layer 152 may include multiple layers.

[0063] The dummy gate structure 171 may be a non-electrically active gate structure (e.g., a non-activated gate structure) and may be formed as a physical structure replicating the gate structure 170. In some embodiments, dummy gate spacers 117 may be located on the sidewalls of the dummy gate structure 171. The dummy gate spacers 117 may include, for example, one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon carbonitride, silicon boron carbonitride (SiBCN), and / or low-k materials). In other embodiments, the dummy gate spacers 117 and the dummy gate structure 171 may be omitted and the gate structure 170 may be used instead.

[0064] The integrated circuit device 100 also includes an upper structure 146 on a first insulating layer 152. The upper structure 146 may include elements formed in a mid-process (MOL) portion and / or a back-end process (BEOL) portion of the device fabrication. As used herein, the upper structure 146 may also be referred to as a "BEOL structure". The upper structure 146 may include conductive elements (e.g., one or more conductive lines and / or one or more via plugs) and insulating elements (e.g., one or more intermediate layers and / or one or more spacers). For example, the upper structure 146 may include an interlayer insulating layer, conductive lines (e.g., metal lines) disposed in the interlayer insulating layer and stacked in a third direction Z, and conductive via plugs (e.g., metal via plugs), each of which is electrically connectable to two conductive lines spaced apart from each other in a third direction Z. Although not explicitly stated in the original text... Figure 2C As shown in the cross-sectional view, however, the conductive elements of the upper structure 146 may be electrically connected to, for example, one or more of the upper source / drain regions 150, one or more of the lower source / drain regions 140, and / or the gate structure 170.

[0065] The integrated circuit device 100 may also include a back-side power delivery network (BSPDN) structure 144 on a second surface S2 (i.e., the back side) of the substrate 110. Back-side contact structures (not shown) may electrically connect the BSPDN structure 144 to one or more of the lower source / drain regions 140. The BSPDN structure 144 may include a back-side insulator and one or more back-side power rails disposed within the back-side insulator. The back-side power rails may be electrically connected to a power source having predetermined voltages (e.g., drain voltage (Vdd) and / or source voltage (Vss)). For example, the BSPDN structure 144 may include a power delivery network. The power delivery network may include a wiring network for delivering power (e.g., gate voltage and / or source / drain voltage) to the back-side power rails.

[0066] As used herein, a back-side power rail may refer to one or more conductive elements included in the BSPDN structure 144. For example, a back-side power rail may include power rails, conductive via plugs, and / or conductive lines included in the BSPDN structure 144. That is, the BSPDN structure 144 may include one or more conductive layers (e.g., metal layers) stacked on a third-direction Z-axis to deliver back-side power to, for example, a lower transistor Tb. The conductive layers may be individually included in insulating layers, and conductive via plugs (e.g., metal via plugs) may electrically connect the conductive layers to each other on a third-direction Z-axis. The conductive layers may include one or more conductive lines (e.g., metal lines).

[0067] In some embodiments, an intermediate structure (not shown) may be disposed between the substrate 110 and the BSPDN structure 144, and the substrate 110 and the BSPDN structure 144 may be separated. The BSPDN structure 144 may improve the power delivery efficiency in the integrated circuit device 100, reduce the area for power delivery in the integrated circuit device 100, and / or improve the voltage drop (i.e., IR drop) in the integrated circuit device 100.

[0068] In some embodiments, the upper transistor Ta and the lower transistor Tb can be different types of MOSFETs. Therefore, the integrated circuit device 100 may include stacked FET devices. For example, the upper transistor Ta and the lower transistor Tb may be a PMOS transistor and an NMOS transistor, respectively, or vice versa. In some embodiments, the upper transistor Ta and the lower transistor Tb may each be a three-dimensional (3D) field-effect transistor (FET) (such as a multi-bridge channel FET (MBCFET) or a gate-all-around FET (GAAFET)), but embodiments of this disclosure are not limited thereto. In some embodiments, the upper transistor Ta and the lower transistor Tb may be formed as a CMOS structure. The upper transistor Ta and the lower transistor Tb may be stacked on the substrate 110 in a third-direction Z-axis orientation.

[0069] Figure 2D It is along Figure 2B A schematic cross-sectional view of line B-B'. (Refer to...) Figure 2B and Figure 2D The lower gate structure 170b may surround the lower channel layer 120b. For example, the lower gate structure 170b (e.g., the lower conductive gate 174b) may be present on the upper surface, lower surface, and opposite side surface of each lower channel layer 120b. For simplicity, from... Figure 2D The view in the diagram omits the gate insulating layer of the lower gate structure 170b. However, it will be understood that the gate insulating layer may be disposed between each lower channel layer 120b and the lower conductive gate 174b, and the lower conductive gate 174b may be separated from the lower channel layer 120b.

[0070] An upper gate structure 170a may surround an upper channel layer 120a. For example, the upper gate structure 170a (e.g., an upper conductive gate 174a) may be present on the upper surface, lower surface, and opposite side surface of each upper channel layer 120a. For simplicity, from... Figure 2D The view in the diagram omits the gate insulating layer of the upper gate structure 170a. However, it will be understood that the gate insulating layer may be disposed between each upper channel layer 120a and the upper conductive gate 174a, and the upper conductive gate 174a may be separated from the upper channel layer 120a.

[0071] The upper gate contact 148 extends into the first insulating layer 152 and can electrically connect the lower gate structure 170b (e.g., the lower conductive gate 174b) and the upper gate structure 170a (e.g., the upper conductive gate 174a) to the upper structure 146. The upper gate contact 148 may include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co and / or Ru.

[0072] The isolation region 130 separates and electrically isolates the lower channel layer 120b from the upper channel layer 120a. In some embodiments, the lower channel layer 120b (e.g., the lower nanosheet) may be wider than the upper channel layer 120a (e.g., the upper nanosheet) in the second direction Y. For example, in some embodiments, the width of the lower channel layer 120b may be more than twice the width of the upper channel layer 120a. In some embodiments, the isolation region 130 may have the same width as the lower channel layer 120b in the second direction Y.

[0073] like Figure 2D As shown, the upper gate structure 170a (e.g., upper conductive gate 174a) and the lower gate structure 170b (e.g., lower conductive gate 174b) are electrically contacted (i.e., electrically connected) to each other and share an interface 174_I (made by...). Figure 2D (shown as dashed lines in the diagram). In some embodiments, a common gate voltage (i.e., a common gate signal) may be applied to both the upper conductive gate 174a and the lower conductive gate 174b (e.g., via the upper gate contact 148).

[0074] Return to reference Figure 1 As described above, the conventional integrated circuit device 1 includes a planar transistor 2 and a MOSCAP 3. For example, the MOSCAP 3 can operate in conjunction with the planar transistor 2 and can be used as a decoupling capacitor. Therefore, the MOSCAP 3 can improve the performance and reliability of the conventional integrated circuit device 1.

[0075] Similar to conventional integrated circuit device 1, it provides MOSCAP to interact with Figures 2A to 2DThe combined operation of the upper transistor Ta and the lower transistor Tb in the transistor stack 101 can be advantageous. For example, MOSCAP can help provide a stable voltage supply and / or filter out noise within the integrated circuit device 100. However, there are at least two challenges in implementing MOSCAP in the integrated circuit device 100. First, the upper transistor Ta and the lower transistor Tb of the integrated circuit device 100 do not include well regions, and therefore the conventional MOSCAP 3 of the integrated circuit device 1 (including the first MOSCAP 4 and the second MOSCAP 5) cannot be implemented in the integrated circuit device 100. Second, the upper gate structure 170a (e.g., the upper conductive gate 174a) of the upper transistor Ta and the lower gate structure 170b (e.g., the lower conductive gate 174b) of the lower transistor Tb are electrically connected to each other, and therefore the gate voltage (i.e., the gate signal) cannot be applied to the upper transistor Ta and the lower transistor Tb separately. As a result, since the upper transistor Ta and the lower transistor Tb have opposite conductivity types and thus operate in different regions of the accumulation region, depletion region, and inversion region in response to the common gate voltage, if the upper transistor Ta and the lower transistor Tb are reconfigured to operate as capacitors, only one of the upper transistor Ta and the lower transistor Tb will exhibit a high capacitance value in response to the gate voltage. Although the upper transistor Ta and the lower transistor Tb could be modified to have the same conductivity type, this would be conflicting because the integrated circuit device 100 would no longer be suitable for applications utilizing the CMOS structure of the upper transistor Ta and the lower transistor Tb.

[0076] Figure 3A This is a schematic block diagram of a MOSCAP integrated circuit device according to some embodiments. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements described above may be omitted.

[0077] Reference Figure 3A The integrated circuit device 100a includes a substrate 110 and a MOSCAP 102 on a first surface S1 (i.e., front side) of the substrate 110. The MOSCAP 102 includes a lower semiconductor device Sb having a stack of lower channel layer 120b and an upper semiconductor device Sa having a stack of upper channel layer 120a. In the third direction Z, the lower semiconductor device Sb is located between the upper semiconductor device Sa and the substrate 110. For example, the upper semiconductor device Sa may be stacked with the lower semiconductor device Sb in the third direction Z. The lower channel layer 120b is located between a pair of lower source / drain regions 140 (e.g., in the first direction X). The upper channel layer 120a is located between a pair of upper source / drain regions 150 (e.g., in the first direction X).

[0078] MOSCAP 102 may also include an isolation region 130' (such as an intermediate dielectric isolation (MDI) region). In some embodiments, the isolation region 130' may serve as a spacer between the upper semiconductor device Sa and the lower semiconductor device Sb. Therefore, the isolation region 130' may also be referred to herein as a "spacer". The lower semiconductor device Sb and the upper semiconductor device Sa may have opposite conductivity types. For example, the lower semiconductor device Sb may have a first conductivity type, while the upper semiconductor device Sa may have a second conductivity type.

[0079] To simplify the explanation, only one MOSCAP 102 is mentioned. Figure 3A The integrated circuit device 100a is shown in the figure. However, it will be understood that, according to some embodiments, the integrated circuit device 100a may include two, three, four or more MOSCAPs 102. In some embodiments, the integrated circuit device 100a includes at least one MOSCAP 102 and at least one transistor stack 101 (see Figure 100a). Figures 2A to 2D For example, transistor stack 101 and MOSCAP 102 may each be formed during the front-end process (FEOL) portion of device fabrication.

[0080] Figure 3B This is a schematic plan view of an integrated circuit device according to some embodiments. For the sake of simplicity, Figure 3B Only some components of the integrated circuit device 100a are shown. For example... Figure 3B As shown, the integrated circuit device 100a includes one or more gate structures 170' on the upper channel layer 120a of the upper semiconductor device Sa and the lower channel layer 120b of the lower semiconductor device Sb. The upper gate contact 148 and the lower gate contact 142 (made of...) Figure 3B (shown by the dashed box in the diagram) is electrically connected to the gate structure 170'. A first upper conductive plug 158a and a second upper conductive plug 158b are electrically connected to a pair of upper source / drain regions 150, respectively. A third upper conductive plug 156a and a fourth upper conductive plug 156b are electrically connected to a pair of lower source / drain regions 140, respectively. In some embodiments, the integrated circuit device 100a further includes a dummy gate structure 171. Line A-A' extends along the channel width of the upper channel layer 120a of the upper semiconductor device Sa in a first direction X. Line B-B' passes longitudinally (i.e., in length) through the gate structure 170' in a second direction Y. Line C-C' passes through the first upper source / drain region 150 of the pair of upper source / drain regions 150 and the first lower source / drain region 140 of the pair of lower source / drain regions 140 in the second direction Y. Line D-D' passes through the second upper source / drain region 150 in a pair of upper source / drain regions 150 and the second lower source / drain region 140 in a pair of lower source / drain regions 140 in the second direction Y.

[0081] Apart from Figure 2C The upper structure 146 can be reconfigured as a front-side metal oxide metal capacitor (MOMCAP) 104 and Figure 2C The BSPDN structure 144 can be reconfigured outside the dorsal MOMCAP 106, along... Figure 3B A cross-sectional view of integrated circuit device 100a taken by line A-A' and Figure 2C The sectional views shown are essentially the same. It will be understood that, except for the... Figure 2C In addition to the descriptions of the upper structure 146 and the BSPDN structure 144, refer to Figure 2C The description of integrated circuit device 100 generally applies to integrated circuit device 100a (unless the context explicitly indicates otherwise). Thus, for the sake of simplicity, details along... Figure 3B A cross-sectional view of integrated circuit device 100a taken by line A-A'.

[0082] Figure 3C It is along Figure 3B A schematic cross-sectional view of line B-B'. (Refer to...) Figure 3B and Figure 3C The gate structure 170' may include an upper gate structure 170a' and a lower gate structure 170b'. A pair of upper source / drain regions 150, an upper channel layer 120a, and an upper gate structure 170a' may partially form an upper semiconductor device Sa. A pair of lower source / drain regions 140, a lower channel layer 120b, and a lower gate structure 170b' may partially form a lower semiconductor device Sb. The upper semiconductor device Sa and the lower semiconductor device Sb include the MOSCAP 102 of the integrated circuit device 100a.

[0083] An upper gate structure 170a' may be located on the upper channel layer 120a of the upper semiconductor device Sa, and a lower gate structure 170b' may be located on the lower channel layer 120b of the lower semiconductor device Sb. The upper gate structure 170a' includes an upper conductive gate 174a'. The upper conductive gate 174a' may be located between the upper channel layers 120a (e.g., on a third-direction Z). The upper channel layers 120a may be stacked on a third-direction Z and spaced apart from each other. The lower gate structure 170b' includes a lower conductive gate 174b'. The lower conductive gate 174b' may be located between the lower channel layers 120b (e.g., on a third-direction Z). The lower channel layers 120b may be stacked on a third-direction Z and spaced apart from each other.

[0084] The upper conductive gate 174a' and the lower conductive gate 174b' may each comprise a metallic material (e.g., tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru)) and / or a semiconductor material. In some embodiments, the upper conductive gate 174a' and the lower conductive gate 174b' may each comprise a metal layer and one or more work function layers (e.g., TiN layer, TaN layer, TiAl layer, TiC layer, TiAlC layer, TiAlN layer, and / or WN layer). For example, one or more work function layers may be disposed between the metal layer and the gate insulating layer (not shown). In some embodiments, one or more work function layers may separate the metal layer from the gate insulating layer. In some embodiments, the upper conductive gate 174a' and the lower conductive gate 174b' may each comprise different metals or metallic materials. In other embodiments, the upper conductive gate 174a' and the lower conductive gate 174b' may comprise the same metallic material.

[0085] A lower gate structure 170b' may surround the lower channel layer 120b. For example, the lower gate structure 170b' (e.g., a lower conductive gate 174b') may be present on the upper surface, lower surface, and opposite side surface of each lower channel layer 120b. For simplicity, from... Figure 3C The view in the diagram omits the gate insulating layer of the lower gate structure 170b'. However, it will be understood that a gate insulating layer may be disposed between each lower channel layer 120b and the lower conductive gate 174b', and may separate the lower conductive gate 174b' from the lower channel layer 120b. In some embodiments, the gate insulating layer may be thinner than the isolation region 130' (e.g., in the third direction Z). The lower gate structure 170b' is located between a pair of lower source / drain regions 140 (e.g., in the first direction X).

[0086] An upper gate structure 170a' may surround an upper channel layer 120a. For example, the upper gate structure 170a' (e.g., an upper conductive gate 174a') may be present on the upper surface, lower surface, and opposite side surface of each upper channel layer 120a. For simplicity, from... Figure 3C The view in the diagram omits the gate insulating layer of the upper gate structure 170a'. However, it will be understood that the gate insulating layer may be disposed between each upper channel layer 120a and the upper conductive gate 174a', and may separate the upper conductive gate 174a' from the upper channel layer 120a. The upper gate structure 170a' is located between a pair of upper source / drain regions 150 (e.g., in the first direction X).

[0087] The isolation region 130' may be a spacer separating the lower channel layer 120b of the lower semiconductor device Sb from the upper channel layer 120a of the upper semiconductor device Sa. The isolation region 130' may be located between the upper gate structure 170a' and the lower gate structure 170b' (e.g., in the third direction Z). The isolation region 130' may include one or more isolation layers, for example, comprising one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, boron silicon carbonitride, and / or low-k materials). Although Figure 3C The isolation region 130' is shown as a single layer, but in some embodiments, the isolation region 130' may include multiple layers.

[0088] like Figure 3C As shown, isolation region 130' separates the lower gate structure 170b' from the upper gate structure 170a' (e.g., electrically). For example, isolation region 130' can insulate the lower conductive gate 174b' from the upper conductive gate 174a' (i.e., electrically isolate). Referring to the above... Figure 2D Unlike the described integrated circuit device 100, the upper gate structure 170a' (e.g., upper conductive gate 174a') and the lower gate structure 170b' (e.g., lower conductive gate 174b') are not electrically connected to each other. In some embodiments, the lower gate structure 170b' (e.g., lower conductive gate 174b') may be configured to receive a first voltage (i.e., a first gate signal), and the upper gate structure 170a' (e.g., upper conductive gate 174a') may be configured to receive a second voltage (i.e., a second gate signal) different from the first voltage. For example, the lower gate structure 170b' may be configured to receive the first voltage via a lower gate contact 142, and the upper gate structure 170a' may be configured to receive the second voltage via an upper gate contact 148. In some embodiments, the first voltage may be a drain voltage Vdd, and the second voltage may be a source voltage Vss, but this disclosure is not limited thereto.

[0089] The upper gate contact 148 extends into the first insulating layer 152 and is electrically connected to the upper gate structure 170a' (e.g., electrically connected to the upper conductive gate 174a'). For example, the upper gate contact 148 may be on the upper surface of the upper gate structure 170a' (e.g., on the upper surface of the upper conductive gate 174a'). The lower gate contact 142 extends into the substrate 110 and the intermediate layer 122 and is electrically connected to the lower gate structure 170b' (e.g., electrically connected to the lower conductive gate 174b'). For example, the lower gate contact 142 may be on the lower surface of the lower gate structure 170b' (e.g., on the lower surface of the lower conductive gate 174b'). The upper gate contact 148 and the lower gate contact 142 may each include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co and / or Ru.

[0090] MOSCAP 102 can operate as a voltage-controlled capacitor dependent on the capacitance between the lower conductive gate 174b' and the lower channel layer 120b of the lower semiconductor device Sb, and the capacitance between the upper conductive gate 174a' and the upper channel layer 120a of the upper semiconductor device Sa. More specifically, the lower conductive gate 174b' and the lower channel layer 120b can form a capacitor, while a gate insulating layer (not shown) serves as the dielectric between the lower conductive gate 174b' and the lower channel layer 120b. Similarly, the upper conductive gate 174a' and the upper channel layer 120a can form a capacitor, while a gate insulating layer (not shown) serves as the dielectric between the upper conductive gate 174a' and the upper channel layer 120a. In some embodiments, the lower conductive gate and upper conductive gate 174b', 174a' may comprise a metallic material, the gate insulating layer may comprise an oxide insulating material (e.g., silicon oxide, but embodiments of this disclosure are not limited thereto), and the lower channel layer and upper channel layer 120b, 120a may comprise a semiconductor material, hence the designation Metal-Oxide-Semiconductor Capacitor (MOSCAP). The capacitance of MOSCAP 102 may vary based on the corresponding voltages applied to the lower gate structure 170b' (e.g., applied to the lower conductive gate 174b') and the upper gate structure 170a' (e.g., applied to the upper conductive gate 174a').

[0091] like Figure 3C As shown, MOSCAP 102 is electrically connected between the front-side metal-oxide-semiconductor capacitor (MOMCAP) 104 and the back-side MOMCAP 106. For example, see the reference above. Figures 2B to 2D The described upper structure 146 and BSPDN structure 144 can be reconfigured to provide a front-side MOMCAP 104 and a back-side MOMCAP 106, respectively. The front-side MOMCAP 104 can be disposed on a first surface S1 (i.e., the front side) of the substrate 110. For example, the front-side MOMCAP 104 can be disposed on a MOSCAP 102 (e.g., on the upper surface of the MOSCAP 102). The back-side MOMCAP 106 can be disposed on a second surface S2 (i.e., the back side) of the substrate 110. For example, the back-side MOMCAP 106 can be disposed on the lower surface of the MOSCAP 102. In the third direction Z, the MOSCAP 102 is located between the front-side MOMCAP 104 and the back-side MOMCAP 106. For example, the MOSCAP 102, the front-side MOMCAP 104, and the back-side MOMCAP 106 can be stacked on top of each other in the third direction Z.

[0092] In some embodiments, including Figures 2B to 2DThe conductive and insulating elements in the upper structure 146 can be reconfigured to provide a front-side MOMCAP 104. For example, the front-side MOMCAP 104 can be formed in the vertical direction (e.g., the third direction Z) while utilizing (or reconfiguring) the existing (i.e., natural) elements of the upper structure 146 (e.g., by utilizing (or reconfiguring) the existing (i.e., natural) elements of the upper structure 146), and therefore the front-side MOMCAP 104 can also be referred to herein as a "front-side vertical natural capacitor (VNCAP)". For example, as a means of... Figures 2B to 2D As part of the manufacturing process of the integrated circuit device 100, the front-side MOMCAP 104 can be formed by reconfiguring the upper structure 146. In some embodiments, the conductive elements of the front-side MOMCAP 104 may be formed using, for example, a front-side signal pattern during the back-end process (BEOL) portion of device manufacturing.

[0093] In some embodiments, including Figures 2B to 2D The conductive and insulating elements in the BSPDN structure 144 can be reconfigured to provide a back-side MOMCAP 106. For example, the back-side MOMCAP 106 can be formed in the vertical direction (e.g., the third direction Z) while utilizing (or reconfiguring) the existing (i.e., natural) elements of the BSPDN structure 144, and therefore the back-side MOMCAP 106 can also be referred to herein as a "back-side vertical natural capacitor (VNCAP)". For example, as a means of... Figures 2B to 2D As part of the manufacturing process of the integrated circuit device 100, the back-side MOMCAP 106 can be formed by reconfiguring the BSPDN structure 144. In some embodiments, the conductive elements of the back-side MOMCAP 106 can be formed using, for example, a back-side signal pattern instead of a back-side power pattern during the back-end process (BEOL) of device fabrication. For example, the pitch of the conductive pattern for signal lines can be finer (i.e., smaller) than the pitch of the conductive pattern for power lines, thereby allowing the density of the back-side MOMCAP 106 to be increased by utilizing the finer pitch signal pattern. Therefore, the minimum width of the conductive elements included in the back-side MOMCAP 106, and the minimum spacing (i.e., minimum distance) between the conductive elements included in the back-side MOMCAP 106, can be reduced. In other embodiments, the conductive elements of the back-side MOMCAP 106 can be formed using, for example, a back-side power pattern.

[0094] like Figure 3CAs shown, the front MOMCAP 104 includes a lower front metallization pattern 160. The lower front metallization pattern 160 may include a first lower front metallization layer 160a and a second lower front metallization layer 160b. The first lower front metallization layer 160a may include a plurality of first lower front fingers 160a-1. The second lower front metallization layer 160b may include a plurality of second lower front fingers 160b-1. As used herein, the plurality of first lower front fingers 160a-1 and the plurality of second lower front fingers 160b-1 may be collectively referred to as a plurality of interleaved lower front fingers 160a-1, 160b-1. The front MOMCAP 104 may also include a second insulating layer 154 extending between the first lower front metallization layer 160a and the second lower front metallization layer 160b. The lower front metallization pattern 160 may include a metal layer or a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru. The second insulating layer 154 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the second insulating layer 154 is shown as a single layer, in some embodiments, the second insulating layer 154 may include multiple layers.

[0095] The first lower front metallization layer 160a (or the first lower front finger 160a-1) and the second lower front metallization layer 160b (or the second lower front finger 160b-1) can be considered as the conductive plate of the front MOMCAP 104, and the second insulating layer 154 is between the first lower front metallization layer 160a and the second lower front metallization layer 160b. Therefore, a capacitor can be formed between the first lower front metallization layer 160a and the second lower front metallization layer 160b of the front MOMCAP 104. In some embodiments, the first lower front metallization layer 160a comprises a metallic material, the second insulating layer 154 comprises an oxide insulating material (e.g., silicon oxide and / or aluminum oxide, but embodiments of this disclosure are not limited thereto), and the second lower front metallization layer 160b comprises a metallic material, hence the designation Metal Oxide Metal Capacitor (MOMCAP). Reference will be made below. Figure 3F and Figure 3G A more detailed description of the front MOMCAP 104.

[0096] MOSCAP 102 can be electrically connected to the front-side MOMCAP 104. For example, the upper gate structure 170a' (e.g., the upper conductive gate 174a') can be electrically connected to the front-side MOMCAP 104 via the upper gate contact 148. The first electrical path 191-1 (by...) Figure 3C(As shown in the dashed box in the diagram) can be disposed between the front-side MOMCAP 104 and MOSCAP 102. An upper gate structure 170a' (e.g., an upper conductive gate 174a') can be electrically connected to a second voltage along a first electrical path 191-1. For example, a second lower front-side metallization layer 160b can be configured to receive the second voltage. In some embodiments, the second voltage can be the source voltage Vss, but this disclosure is not limited thereto. For example, the first electrical path 191-1 can correspond to the output paths of MOSCAP 102, the front-side MOMCAP 104, and the back-side MOMCAP 106, but this disclosure is not limited thereto.

[0097] Still refer to Figure 3C The back-side MOMCAP 106 includes an upper back-side metallization pattern 180. The upper back-side metallization pattern 180 may include a first upper back-side metallization layer 180a and a second upper back-side metallization layer 180b. The first upper back-side metallization layer 180a may include a plurality of first upper back-side fingers 180a-1. The second upper back-side metallization layer 180b may include a plurality of second upper back-side fingers 180b-1. As used herein, the plurality of first upper back-side fingers 180a-1 and the plurality of second upper back-side fingers 180b-1 may be collectively referred to as a plurality of interleaved upper back-side fingers 180a-1, 180b-1. The back-side MOMCAP 106 may also include a third insulating layer 194 extending between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b. The upper back-side metallization pattern 180 may include a metal layer or a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru. The third insulating layer 194 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the third insulating layer 194 is shown as a single layer, in some embodiments, the third insulating layer 194 may include multiple layers.

[0098] The first upper back-side metallization layer 180a (or the first upper back-side finger 180a-1) and the second upper back-side metallization layer 180b (or the second upper back-side finger 180b-1) can be considered as the conductive plate of the back-side MOMCAP 106, and the third insulating layer 194 is between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b. Therefore, a capacitor can be formed between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b of the back-side MOMCAP 106. In some embodiments, the first upper back-side metallization layer 180a comprises a metallic material, the third insulating layer 194 comprises an oxide insulating material (e.g., silicon oxide and / or aluminum oxide, but embodiments of this disclosure are not limited thereto), and the second upper back-side metallization layer 180b comprises a metallic material, hence the designation Metal Oxide Metal Capacitor (MOMCAP). Reference will be made below. Figure 3H and Figure 3I A more detailed description of the dorsal MOMCAP 106.

[0099] MOSCAP 102 can be electrically connected to the back-side MOMCAP 106. For example, the lower gate structure 170b' (e.g., the lower conductive gate 174b') can be electrically connected to the back-side MOMCAP 106 via the lower gate contact 142. The second electrical path 192-1 (by...) Figure 3C (As shown in the dashed box in the diagram) can be disposed between the back-side MOMCAP 106 and MOSCAP 102. A lower gate structure 170b' (e.g., a lower conductive gate 174b') can be electrically connected to a first voltage along a second electrical path 192-1. For example, a first upper back-side metallization layer 180a can be configured to receive the first voltage. In some embodiments, the first voltage can be a drain voltage Vdd, but this disclosure is not limited thereto. For example, the second electrical path 192-1 can correspond to the input paths of MOSCAP 102, the front-side MOMCAP 104, and the back-side MOMCAP 106, but this disclosure is not limited thereto.

[0100] Figure 3D It is along Figure 3B A schematic cross-sectional view taken by line C-C'. Figure 3E It is along Figure 3B A schematic cross-sectional view taken along line D-D'. (Refer to...) Figure 3B , Figure 3D and Figure 3E A pair of upper source / drain regions 150 of MOSCAP 102 may be electrically connected to both the front-side MOSCAP 104 and the back-side MOSCAP 106. Similarly, a pair of lower source / drain regions 140 of MOSCAP 102 may be electrically connected to both the front-side MOSCAP 104 and the back-side MOSCAP 106. In some embodiments, the width of each of the pair of lower source / drain regions 140 in the second direction Y may be greater than the width of each of the pair of upper source / drain regions 150 in the second direction Y.

[0101] like Figure 3DAs shown, a first upper source / drain region 150 of a pair of upper source / drain regions 150 can be electrically connected to both the front MOMCAP 104 and the back MOMCAP 106 via a first upper source / drain contact structure 133a. The first upper source / drain contact structure 133a can extend into the substrate 110, the intermediate layer 122, and the first insulating layer 152. For example, the first upper source / drain contact structure 133a can extend (e.g., in the third direction Z) between the front MOMCAP 104 and the back MOMCAP 106. The first upper source / drain contact structure 133a may include a first upper conductive plug 158a, a first source / drain contact 108a, a first intermediate conductive plug 114a, and a first lower conductive plug 118a. The first source / drain contact 108a may contact the first upper source / drain region 150 of a pair of upper source / drain regions 150 (e.g., may be electrically contacted with the first upper source / drain region 150 of a pair of upper source / drain regions 150). For example, the first source / drain contact 108a may be on the upper surface of the first upper source / drain region 150 of the pair of upper source / drain regions 150 and contact the upper surface of the first upper source / drain region 150 of the pair of upper source / drain regions 150. The first lower conductive plug 118a is electrically connected between the back-side MOMCAP 106 and the first intermediate conductive plug 114a. For example, according to some embodiments, the first lower conductive plug 118a may contact the back-side MOMCAP 106 (e.g., may be electrically contacted with the back-side MOMCAP 106). The first intermediate conductive plug 114a is electrically connected between the first source / drain contact 108a and the first lower conductive plug 118a (e.g., in the third direction Z). The first upper conductive plug 158a is electrically connected between the front MOMCAP 104 and the first source / drain contact 108a. For example, according to some embodiments, the first upper conductive plug 158a may contact the front MOMCAP 104 (e.g., may be electrically contacted with the front MOMCAP 104). Therefore, the first upper source / drain contact structure 133a is electrically connected to the first upper source / drain region 150, the front MOMCAP 104, and the back MOMCAP 106 in a pair of upper source / drain regions 150. The first upper conductive plug 158a, the first source / drain contact 108a, the first intermediate conductive plug 114a, and the first lower conductive plug 118a may each include a metal layer or include a material containing, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0102] Third electrical path 192-2 (by Figure 3D(As shown in the dashed box) can be disposed between the front MOMCAP 104 and MOSCAP 102 and between the back MOMCAP 106 and MOSCAP 102. A first upper source / drain region 150 of a pair of upper source / drain regions 150 can be electrically connected to a first voltage along a third electrical path 192-2. For example, a first lower front metallization layer 160a of the front MOMCAP 104 and / or a first upper back metallization layer 180a of the back MOMCAP 106 can be configured to receive the first voltage. In some embodiments, the first voltage may be a drain voltage Vdd, but this disclosure is not limited thereto. For example, the third electrical path 192-2 may correspond to the input paths of MOSCAP 102, the front MOMCAP 104, and the back MOMCAP 106, but this disclosure is not limited thereto.

[0103] like Figure 3C and Figure 3D As shown, the lower gate structure 170b' (e.g., the lower conductive gate 174b') is electrically connected to the first upper back-side metallization layer 180a of the back-side MOMCAP 106 along the second electrical path 192-1, while the first upper source / drain region 150 of the pair of upper source / drain regions 150 is electrically connected to the first upper back-side metallization layer 180a of the back-side MOMCAP 106 along the third electrical path 192-2. Therefore, the lower gate structure 170b' (e.g., the lower conductive gate 174b') can be electrically connected to the first upper source / drain region 150 of the pair of upper source / drain regions 150. That is, the lower gate structure 170b' of MOSCAP 102 can be electrically shorted to the first upper source / drain region 150 of the pair of upper source / drain regions 150 of MOSCAP 102. In other words, MOSCAP 102 can be connected to the lower semiconductor device Sb (see...) Figure 3A The lower gate structure 170b' is electrically connected to the upper semiconductor device Sa (see Figure 3A The first source / drain region 150 of a pair of source / drain regions 150 is partially formed.

[0104] like Figure 3EAs shown, the second upper source / drain region 150 of a pair of upper source / drain regions 150 can be electrically connected to both the front MOMCAP 104 and the back MOMCAP 106 via a second upper source / drain contact structure 133b. The second upper source / drain contact structure 133b can extend into the substrate 110, the intermediate layer 122, and the first insulating layer 152. For example, the second upper source / drain contact structure 133b can extend (e.g., in the third direction Z) between the front MOMCAP 104 and the back MOMCAP 106. The second upper source / drain contact structure 133b may include a second upper conductive plug 158b, a second source / drain contact 108b, a second intermediate conductive plug 114b, and a second lower conductive plug 118b. The second source / drain contact 108b may contact the second upper source / drain region 150 of the pair of upper source / drain regions 150 (e.g., may be electrically contacted with the second upper source / drain region 150 of the pair of upper source / drain regions 150). For example, the second source / drain contact 108b may be on the upper surface of the second upper source / drain region 150 of the pair of upper source / drain regions 150 and contact the upper surface of the second upper source / drain region 150 of the pair of upper source / drain regions 150. The second lower conductive plug 118b is electrically connected between the back side MOMCAP 106 and the second intermediate conductive plug 114b. For example, according to some embodiments, the second lower conductive plug 118b may contact the back side MOMCAP 106 (e.g., may be electrically contacted with the back side MOMCAP 106). The second intermediate conductive plug 114b is electrically connected between the second source / drain contact 108b and the second lower conductive plug 118b (e.g., in the third direction Z). The second upper conductive plug 158b is electrically connected between the front MOMCAP 104 and the second source / drain contact 108b. For example, according to some embodiments, the second upper conductive plug 158b may contact the front MOMCAP 104 (e.g., may be electrically contacted with the front MOMCAP 104). Therefore, the second upper source / drain contact structure 133b is electrically connected to the second upper source / drain region 150, the front MOMCAP 104, and the back MOMCAP 106 in a pair of upper source / drain regions 150. The second upper conductive plug 158b, the second source / drain contact 108b, the second intermediate conductive plug 114b, and the second lower conductive plug 118b may each include a metal layer or include a material containing, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0105] Fourth electrical path 192-3 (by Figure 3E(As shown in the dashed box) can be disposed between the front MOMCAP 104 and MOSCAP 102 and between the back MOMCAP 106 and MOSCAP 102. A second upper source / drain region 150 of a pair of upper source / drain regions 150 can be electrically connected to a first voltage along a fourth electrical path 192-3. For example, the first lower front metallization layer 160a of the front MOMCAP 104 and / or the first upper back metallization layer 180a of the back MOMCAP 106 can be configured to receive the first voltage. In some embodiments, the first voltage may be a drain voltage Vdd, but this disclosure is not limited thereto. For example, the fourth electrical path 192-3 may correspond to the input paths of MOSCAP 102, the front MOMCAP 104, and the back MOMCAP 106, but this disclosure is not limited thereto.

[0106] like Figure 3C and Figure 3E As shown, the lower gate structure 170b' (e.g., the lower conductive gate 174b') is electrically connected to the first upper back-side metallization layer 180a of the back-side MOMCAP 106 along the second electrical path 192-1, while the second upper source / drain region 150 of the pair of upper source / drain regions 150 is electrically connected to the first upper back-side metallization layer 180a of the back-side MOMCAP 106 along the fourth electrical path 192-3. Therefore, the lower gate structure 170b' (e.g., the lower conductive gate 174b') can be electrically connected to the second upper source / drain region 150 of the pair of upper source / drain regions 150. That is, the lower gate structure 170b' of MOSCAP 102 can be electrically short-circuited to the second upper source / drain region 150 of the pair of upper source / drain regions 150 of MOSCAP 102. In other words, MOSCAP 102 can be connected to the lower semiconductor device Sb (see...) Figure 3A The lower gate structure 170b' is electrically connected to the upper semiconductor device Sa (see Figure 3A The second source / drain region 150 is partially formed in one of the pair of source / drain regions 150.

[0107] As described above, a pair of upper source / drain regions 150 of MOSCAP 102 can each be electrically connected to the lower gate structure 170b' of MOSCAP 102. In other words, a pair of upper source / drain regions 150 of the upper semiconductor device Sa included in MOSCAP 102 can each be electrically connected to the lower gate structure 170b' of the lower semiconductor device Sb included in MOSCAP 102.

[0108] like Figure 3DAs shown, a first lower source / drain region 140 of a pair of lower source / drain regions 140 can be electrically connected to both the front MOMCAP 104 and the back MOMCAP 106 via a first lower source / drain contact structure 134a. The first lower source / drain contact structure 134a can extend into the substrate 110, the intermediate layer 122, and the first insulating layer 152. For example, the first lower source / drain contact structure 134a can extend (e.g., in a third direction Z) between the front MOMCAP 104 and the back MOMCAP 106. The first lower source / drain contact structure 134a may include a third upper conductive plug 156a, a first conductive line 132a, a third intermediate conductive plug 116a, a third source / drain contact 112a, and a fourth source / drain contact 124a.

[0109] The third source / drain contact 112a may contact the first lower source / drain region 140 of the pair of lower source / drain regions 140 (e.g., may make electrical contact with the first lower source / drain region 140 of the pair of lower source / drain regions 140). For example, the third source / drain contact 112a may be on the upper surface of the first lower source / drain region 140 of the pair of lower source / drain regions 140 and may make contact with the upper surface of the first lower source / drain region 140 of the pair of lower source / drain regions 140. The fourth source / drain contact 124a may also contact the first lower source / drain region 140 of the pair of lower source / drain regions 140 (e.g., may make electrical contact with the first lower source / drain region 140 of the pair of lower source / drain regions 140). For example, the fourth source / drain contact 124a may be in contact with the lower surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140 and the lower surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140. The contact area between the first lower source / drain contact structure 134a and the first lower source / drain region 140 in the pair of lower source / drain regions 140 can be increased by providing both the third source / drain contact 112a and the fourth source / drain contact 124a. The third source / drain contact 112a is on the upper surface of the first lower source / drain region 140 in the pair of lower source / drain regions 140 and is electrically connected to the upper surface of the first lower source / drain region 140 in the pair of lower source / drain regions 140. The fourth source / drain contact 124a is on the lower surface of the first lower source / drain region 140 in the pair of lower source / drain regions 140 and is electrically connected to the lower surface of the first lower source / drain region 140 in the pair of lower source / drain regions 140. Therefore, the resistance between the first lower source / drain contact structure 134a and the first lower source / drain region 140 in a pair of lower source / drain regions 140 can be reduced, thereby reducing power loss during operation of the integrated circuit device 100a.

[0110] A fourth source / drain contact 124a is electrically connected between the back-side MOMCAP 106 and the first lower source / drain region 140 of a pair of lower source / drain regions 140. For example, according to some embodiments, the fourth source / drain contact 124a may contact the back-side MOMCAP 106 (e.g., may be electrically contacted with the back-side MOMCAP 106). A third upper conductive plug 156a is electrically connected between the front-side MOMCAP 104 and the first conductive line 132a. For example, according to some embodiments, the third upper conductive plug 156a may contact the front-side MOMCAP 104 (e.g., may be electrically contacted with the front-side MOMCAP 104). The first conductive line 132a and the third intermediate conductive plug 116a may be electrically connected between the third upper conductive plug 156a and the third source / drain contact 112a. For example, the first conductive line 132a may extend in a horizontal direction (e.g., the second direction Y), and the third intermediate conductive plug 116a may extend in a vertical direction (e.g., the third direction Z). The first lower source / drain contact structure 134a may be electrically connected to the first lower source / drain region 140, the front MOMCAP 104, and the back MOMCAP 106 in a pair of lower source / drain regions 140. The third upper conductive plug 156a, the first conductive line 132a, the third intermediate conductive plug 116a, the third source / drain contact 112a, and the fourth source / drain contact 124a may each include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0111] Fifth electrical path 191-2 (by Figure 3D (As shown in the dashed box) can be disposed between the front MOMCAP 104 and MOSCAP 102 and between the back MOMCAP 106 and MOSCAP 102. A first lower source / drain region 140 of a pair of lower source / drain regions 140 can be electrically connected to a second voltage along a fifth electrical path 191-2. For example, a second lower front metallization layer 160b of the front MOMCAP 104 and / or a second upper back metallization layer 180b of the back MOMCAP 106 can be configured to receive the second voltage. In some embodiments, the second voltage can be a source voltage Vss, but this disclosure is not limited thereto. For example, the fifth electrical path 191-2 can correspond to the output paths of MOSCAP 102, the front MOMCAP 104, and the back MOMCAP 106, but this disclosure is not limited thereto.

[0112] like Figure 3C and Figure 3DAs shown, the upper gate structure 170a' (e.g., the upper conductive gate 174a') is electrically connected to the second lower front metallization layer 160b of the front-side MOMCAP 104 along the first electrical path 191-1, while the first lower source / drain region 140 of the pair of lower source / drain regions 140 is electrically connected to the second lower front metallization layer 160b of the front-side MOMCAP 104 along the fifth electrical path 191-2. Therefore, the upper gate structure 170a' (e.g., the upper conductive gate 174a') can be electrically connected to the first lower source / drain region 140 of the pair of lower source / drain regions 140. That is, the upper gate structure 170a' of MOSCAP 102 can be electrically short-circuited to the first lower source / drain region 140 of the pair of lower source / drain regions 140 of MOSCAP 102. In other words, MOSCAP 102 can be connected to the upper semiconductor device Sa (see...) Figure 3A The upper gate structure 170a' is electrically connected to the lower semiconductor device Sb (see Figure 3A The first lower source / drain region 140 is partially formed in a pair of lower source / drain regions 140.

[0113] like Figure 3E As shown, the second lower source / drain region 140 of a pair of lower source / drain regions 140 can be electrically connected to both the front MOMCAP 104 and the back MOMCAP 106 via a second lower source / drain contact structure 134b. The second lower source / drain contact structure 134b can extend into the substrate 110, the intermediate layer 122, and the first insulating layer 152. For example, the second lower source / drain contact structure 134b can extend (e.g., in a third direction Z) between the front MOMCAP 104 and the back MOMCAP 106. The second lower source / drain contact structure 134b may include a fourth upper conductive plug 156b, a second conductive line 132b, a fourth intermediate conductive plug 116b, a fifth source / drain contact 112b, and a sixth source / drain contact 124b.

[0114] The fifth source / drain contact 112b may contact the second lower source / drain region 140 of the pair of lower source / drain regions 140 (e.g., may make electrical contact with the second lower source / drain region 140 of the pair of lower source / drain regions 140). For example, the fifth source / drain contact 112b may be on the upper surface of the second lower source / drain region 140 of the pair of lower source / drain regions 140 and may make contact with the upper surface of the second lower source / drain region 140 of the pair of lower source / drain regions 140. The sixth source / drain contact 124b may also contact the second lower source / drain region 140 of the pair of lower source / drain regions 140 (e.g., may make electrical contact with the second lower source / drain region 140 of the pair of lower source / drain regions 140). For example, the sixth source / drain contact 124b may be in contact with the lower surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140 and the lower surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140. The contact area between the second lower source / drain contact structure 134b and the second lower source / drain region 140 in the pair of lower source / drain regions 140 can be increased by providing both the fifth source / drain contact 112b and the sixth source / drain contact 124b. The fifth source / drain contact 112b is on the upper surface of the second lower source / drain region 140 in the pair of lower source / drain regions 140 and is electrically connected to the upper surface of the second lower source / drain region 140 in the pair of lower source / drain regions 140. The sixth source / drain contact 124b is on the lower surface of the second lower source / drain region 140 in the pair of lower source / drain regions 140 and is electrically connected to the lower surface of the second lower source / drain region 140 in the pair of lower source / drain regions 140. Therefore, the resistance between the second lower source / drain contact structure 134b and the second lower source / drain region in the pair of lower source / drain regions 140 can be reduced, thereby reducing power loss during operation of the integrated circuit device 100a.

[0115] A sixth source / drain contact 124b is electrically connected between the back-side MOMCAP 106 and the second lower source / drain region 140 of a pair of lower source / drain regions 140. For example, according to some embodiments, the sixth source / drain contact 124b may contact the back-side MOMCAP 106 (e.g., may be electrically contacted with the back-side MOMCAP 106). A fourth upper conductive plug 156b is electrically connected between the front-side MOMCAP 104 and the second conductive line 132b. For example, according to some embodiments, the fourth upper conductive plug 156b may contact the front-side MOMCAP 104 (e.g., may be electrically contacted with the front-side MOMCAP 104). The second conductive line 132b and the fourth intermediate conductive plug 116b may be electrically connected between the fourth upper conductive plug 156b and the fifth source / drain contact 112b. For example, the second conductive line 132b may extend in a horizontal direction (e.g., the second direction Y), and the fourth intermediate conductive plug 116b may extend in a vertical direction (e.g., the third direction Z). The second lower source / drain contact structure 134b may be electrically connected to the second lower source / drain region 140, the front MOMCAP 104, and the back MOMCAP 106 in a pair of lower source / drain regions 140. The fourth upper conductive plug 156b, the second conductive line 132b, the fourth intermediate conductive plug 116b, the fifth source / drain contact 112b, and the sixth source / drain contact 124b may each include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0116] Sixth electrical path 191-3 (by Figure 3E (As shown in the dashed box) can be disposed between the front MOMCAP 104 and MOSCAP 102 and between the back MOMCAP 106 and MOSCAP 102. A second lower source / drain region 140 of a pair of lower source / drain regions 140 can be electrically connected to a second voltage along a sixth electrical path 191-3. For example, the second lower front metallization layer 160b of the front MOMCAP 104 and / or the second upper back metallization layer 180b of the back MOMCAP 106 can be configured to receive the second voltage. In some embodiments, the second voltage can be the source voltage Vss, but this disclosure is not limited thereto. For example, the sixth electrical path 191-3 can correspond to the output paths of MOSCAP 102, the front MOMCAP 104, and the back MOMCAP 106, but this disclosure is not limited thereto.

[0117] like Figure 3C and Figure 3EAs shown, the upper gate structure 170a' (e.g., the upper conductive gate 174a') is electrically connected to the second lower front metallization layer 160b of the front-side MOMCAP 104 along the first electrical path 191-1, while the second lower source / drain region 140 of the pair of lower source / drain regions 140 is electrically connected to the second lower front metallization layer 160b of the front-side MOMCAP 104 along the sixth electrical path 191-3. Therefore, the upper gate structure 170a' (e.g., the upper conductive gate 174a') can be electrically connected to the second lower source / drain region 140 of the pair of lower source / drain regions 140. That is, the upper gate structure 170a' of MOSCAP 102 can be electrically short-circuited to the second lower source / drain region 140 of the pair of lower source / drain regions 140 of MOSCAP 102. In other words, MOSCAP 102 can be connected to the upper semiconductor device Sa (see...) Figure 3A The upper gate structure 170a' is electrically connected to the lower semiconductor device Sb (see Figure 3A The second lower source / drain region 140 is partially formed in a pair of lower source / drain regions 140.

[0118] As described above, a pair of lower source / drain regions 140 of MOSCAP 102 can each be electrically connected to the upper gate structure 170a' of MOSCAP 102. In other words, a pair of lower source / drain regions 140 of the lower semiconductor device Sb included in MOSCAP 102 can each be electrically connected to the upper gate structure 170a' of the upper semiconductor device Sa included in MOSCAP 102.

[0119] Figure 3F This is a schematic plan view of the front MOMCAP according to some embodiments. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements described above may be omitted.

[0120] Reference Figure 3F The front-side MOMCAP 104 includes a lower front-side metallization pattern 160. The lower front-side metallization pattern 160 may include a first lower front-side metallization layer 160a and a second lower front-side metallization layer 160b. A second insulating layer 154 may extend between the first lower front-side metallization layer 160a and the second lower front-side metallization layer 160b. For example, the second insulating layer 154 may insulate (i.e., isolate) the first lower front-side metallization layer 160a from the second lower front-side metallization layer 160b. In some embodiments, the first lower front-side metallization layer 160a may be configured to receive a first voltage (e.g., drain voltage Vdd), and the second lower front-side metallization layer 160b may be configured to receive a second voltage (e.g., source voltage Vss).

[0121] The first lower front metallization layer 160a may include a plurality of first lower front fingers 160a-1 and a first lower front conductive plate 160a-2. The first lower front fingers 160a-1 may extend from the first lower front conductive plate 160a-2 in a first direction X (e.g., may extend longitudinally from the first lower front conductive plate 160a-2 in the first direction X). For example, the first lower front conductive plate 160a-2 may serve as a common electrical path for the first lower front fingers 160a-1 and may share a first voltage with the first lower front fingers 160a-1. In some embodiments, the longest dimension of the first lower front fingers 160a-1 may be in the first direction X.

[0122] The second lower front metallization layer 160b may include a plurality of second lower front fingers 160b-1 and a second lower front conductive plate 160b-2. The second lower front fingers 160b-1 may extend from the second lower front conductive plate 160b-2 in a first direction X (e.g., opposite to the first lower front fingers 160a-1), for example, longitudinally extending from the second lower front conductive plate 160b-2 in the first direction X. For example, the second lower front conductive plate 160b-2 may serve as a common electrical path for the second lower front fingers 160b-1 and may share a second voltage with the second lower front fingers 160b-1. In some embodiments, the longest dimension of the second lower front fingers 160b-1 may be in the first direction X.

[0123] The first lower anterior finger 160a-1 and the second lower anterior finger 160b-1 may be interlocked (e.g., similar to an interlocking structure (such as the fingers of two hands clasped together)), and therefore the first lower anterior finger 160a-1 and the second lower anterior finger 160b-1 may be collectively referred to as interlocked lower anterior fingers 160a-1, 160b-1. Figure 3F As shown, the second insulating layer 154 extends between adjacent lower front fingers in the staggered lower front fingers 160a-1, 160b-1, and thus the capacitance (by...) Figure 3F(The capacitor symbol shown in the diagram) can be formed between adjacent lower front fingers of the staggered lower front fingers 160a-1, 160b-1 (e.g., in the second direction Y). The staggered lower front fingers 160a-1, 160b-1 can extend in the first direction X and can be spaced apart from each other in the second direction Y. The first lower front finger 160a-1 and the second lower front finger 160b-1 may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first lower front finger 160a-1 and the second lower front finger 160b-1), and may instead be capacitively coupled to each other only. In other words, the first lower front metallization layer 160a and the second lower front metallization layer 160b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first lower front metallization layer 160a and the second lower front metallization layer 160b), and may instead be capacitively coupled to each other only. Although Figure 3F Eleven staggered lower anterior fingers 160a-1, 160b-1 are shown, but this disclosure is not limited thereto. In other embodiments, the anterior MOMCAP 104 may include more than eleven staggered lower anterior fingers 160a-1, 160b-1 or fewer than eleven staggered lower anterior fingers 160a-1, 160b-1.

[0124] In some embodiments, a minimum width (e.g., according to predefined design rules) may be used for the lower front metallization pattern 160 to increase the capacitance density of the front MOMCAP 104 (i.e., increase the amount of capacitance per unit area). For example, each of the staggered lower front fingers 160a-1, 160b-1 may have a width of less than 100 nanometers (nm) in the second direction Y. In some embodiments, a minimum spacing (e.g., according to predefined design rules) between the first lower front metallization layer 160a and the second lower front metallization layer 160b of the front MOMCAP 104 may be used to increase the capacitance density of the front MOMCAP 104. For example, adjacent lower anterior fingers in the staggered lower anterior fingers 160a-1 and 160b-1 (e.g., a corresponding first lower anterior finger in the first lower anterior finger 160a-1 adjacent to a corresponding second lower anterior finger in the second lower anterior finger 160b-1) may be spaced apart from each other by less than 100 nanometers (nm) in the second direction Y. In other words, the distance between adjacent lower anterior fingers in the staggered lower anterior fingers 160a-1 and 160b-1 in the second direction Y may be less than 100 nanometers (nm).

[0125] Figure 3G According to some embodiments, including Figure 3F A schematic plan view of the front-side MOMCAP integrated circuit device. For simplicity, Figure 3GOnly some components of the integrated circuit device 100a are shown. To further illustrate exemplary embodiments of this disclosure, in... Figure 3G The plan view shows the respective with Figure 3C , Figure 3D and Figure 3E The sectional views correspond to lines B-B', C-C', and D-D'. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements may be omitted.

[0126] like Figure 3G As shown, the integrated circuit device 100a may include a plurality of unit cells 100a-1 to 100a-4. For example, the first unit cell 100a-1 of the integrated circuit device 100a may correspond to Figure 3B The plan view of the integrated circuit device 100a shown is illustrated. Although... Figure 3G Four unit cells 100a-1 to 100a-4 are shown, but this disclosure is not limited thereto. In other embodiments, the integrated circuit device 100a may include more than four unit cells or fewer than four unit cells.

[0127] like Figure 3GAs shown, the staggered lower front fingers 160a-1, 160b-1 may extend in a first direction X (e.g., may extend longitudinally in the first direction X), and the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') may extend in a second direction Y (e.g., may extend longitudinally in the second direction Y). For example, the longest dimension of the staggered lower front fingers 160a-1, 160b-1 may be in the first direction X, and the longest dimension of the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') may be in the second direction Y, but the embodiments of this disclosure are not limited thereto. For example, staggered lower front fingers 160a-1 and 160b-1 may extend perpendicularly to the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170'). The staggered lower front fingers 160a-1 and 160b-1 may be stacked on the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') in the third direction Z. The staggered lower front fingers 160a-1 and 160b-1 may also be stacked on the first upper conductive plug 158a, the second upper conductive plug 158b, the third upper conductive plug 156a, the fourth upper conductive plug 156b, the lower gate contact 142, and the upper gate contact 148 in the third direction Z. For example, the first lower front finger 160a-1 can be connected in the third direction Z to the first upper conductive plug 158a, the second upper conductive plug 158b, and the lower gate contact 142 (made by...). Figure 3G (shown in the dashed box) are stacked, and the second lower front finger 160b-1 may be stacked with the third upper conductive plug 156a, the fourth upper conductive plug 156b and the upper gate contact 148 in the third direction Z.

[0128] Figure 3H This is a schematic plan view of the rear-side MOMCAP according to some embodiments. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements described above may be omitted.

[0129] Reference Figure 3HThe back-side MOMCAP 106 includes an upper back-side metallization pattern 180. The upper back-side metallization pattern 180 may include a first upper back-side metallization layer 180a and a second upper back-side metallization layer 180b. A third insulating layer 194 may extend between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b. For example, the third insulating layer 194 may insulate (i.e., isolate) the first upper back-side metallization layer 180a from the second upper back-side metallization layer 180b. In some embodiments, the first upper back-side metallization layer 180a of the back-side MOMCAP 106 may be configured to receive a first voltage (e.g., drain voltage Vdd), and the second upper back-side metallization layer 180b may be configured to receive a second voltage (e.g., source voltage Vss).

[0130] The first upper back-side metallization layer 180a may include a plurality of first upper back-side fingers 180a-1 and a first upper back-side conductive plate 180a-2. The first upper back-side fingers 180a-1 may extend from the first upper back-side conductive plate 180a-2 in a first direction X (e.g., may extend longitudinally from the first upper back-side conductive plate 180a-2 in the first direction X). For example, the first upper back-side conductive plate 180a-2 may serve as a common electrical path for the first upper back-side fingers 180a-1 and may share a first voltage with the first upper back-side fingers 180a-1. In some embodiments, the longest dimension of the first upper back-side fingers 180a-1 may be in the first direction X.

[0131] The second upper back-side metallization layer 180b may include a plurality of second upper back-side fingers 180b-1 and a second upper back-side conductive plate 180b-2. The second upper back-side fingers 180b-1 may extend from the second upper back-side conductive plate 180b-2 in a first direction X (e.g., opposite to the first upper back-side fingers 180a-1), for example, by extending longitudinally from the second upper back-side conductive plate 180b-2 in the first direction X. For example, the second upper back-side conductive plate 180b-2 may serve as a common electrical path for the second upper back-side fingers 180b-1 and may share a second voltage with the second upper back-side fingers 180b-1. In some embodiments, the longest dimension of the second upper back-side fingers 180b-1 may be in the first direction X.

[0132] The first upper dorsal finger 180a-1 and the second upper dorsal finger 180b-1 may be interlocked (e.g., similar to an interlocking structure (such as the fingers of two hands clasped together)), and therefore the first upper dorsal finger 180a-1 and the second upper dorsal finger 180b-1 may be collectively referred to as interlocked upper dorsal fingers 180a-1, 180b-1. Figure 3H As shown, the third insulating layer 194 extends between adjacent upper back-side fingers in the staggered upper back-side fingers 180a-1, 180b-1, and thus the capacitance (by...) Figure 3H (The capacitor symbol shown in the diagram) can be formed between adjacent upper back-side fingers of the staggered upper back-side fingers 180a-1, 180b-1 (e.g., in the second direction Y). The staggered upper back-side fingers 180a-1, 180b-1 can extend in the first direction X and can be spaced apart from each other in the second direction Y. The first upper back-side fingers 180a-1 and the second upper back-side fingers 180b-1 may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first upper back-side fingers 180a-1 and the second upper back-side fingers 180b-1), and may instead be capacitively coupled to each other only. In other words, the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b), and may instead be capacitively coupled to each other only. Although Figure 3H Eleven staggered upper dorsal fingers 180a-1, 180b-1 are shown, but this disclosure is not limited thereto. In other embodiments, the dorsal MOMCAP 106 may include more than eleven staggered upper dorsal fingers 180a-1, 180b-1 or fewer than eleven staggered upper dorsal fingers 180a-1, 180b-1.

[0133] In some embodiments, a minimum width (e.g., according to predefined design rules) may be used for the upper back-side metallization pattern 180 to increase the capacitance density of the back-side MOMCAP 106 (i.e., to increase the amount of capacitance per unit area). For example, each of the staggered upper back-side fingers 180a-1, 180b-1 may have a width of less than 100 nanometers (nm) in the second direction Y. In some embodiments, a minimum spacing (e.g., according to predefined design rules) between the first upper back-side metallization layer 180a and the second upper back-side metallization layer 180b of the back-side MOMCAP 106 may be used to increase the capacitance density of the back-side MOMCAP 106. For example, adjacent upper back-side fingers in the staggered upper back-side fingers 180a-1 and 180b-1 (e.g., a corresponding first upper back-side finger 180a-1 adjacent to a corresponding second upper back-side finger in the second upper back-side finger 180b-1) may be spaced apart from each other by less than 100 nanometers (nm) in the second direction Y. In other words, the distance between adjacent upper back-side fingers in the staggered upper back-side fingers 180a-1 and 180b-1 in the second direction Y may be less than 100 nanometers (nm).

[0134] Reference Figure 3F and 3HIn some embodiments, the width (e.g., in the second direction Y) of the staggered upper dorsal fingers 180a-1, 180b-1 of the dorsal MOMCAP 106 may be substantially equal to the width (e.g., in the second direction Y) of the staggered lower anterior fingers 160a-1, 160b-1 of the anterior MOMCAP 104. In some embodiments, the spacing or distance (e.g., in the second direction Y) between adjacent upper dorsal fingers of the staggered upper dorsal fingers 180a-1, 180b-1 of the dorsal MOMCAP 106 may be substantially equal to the spacing or distance (e.g., in the second direction Y) between adjacent lower anterior fingers of the staggered lower anterior fingers 160a-1, 160b-1 of the anterior MOMCAP 104.

[0135] Figure 3I According to some embodiments, including Figure 3H A schematic plan view of the integrated circuit device on the back side of the MOMCAP. For simplicity, Figure 3I Only some components of the integrated circuit device 100a are shown. To further illustrate exemplary embodiments of this disclosure, in... Figure 3I The plan view shows the respective with Figure 3C , Figure 3D and Figure 3E The sectional views correspond to lines B-B', C-C', and D-D'. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements may be omitted.

[0136] like Figure 3I As shown, the integrated circuit device 100a may include a plurality of unit cells 100a-1 to 100a-4. For example, the first unit cell 100a-1 of the integrated circuit device 100a may correspond to Figure 3B The plan view of the integrated circuit device 100a shown is illustrated. Although... Figure 3I Four unit cells 100a-1 to 100a-4 are shown, but this disclosure is not limited thereto. In other embodiments, the integrated circuit device 100a may include more than four unit cells or fewer than four unit cells.

[0137] like Figure 3IAs shown, the staggered upper back-side fingers 180a-1, 180b-1 may extend in a first direction X (e.g., may extend longitudinally in the first direction X), and the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') may extend in a second direction Y (e.g., may extend longitudinally in the second direction Y). For example, the longest dimension of the staggered upper back-side fingers 180a-1, 180b-1 may be in the first direction X, and the longest dimension of the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') may be in the second direction Y, but the embodiments of this disclosure are not limited thereto. For example, staggered upper back-side fingers 180a-1 and 180b-1 may extend perpendicularly to the gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170'). The gate structure 170' (and the upper gate structure 170a' and lower gate structure 170b' included in the gate structure 170') may be stacked with the staggered upper back-side fingers 180a-1 and 180b-1 in the third direction Z. The first upper conductive plug 158a, the second upper conductive plug 158b, the third upper conductive plug 156a, the fourth upper conductive plug 156b, the lower gate contact 142, and the upper gate contact 148 may also be stacked with the staggered upper back-side fingers 180a-1 and 180b-1 in the third direction Z. For example, the first upper conductive plug 158a, the second upper conductive plug 158b, and the lower gate contact 142 (made of...) Figure 3I (shown in dashed box) can be stacked on the third direction Z with the first upper back side finger 180a-1, and the third upper conductive plug 156a, the fourth upper conductive plug 156b and the upper gate contact 148 can be stacked on the third direction Z with the second upper back side finger 180b-1.

[0138] Figure 3J According to some embodiments Figures 3A to 3E A schematic circuit diagram of MOSCAP. Figure 3K According to some embodiments Figures 3A to 3E A schematic circuit diagram of an integrated circuit device.

[0139] like Figure 3J As shown, MOSCAP 102 includes a lower semiconductor device Sb and an upper semiconductor device Sa. The lower gate structure 170b' of the lower semiconductor device Sb is electrically connected (i.e., electrically short-circuited) to both of a pair of upper source / drain regions 150 of the upper semiconductor device Sa. The lower gate structure 170b' can be configured to receive a first voltage. In some embodiments, the first voltage is as follows: Figure 3JThe drain voltage Vdd is shown in the figure, but this disclosure is not limited thereto. A pair of lower source / drain regions 140 of the lower semiconductor device Sb can be configured to receive a second voltage. In some embodiments, the second voltage is as follows: Figure 3J The source voltage Vss is shown in the figure, but this disclosure is not limited thereto. For example, as Figure 3J As shown, the source voltage Vss may have a value of zero volts (0V), but embodiments of this disclosure are not limited thereto. Therefore, the gate-to-source voltage Vgs applied to the lower semiconductor device Sb may correspond to a first voltage (i.e., +Vdd). The second voltage differs from the first voltage.

[0140] The upper gate structure 170a' of the upper semiconductor device Sa is electrically connected (i.e., electrically short-circuited) to both of the lower source / drain regions 140 of the lower semiconductor device Sb. The upper gate structure 170a' can be configured to receive a second voltage (e.g., Vss). Figure 3J As shown, the source voltage Vss may have a value of zero volts (0V), but embodiments of this disclosure are not limited thereto. A pair of upper source / drain regions 150 of the upper semiconductor device Sa are configured to receive a first voltage (e.g., Vdd). Therefore, the gate-to-source voltage Vgs applied to the upper semiconductor device Sa may correspond to the first voltage with reversed polarity (i.e., -Vdd). In other words, the gate-to-source voltage Vgs applied to the upper semiconductor device Sa may correspond to the negative version of the first voltage (i.e., -Vdd).

[0141] like Figure 3K As shown, MOSCAP 102 is electrically connected between the front-side MOMCAP 104 and the back-side MOMCAP 106. In other words, MOSCAP 102, the front-side MOMCAP 104, and the back-side MOMCAP 106 can be electrically connected to each other. For example, MOSCAP 102 can be electrically connected in parallel with the front-side MOMCAP 104 and the back-side MOMCAP 106, but the embodiments of this disclosure are not limited thereto. For example, a first voltage (e.g., drain voltage Vdd) and a second voltage (e.g., source voltage Vss) can be electrically connected to a first node 103 and a second node 105, respectively. In some embodiments, the first node 103 and the second node 105 can correspond to the input path and output path of MOSCAP 102, the front-side MOMCAP 104, and the back-side MOMCAP 106, respectively, but the disclosure is not limited thereto. Although Figure 3J and Figure 3K The illustration shows that the upper semiconductor device Sa is a p-type device and the lower semiconductor device Sb is an n-type device; however, the embodiments of this disclosure are not limited thereto. In other embodiments, the upper semiconductor device Sa may be an n-type device and the lower semiconductor device Sb may be a p-type device. In this case, Figure 3J and3K The first voltage (e.g., Vdd) and the second voltage (e.g., Vss) shown are invertible. That is, the upper gate structure 170a' and a pair of lower source / drain regions 140 can be configured to receive the first voltage (e.g., Vdd), and the lower gate structure 170b' and a pair of upper source / drain regions 150 can be configured to receive the second voltage (e.g., Vss).

[0142] Return to reference Figures 3A to 3E The integrated circuit device 100a may include at least three capacitors: MOSCAP 102, front-side MOMCAP 104, and back-side MOMCAP 106. MOSCAP 102, front-side MOMCAP 104, and back-side MOMCAP 106 can be modified for forming three-dimensional (3D) stacked transistors (e.g., see...). Figures 2A to 2D The existing architecture of the transistor stack 101 is configured such that MOSCAP 102, front-side MOMCAP 104, and back-side MOMCAP 106 do not adversely affect the integration density of the integrated circuit device 100a and can be seamlessly implemented in the integrated circuit device 100a. As a result, the integrated circuit device 100a may include multiple high-density capacitors. For example, these capacitors may be used as decoupling capacitors. For example, the integrated circuit device according to some embodiments of this disclosure may include MOSCAP 102, front-side MOMCAP 104, and back-side MOMCAP 106, as well as the upper transistor Ta and lower transistor Tb of the transistor stack 101 (see Figures 2A to 2D For example, MOSCAP 102, front-side MOMCAP 104, and back-side MOMCAP 106 can operate in conjunction with the upper transistor Ta and lower transistor Tb of the transistor stack 101 to help provide a stable voltage supply and / or filter out noise within the integrated circuit device, thereby improving the performance and reliability of the integrated circuit device.

[0143] Figure 4 This illustrates some embodiments. Figures 3A to 3E The graph of the CV curve of MOSCAP. Specifically, Figure 4 The relationship between the capacitance (C) of MOSCAP 102 and the gate-to-source voltage (Vgs) applied to MOSCAP 102 is shown. Figure 4 The vertical axis in the figure corresponds to the capacitance (C) of the MOSCAP 102, and Figure 4 The horizontal axis in the figure corresponds to the gate-to-source voltage (Vgs) applied to the MOSCAP 102.

[0144] like Figure 4As shown, the lower semiconductor device Sb and the upper semiconductor device Sa are configured to provide MOSCAP 102. The lower semiconductor device Sb can operate in an accumulation region, a depletion region, or an inversion region based on the gate-to-source voltage (Vgs) applied to the lower semiconductor device Sb. Similarly, the upper semiconductor device Sa can operate in an accumulation region, a depletion region, or an inversion region based on the gate-to-source voltage (Vgs) applied to the upper semiconductor device Sa.

[0145] Reference Figure 3J and Figure 4 The gate-to-source voltage (Vgs) of the lower semiconductor device Sb is a function of a first voltage (e.g., Vdd) applied to the lower gate structure 170b' of the lower semiconductor device Sb and a second voltage (e.g., Vss) applied to a pair of lower source / drain regions 140 of the lower semiconductor device Sb. For example, the gate-to-source voltage (Vgs) of the lower semiconductor device Sb corresponds to the voltage difference between the first voltage and the second voltage. Therefore, the capacitance value of the lower semiconductor device Sb can vary based on the first voltage and the second voltage. The gate-to-source voltage (Vgs) of the upper semiconductor device Sa is a function of a second voltage (e.g., Vss) applied to the upper gate structure 170a' of the upper semiconductor device Sa and a first voltage (e.g., Vdd) applied to a pair of upper source / drain regions 150 of the upper semiconductor device Sa. For example, the gate-to-source voltage (Vgs) of the upper semiconductor device Sa corresponds to the voltage difference between the second voltage and the first voltage. Therefore, the capacitance value of the upper semiconductor device Sa can vary based on the first voltage and the second voltage.

[0146] By electrically connecting the lower gate structure 170b' of the lower semiconductor device Sb to both of the pair of upper source / drain regions 150 of the upper semiconductor device Sa, and electrically connecting the upper gate structure 170a' of the upper semiconductor device Sa to both of the pair of lower source / drain regions 140 of the lower semiconductor device Sb, MOSCAP 102 can be configured to have a maximum capacitance value when both the lower semiconductor device Sb and the upper semiconductor device Sa are operating in the inversion region. As used herein, "maximum capacitance value of MOSCAP" (or similar language) means the highest capacitance that MOSCAP 102 is configured to provide during normal operation of the integrated circuit device 100a. Furthermore, both the lower semiconductor device Sb and the upper semiconductor device Sa can be configured to operate simultaneously in the inversion region by electrically separating (i.e., electrically isolating) the lower gate structure 170b' of the lower semiconductor device Sb from the upper gate structure 170a' of the upper semiconductor device Sa.

[0147] like Figure 3J and Figure 4As shown, when the gate-to-source voltage (Vgs) applied to the lower semiconductor device Sb causes it to operate in the inversion region, the lower semiconductor device Sb can have a maximum capacitance value of 401 (as shown in the diagram). Figure 4 (The dashed box in the diagram is shown). In other words, when the first and second voltages (e.g., Vdd and Vss) cause the lower semiconductor device Sb to operate in the inversion region, the lower semiconductor device Sb may have (i.e., may exhibit) a maximum capacitance value of 401. When the first and second voltages cause the lower semiconductor device Sb to operate in the depletion region, the capacitance value of the lower semiconductor device Sb may decrease, and when the first and second voltages cause the lower semiconductor device Sb to operate in the accumulation region, the capacitance value of the lower semiconductor device Sb may decrease further. Therefore, the capacitance value of the lower semiconductor device Sb may vary based on the gate-to-source voltage (Vgs) applied to the lower semiconductor device Sb.

[0148] Still refer to Figure 3J and Figure 4 When the gate-to-source voltage (Vgs) applied to the upper semiconductor device Sa causes it to operate in the inversion region, the upper semiconductor device Sa can have a maximum capacitance value of 402 (from...). Figure 4 (The dashed box in the diagram shows this). In other words, when the first and second voltages (e.g., Vdd and Vss) cause the upper semiconductor device Sa to operate in the inversion region, the upper semiconductor device Sa may have (i.e., may exhibit) a maximum capacitance value of 402. When the first and second voltages cause the upper semiconductor device Sa to operate in the depletion region, the capacitance value of the upper semiconductor device Sa may decrease, and when the first and second voltages cause the upper semiconductor device Sa to operate in the accumulation region, the capacitance value of the upper semiconductor device Sa may decrease further. Therefore, the capacitance value of the upper semiconductor device Sa may vary based on the gate-to-source voltage (Vgs) applied to the upper semiconductor device Sa.

[0149] As described above, when the first voltage (e.g., Vdd) and the second voltage (e.g., Vss) cause both the lower semiconductor device Sb and the upper semiconductor device Sa to operate in the inversion region, MOSCAP 102 is configured to have the maximum capacitance value (e.g., 401+402). This is similar to the conventional integrated circuit device 1 where MOSCAP 3 can be configured to have the maximum capacitance value when both the first MOSCAP 4 and the second MOSCAP 5 operate in the accumulation region (see...). Figure 1 Unlike MOSCAP 3, MOSCAP 102 according to embodiments of the present disclosure can have a maximum capacitance value when both the current semiconductor device Sb and the upper semiconductor device Sa are operating in the inversion region. As described above, the capacitance value can be further increased by electrically connecting MOSCAP 102 to the front-side MOMCAP 104 and the back-side MOMCAP 106.

[0150] although Figure 3J and Figure 4 The illustration shows that the upper semiconductor device Sa is a p-type device and the lower semiconductor device Sb is an n-type device, but the embodiments of this disclosure are not limited thereto. In other embodiments, the upper semiconductor device Sa can be an n-type device and the lower semiconductor device Sb can be a p-type device. In this case, the CV curves of the upper semiconductor device Sa and the lower semiconductor device Sb can be obtained from... Figure 4 The CV curve shown is reversed.

[0151] Figure 5A This is a schematic plan view of the front MOMCAP according to some further embodiments. Figure 5B This is a schematic plan view of the back side of the MOMCAP according to some further embodiments. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements described above may be omitted.

[0152] Reference Figure 5A The front MOMCAP 104' may include a lower front metallization pattern 160. The front MOMCAP 104' may also include an upper front metallization pattern 162 (e.g., on a third-direction Z) on the lower front metallization pattern 160 (e.g., stacked on the lower front metallization pattern 160), and a front insulating layer 164 (e.g., on a third-direction Z) between the lower front metallization pattern 160 and the upper front metallization pattern 162. The upper front metallization pattern 162 may include a first upper front metallization layer 162a and a second upper front metallization layer 162b. The upper front metallization pattern 162 may include a metal layer or a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru. The front insulating layer 164 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the front insulating layer 164 is shown as a single layer, in some embodiments, the front insulating layer 164 may include multiple layers.

[0153] The front-side MOMCAP 104' may also include a fourth insulating layer 168 extending between the first upper front-side metallization layer 162a and the second upper front-side metallization layer 162b. The fourth insulating layer 168 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the fourth insulating layer 168 is shown as a single layer, in some embodiments, the fourth insulating layer 168 may include multiple layers. For example, the fourth insulating layer 168 may insulate (i.e., isolate) the first upper front-side metallization layer 162a from the second upper front-side metallization layer 162b. In some embodiments, the first upper front-side metallization layer 162a may be configured to receive a first voltage (e.g., drain voltage Vdd), and the second upper front-side metallization layer 162b may be configured to receive a second voltage (e.g., source voltage Vss).

[0154] The first upper front metallization layer 162a may include a plurality of first upper front fingers 162a-1 and a first upper front conductive plate 162a-2. The first upper front fingers 162a-1 may extend from the first upper front conductive plate 162a-2 in the second direction Y (e.g., may extend longitudinally from the first upper front conductive plate 162a-2 in the second direction Y). For example, the first upper front conductive plate 162a-2 may serve as a common electrical path for the first upper front fingers 162a-1 and may share a first voltage with the first upper front fingers 162a-1. In some embodiments, the longest dimension of the first upper front fingers 162a-1 may be in the second direction Y.

[0155] The second upper front metallization layer 162b may include a plurality of second upper front fingers 162b-1 and a second upper front conductive plate 162b-2. The second upper front fingers 162b-1 may extend from the second upper front conductive plate 162b-2 in a second direction Y (e.g., opposite to the first upper front fingers 162a-1), for example, extending longitudinally from the second upper front conductive plate 162b-2 in the second direction Y. For example, the second upper front conductive plate 162b-2 may serve as a common electrical path for the second upper front fingers 162b-1 and may share a second voltage with the second upper front fingers 162b-1. In some embodiments, the longest dimension of the second upper front fingers 162b-1 may be in the second direction Y.

[0156] The first anterior digit 162a-1 and the second anterior digit 162b-1 may be interlocked (e.g., similar to an interlocking structure (such as the fingers of two hands clasped together)), and therefore the first anterior digit 162a-1 and the second anterior digit 162b-1 may be collectively referred to as interlocked anterior digits 162a-1, 162b-1. Figure 5AAs shown, the fourth insulating layer 168 extends between adjacent upper front fingers in the staggered upper front fingers 162a-1, 162b-1, and thus the capacitance (by...) Figure 5A (The capacitor symbol shown in the diagram) may be formed between adjacent upper front fingers of the staggered upper front fingers 162a-1, 162b-1 (e.g., in the first direction X). The staggered upper front fingers 162a-1, 162b-1 may extend in the second direction Y and may be spaced apart from each other in the first direction X. The first upper front finger 162a-1 and the second upper front finger 162b-1 may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first upper front finger 162a-1 and the second upper front finger 162b-1), and may instead be capacitively coupled to each other only. In other words, the first upper front metallization layer 162a and the second upper front metallization layer 162b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first upper front metallization layer 162a and the second upper front metallization layer 162b), and may instead be capacitively coupled to each other only. Although Figure 5A Eleven staggered upper anterior fingers 162a-1, 162b-1 are shown, but this disclosure is not limited thereto. In other embodiments, the anterior MOMCAP 104' may include more than eleven staggered upper anterior fingers 162a-1, 162b-1 or fewer than eleven staggered upper anterior fingers 162a-1, 162b-1.

[0157] In some embodiments, each of the staggered upper front fingers 162a-1, 162b-1 may have a width of less than 100 nanometers (nm) in the first direction X. In some embodiments, adjacent upper front fingers of the staggered upper front fingers 162a-1, 162b-1 (e.g., a corresponding first upper front finger in the first upper front finger 162a-1 adjacent to a corresponding second upper front finger in the second upper front finger 162b-1) may be spaced apart from each other by less than 100 nanometers (nm) in the first direction X. In other words, the distance between adjacent upper front fingers of the staggered upper front fingers 162a-1, 162b-1 in the first direction X may be less than 100 nanometers (nm).

[0158] A front via 166 may be disposed in the front insulating layer 164. The front via 166 may (e.g., in a third direction Z) extend in the front insulating layer 164 between the lower front metallization pattern 160 and the upper front metallization pattern 162. A first front via in the front via 166 may extend between the first lower front metallization layer 160a and the first upper front metallization layer 162a, and may electrically connect the first lower front metallization layer 160a to the first upper front metallization layer 162a. In other words, the first front via in the front via 166 may allow the first lower front metallization layer 160a and the first upper front metallization layer 162a to be electrically coupled (e.g., a direct electrical connection may be provided between the first lower front metallization layer 160a and the first upper front metallization layer 162a). Therefore, the first upper front metallization layer 162a may be electrically connected to the first lower front metallization layer 160a. The second front via in the front via 166 extends between the second lower front metallization layer 160b and the second upper front metallization layer 162b, and can electrically connect the second lower front metallization layer 160b to the second upper front metallization layer 162b. In other words, the second front via in the front via 166 allows the second lower front metallization layer 160b and the second upper front metallization layer 162b to be electrically coupled (e.g., a direct electrical connection can be provided between the second lower front metallization layer 160b and the second upper front metallization layer 162b). Therefore, the second upper front metallization layer 162b can be electrically connected to the second lower front metallization layer 160b.

[0159] The first upper front metallization layer 162a and the second lower front metallization layer 160b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first upper front metallization layer 162a and the second lower front metallization layer 160b), and may be electrically separated from each other through the front insulating layer 164. Similarly, the second upper front metallization layer 162b and the first lower front metallization layer 160a may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the second upper front metallization layer 162b and the first lower front metallization layer 160a), and may be electrically separated from each other through the front insulating layer 164.

[0160] like Figure 5AAs shown, the staggered lower front fingers 160a-1 and 160b-1 can extend in the first direction X, while the staggered upper front fingers 162a-1 and 162b-1 can extend in the second direction Y. For example, the staggered lower front fingers 160a-1 and 160b-1 can extend perpendicularly to the staggered upper front fingers 162a-1 and 162b-1. The staggered upper front fingers 162a-1 and 162b-1 can extend on the staggered lower front fingers 160a-1 and 160b-1, and can (e.g., in the third direction Z) stack with the staggered lower front fingers 160a-1 and 160b-1. Therefore, the capacitor (made by Figure 5A (As shown by the dashed circle in the diagram) can be formed between the staggered lower front fingers 160a-1, 160b-1 and the staggered upper front fingers 162a-1, 162b-1. For example, since the first upper front metallization layer 162a and the second lower front metallization layer 160b are not electrically coupled to each other, a capacitor can be formed where the first upper front finger 162a-1 and the second lower front finger 160b-1 overlap (for example, the front insulating layer 164 is between the first upper front finger 162a-1 and the second lower front finger 160b-1). Similarly, since the second upper front metallization layer 162b and the first lower front metallization layer 160a are not electrically coupled to each other, a capacitor can be formed where the second upper front finger 162b-1 and the first lower front finger 160a-1 overlap (for example, the front insulating layer 164 is between the second upper front finger 162b-1 and the first lower front finger 160a-1).

[0161] exist Figure 5A Dashed circles are provided to help illustrate example embodiments of this disclosure. For the sake of simplicity, Figure 5A The dashed circles in the diagram only indicate some capacitances that may be formed between the staggered lower front fingers 160a-1, 160b-1 and the staggered upper front fingers 162a-1, 162b-1. It will be understood that capacitances not formed between the staggered lower front fingers 160a-1, 160b-1 and the staggered upper front fingers 162a-1, 162b-1 may exist. Figure 5A The additional capacitor is indicated by the dashed circle in the diagram.

[0162] The upper front metallization pattern 162 of the front MOMCAP 104' can increase the capacitance density of the front MOMCAP 104' (i.e., can increase the amount of capacitance per unit area). For example, the front MOMCAP 104' can have capacitance between: (i) adjacent lower front fingers of the staggered lower front fingers 160a-1, 160b-1, (ii) adjacent upper front fingers of the staggered upper front fingers 162a-1, 162b-1, and (iii) staggered lower front fingers 160a-1, 160b-1 and staggered upper front fingers 162a-1, 162b-1. The capacitance density of the front MOMCAP 104' can also be increased by configuring the staggered lower front fingers 160a-1, 160b-1 to extend in the first direction X, while configuring the staggered upper front fingers 162a-1, 162b-1 to extend in the second direction Y, thereby increasing the stacking that can occur between the staggered upper front fingers 162a-1, 162b-1 and the staggered lower front fingers 160a-1, 160b-1.

[0163] As described above, the front MOMCAP 104' may include an upper front metallization pattern 162 on the lower front metallization pattern 160 (e.g., stacked on the lower front metallization pattern 160), with a front insulating layer 164 between the upper front metallization pattern 162 and the lower front metallization pattern 160. For example, in the third direction Z, the lower front metallization pattern 160 may be on the substrate 110 (e.g., see...). Figures 3A to 3E Between the lower front metallization pattern 160 and the upper front metallization pattern 162. In other words, in the third direction Z, the lower front metallization pattern 160 may be located between MOSCAP 102 (e.g., see...). Figures 3A to 3E Between the front-side metallized pattern 162 and the upper front-side pattern 162. It will be understood that in some embodiments, the aforementioned front-side MOMCAP 104 (e.g., see...) Figures 3A to 3E The front-side MOMCAP 104' can be used instead. That is, the aforementioned integrated circuit device 100a is not limited to including the front-side MOMCAP 104, and can alternatively include the front-side MOMCAP 104'. Although Figure 5AThe front MOMCAP 104' is shown to include two metallization patterns (i.e., upper front metallization pattern 162 and lower front metallization pattern 160), but embodiments of this disclosure are not limited thereto. In some other embodiments, the front MOMCAP 104' may include three, four, five, six or more metallization patterns stacked on top of each other, with insulating layers (i.e., dielectric layers) disposed between adjacent metallization patterns. For example, in some other embodiments, the front MOMCAP 104' may include (e.g., in a third direction Z) at least four metallization patterns stacked on top of each other, with staggered fingers of successive metallization patterns alternating between "extending in a first direction X" and "extending in a second direction Y". In other words, in some other embodiments, the front MOMCAP 104' may include a lower front metallized pattern 160 as the lowest metallized pattern, an upper front metallized pattern 162 (e.g., on a third-direction Z) on (e.g., stacked on) the lower front metallized pattern 160, another lower front metallized pattern 160 (e.g., on a third-direction Z) on (e.g., stacked on) the upper front metallized pattern 162, and another upper front metallized pattern 162 (e.g., on a third-direction Z) on (e.g., stacked on) the other lower front metallized pattern 160.

[0164] Reference Figure 5B The back-side MOMCAP 106' may include an upper back-side metallization pattern 180. The back-side MOMCAP 106' may also include a lower back-side metallization pattern 182 (e.g., on a third-direction Z) on the lower surface of the upper back-side metallization pattern 180, and a back-side insulating layer 184 (e.g., on a third-direction Z) between the upper back-side metallization pattern 180 and the lower back-side metallization pattern 182. For example, the upper back-side metallization pattern 180 may be (e.g., may be stacked on) the lower back-side metallization pattern 182 (e.g., on a third-direction Z), and the back-side insulating layer 184 may be between the upper back-side metallization pattern 180 and the lower back-side metallization pattern 182. The lower back-side metallization pattern 182 may include a first lower back-side metallization layer 182a and a second lower back-side metallization layer 182b. The lower back-side metallization pattern 182 may include a metal layer or a material comprising, for example, W, Al, Cu, Mo, Co, and / or Ru. The back-side insulating layer 184 may include one or more insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the back-side insulating layer 184 is shown as a single layer, in some embodiments, the back-side insulating layer 184 may include multiple layers.

[0165] The back-side MOMCAP 106' may also include a fifth insulating layer 188 extending between the first lower back-side metallization layer 182a and the second lower back-side metallization layer 182b. The fifth insulating layer 188 may include (one or more) insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, and / or low-k materials). Although the fifth insulating layer 188 is shown as a single layer, in some embodiments, the fifth insulating layer 188 may include multiple layers. For example, the fifth insulating layer 188 may insulate (i.e., isolate) the first lower back-side metallization layer 182a from the second lower back-side metallization layer 182b. In some embodiments, the first lower back-side metallization layer 182a may be configured to receive a first voltage (e.g., drain voltage Vdd), and the second lower back-side metallization layer 182b may be configured to receive a second voltage (e.g., source voltage Vss).

[0166] The first lower back-side metallization layer 182a may include a plurality of first lower back-side fingers 182a-1 and a first lower back-side conductive plate 182a-2. The first lower back-side fingers 182a-1 may extend from the first lower back-side conductive plate 182a-2 in the second direction Y (e.g., may extend longitudinally from the first lower back-side conductive plate 182a-2 in the second direction Y). For example, the first lower back-side conductive plate 182a-2 may serve as a common electrical path for the first lower back-side fingers 182a-1 and may share a first voltage with the first lower back-side fingers 182a-1. In some embodiments, the longest dimension of the first lower back-side fingers 182a-1 may be in the second direction Y.

[0167] The second lower back-side metallization layer 182b may include a plurality of second lower back-side fingers 182b-1 and a second lower back-side conductive plate 182b-2. The second lower back-side fingers 182b-1 may extend from the second lower back-side conductive plate 182b-2 in a second direction Y (e.g., opposite to the first lower back-side fingers 182a-1), for example, by extending longitudinally from the second lower back-side conductive plate 182b-2 in the second direction Y. For example, the second lower back-side conductive plate 182b-2 may serve as a common electrical path for the second lower back-side fingers 182b-1 and may share a second voltage with the second lower back-side fingers 182b-1. In some embodiments, the longest dimension of the second lower back-side fingers 182b-1 may be in the second direction Y.

[0168] The first lower dorsal finger 182a-1 and the second lower dorsal finger 182b-1 may be interlocked (e.g., similar to an interlocking structure (such as the fingers of two hands clasped together)), and therefore the first lower dorsal finger 182a-1 and the second lower dorsal finger 182b-1 may be collectively referred to as interlocked lower dorsal fingers 182a-1, 182b-1. Figure 5BAs shown, the fifth insulating layer 188 extends between adjacent lower back-side fingers in the staggered lower back-side fingers 182a-1, 182b-1, and thus the capacitance (by...) Figure 5B (The capacitor symbol shown in the diagram) may be formed between adjacent lower back-side fingers of the staggered lower back-side fingers 182a-1, 182b-1 (e.g., in the first direction X). The staggered lower back-side fingers 182a-1, 182b-1 may extend in the second direction Y and may be spaced apart from each other in the first direction X. The first lower back-side fingers 182a-1 and the second lower back-side fingers 182b-1 may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first lower back-side fingers 182a-1 and the second lower back-side fingers 182b-1), and may instead be capacitively coupled to each other only. In other words, the first lower back-side metallization layer 182a and the second lower back-side metallization layer 182b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first lower back-side metallization layer 182a and the second lower back-side metallization layer 182b), and may instead be capacitively coupled to each other only. Although Figure 5B Eleven staggered lower dorsal fingers 182a-1, 182b-1 are shown, but this disclosure is not limited thereto. In other embodiments, the dorsal MOMCAP 106' may include more than eleven staggered lower dorsal fingers 182a-1, 182b-1 or fewer than eleven staggered lower dorsal fingers 182a-1, 182b-1.

[0169] In some embodiments, each of the staggered lower back-side fingers 182a-1, 182b-1 may have a width of less than 100 nanometers (nm) in the first direction X. In some embodiments, adjacent lower back-side fingers of the staggered lower back-side fingers 182a-1, 182b-1 (e.g., a corresponding first lower back-side finger in the first lower back-side finger 182a-1 adjacent to a corresponding second lower back-side finger in the second lower back-side finger 182b-1) may be spaced apart from each other by less than 100 nanometers (nm) in the first direction X. In other words, the distance between adjacent lower back-side fingers of the staggered lower back-side fingers 182a-1, 182b-1 in the first direction X may be less than 100 nanometers (nm).

[0170] A back-side via 186 may be disposed in a back-side insulating layer 184. The back-side via 186 may (e.g., in a third direction Z) extend in the back-side insulating layer 184 between the upper back-side metallization pattern 180 and the lower back-side metallization pattern 182. A first back-side via in the back-side via 186 may extend between a first upper back-side metallization layer 180a and a first lower back-side metallization layer 182a, and may electrically connect the first upper back-side metallization layer 180a to the first lower back-side metallization layer 182a. In other words, the first back-side via in the back-side via 186 may allow the first upper back-side metallization layer 180a and the first lower back-side metallization layer 182a to be electrically coupled (e.g., providing a direct electrical connection between the first upper back-side metallization layer 180a and the first lower back-side metallization layer 182a). Therefore, the first lower back-side metallization layer 182a may be electrically connected to the first upper back-side metallization layer 180a. The second back-side via in the back-side via 186 extends between the second upper back-side metallization layer 180b and the second lower back-side metallization layer 182b, and can electrically connect the second upper back-side metallization layer 180b to the second lower back-side metallization layer 182b. In other words, the second back-side via in the back-side via 186 allows the second upper back-side metallization layer 180b and the second lower back-side metallization layer 182b to be electrically coupled (e.g., providing a direct electrical connection between the second upper back-side metallization layer 180b and the second lower back-side metallization layer 182b). Therefore, the second lower back-side metallization layer 182b can be electrically connected to the second upper back-side metallization layer 180b.

[0171] The first lower back metallization layer 182a and the second upper back metallization layer 180b may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the first lower back metallization layer 182a and the second upper back metallization layer 180b), and may be electrically separated from each other through the back insulating layer 184. Similarly, the second lower back metallization layer 182b and the first upper back metallization layer 180a may not be electrically coupled to each other (e.g., there may be no direct electrical connection between the second lower back metallization layer 182b and the first upper back metallization layer 180a), and may be electrically separated from each other through the back insulating layer 184.

[0172] like Figure 5BAs shown, the staggered upper back-side fingers 180a-1 and 180b-1 extend in a first direction X, while the staggered lower back-side fingers 182a-1 and 182b-1 extend in a second direction Y. For example, the staggered upper back-side fingers 180a-1 and 180b-1 may extend perpendicularly to the staggered lower back-side fingers 182a-1 and 182b-1. The staggered upper back-side fingers 180a-1 and 180b-1 may extend over the staggered lower back-side fingers 182a-1 and 182b-1, and may (e.g., in a third direction Z) be stacked with the staggered lower back-side fingers 182a-1 and 182b-1. Therefore, the capacitor (made by Figure 5B (As shown by the dashed circle in the diagram) can be formed between the staggered upper back-side fingers 180a-1, 180b-1 and the staggered lower back-side fingers 182a-1, 182b-1. For example, since the second lower back-side metallization layer 182b and the first upper back-side metallization layer 180a are not electrically coupled to each other, a capacitor can be formed where the first upper back-side fingers 180a-1 and the second lower back-side fingers 182b-1 overlap (e.g., the back-side insulating layer 184 is between the first upper back-side fingers 180a-1 and the second lower back-side fingers 182b-1). Similarly, since the first lower back metallization layer 182a and the second upper back metallization layer 180b are not electrically coupled to each other, a capacitor can be formed where the second upper back finger 180b-1 overlaps with the first lower back finger 182a-1 (for example, the back insulating layer 184 is between the second upper back finger 180b-1 and the first lower back finger 182a-1).

[0173] exist Figure 5B Dashed circles are provided to help illustrate example embodiments of this disclosure. For the sake of simplicity, Figure 5B The dashed circles in the diagram only indicate some capacitances that may be formed between the staggered upper back-side fingers 180a-1, 180b-1 and the staggered lower back-side fingers 182a-1, 182b-1. It will be understood that capacitances not formed between the staggered upper back-side fingers 180a-1, 180b-1 and the staggered lower back-side fingers 182a-1, 182b-1 may exist. Figure 5B The additional capacitor is indicated by the dashed circle in the diagram.

[0174] The lower back-side metallization pattern 182 of the back-side MOMCAP 106' can increase the capacitance density of the back-side MOMCAP 106' (i.e., increase the amount of capacitance per unit area). For example, the back-side MOMCAP 106' can have capacitance between: (i) adjacent upper back-side fingers of staggered upper back-side fingers 180a-1, 180b-1, (ii) adjacent lower back-side fingers of staggered lower back-side fingers 182a-1, 182b-1, and (iii) staggered upper back-side fingers 180a-1, 180b-1 and staggered lower back-side fingers 182a-1, 182b-1. The capacitance density of the back-side MOMCAP 106' can also be increased by configuring the staggered upper back-side fingers 180a-1, 180b-1 to extend in the first direction X, while configuring the staggered lower back-side fingers 182a-1, 182b-1 to extend in the second direction Y, thereby increasing the stacking that can occur between the staggered upper back-side fingers 180a-1, 180b-1 and the staggered lower back-side fingers 182a-1, 182b-1.

[0175] As described above, the back-side MOMCAP 106' may include (e.g., stacked on) an upper back-side metallization pattern 180 on a lower back-side metallization pattern 182, with a back-side insulating layer 184 between the upper back-side metallization pattern 180 and the lower back-side metallization pattern 182. For example, in the third direction Z, the upper back-side metallization pattern 180 may be on the substrate 110 (e.g., see...). Figures 3A to 3E The upper back-side metallization pattern 180 is located between the upper back-side metallization pattern 180 and the lower back-side metallization pattern 182. In other words, in the third direction Z, the upper back-side metallization pattern 180 can be located between the MOSCAP 102 (e.g., see [reference]). Figures 3A to 3E Between the lower back-side metallized pattern 182 and the aforementioned back-side MOMCAP 106 (e.g., see...). It will be understood that in some embodiments, the aforementioned back-side MOMCAP 106 (e.g., see...) Figures 3A to 3E The back-side MOMCAP 106' can be used instead. That is, the aforementioned integrated circuit device 100a is not limited to including the back-side MOMCAP 106, and may alternatively include the back-side MOMCAP 106'. Although Figure 5BThe back-side MOMCAP 106' is shown to include two metallization patterns (i.e., upper back-side metallization pattern 180 and lower back-side metallization pattern 182), but embodiments of this disclosure are not limited thereto. In some other embodiments, the back-side MOMCAP 106' may include three, four, five, six or more metallization patterns stacked on top of each other, with insulating layers (i.e., dielectric layers) disposed between adjacent metallization patterns. For example, in some other embodiments, the back-side MOMCAP 106' may include at least four metallization patterns stacked on top of each other (e.g., in a third direction Z), with staggered fingers of successive metallization patterns alternating between "extending in a first direction X" and "extending in a second direction Y". In other words, in some other embodiments, the back side MOMCAP106' may include an upper back side metallization pattern 180 as the uppermost metallization pattern, a lower back side metallization pattern 182 on the lower surface of the upper back side metallization pattern 180 (e.g., on the third direction Z), another upper back side metallization pattern 180 on the lower surface of the lower back side metallization pattern 182 (e.g., on the third direction Z), and another lower back side metallization pattern 182 on the lower surface of the other upper back side metallization pattern 180 (e.g., on the third direction Z).

[0176] Figure 6A It is according to some further embodiments along Figure 3B A schematic cross-sectional view taken by line C-C'. Figure 6B It is according to some further embodiments along Figure 3B A schematic cross-sectional view taken by line D-D'. The same reference numerals denote the same elements. For simplicity, repeated descriptions of the same elements may be omitted.

[0177] like Figure 6A As shown, the first lower source / drain contact structure 134a' may not include the third source / drain contact 112a (see [reference]). Figure 3DFor example, the upper surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140 may not be in contact with the first lower source / drain contact structure 134a'. The first lower source / drain contact structure 134a' may include a third intermediate conductive plug 116a', a fourth source / drain contact 124a', and a third lower conductive plug 128a. The third lower conductive plug 128a may be electrically connected between the fourth source / drain contact 124a' and the back-side MOMCAP 106. For example, according to some embodiments, the third lower conductive plug 128a may be in contact with the back-side MOMCAP 106 (e.g., may be electrically contacted with the back-side MOMCAP 106). The third intermediate conductive plug 116a' may be electrically connected between the first conductive line 132a and the fourth source / drain contact 124a'. The fourth source / drain contact 124a' may contact the first lower source / drain region 140 of a pair of lower source / drain regions 140 (e.g., may make electrical contact with the first lower source / drain region 140 of a pair of lower source / drain regions 140). For example, the fourth source / drain contact 124a' may be on the lower surface of the first lower source / drain region 140 of a pair of lower source / drain regions 140 and contact the lower surface of the first lower source / drain region 140 of a pair of lower source / drain regions 140. The third lower conductive plug 128a may include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co and / or Ru.

[0178] Instead of providing a third source / drain contact 112a on the upper surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140, a fourth source / drain contact 124a' is provided only on the lower surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140 (see [link to source / drain contact]). Figure 3D Both the first lower source / drain contact 124a on the lower surface of the first lower source / drain region 140 in a pair of lower source / drain regions 140 can simplify the manufacturing process for the first lower source / drain contact structure 134a' and reduce the associated costs.

[0179] like Figure 6B As shown, the second lower source / drain contact structure 134b' may not include the fifth source / drain contact 112b (see [reference]). Figure 3EFor example, the upper surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140 may not be in contact with the second lower source / drain contact structure 134b'. The second lower source / drain contact structure 134b' may include a fourth intermediate conductive plug 116b', a sixth source / drain contact 124b', and a fourth lower conductive plug 128b. The fourth lower conductive plug 128b may be electrically connected between the sixth source / drain contact 124b' and the back-side MOMCAP 106. For example, according to some embodiments, the fourth lower conductive plug 128b may be in contact with the back-side MOMCAP 106 (e.g., may be electrically contacted with the back-side MOMCAP 106). The fourth intermediate conductive plug 116b' may be electrically connected between the second conductive line 132b and the sixth source / drain contact 124b'. The sixth source / drain contact 124b' may contact the second lower source / drain region 140 of a pair of lower source / drain regions 140 (e.g., may be electrically contacted with the second lower source / drain region 140 of a pair of lower source / drain regions 140). For example, the sixth source / drain contact 124b' may be on the lower surface of the second lower source / drain region 140 of a pair of lower source / drain regions 140 and contact the lower surface of the second lower source / drain region 140 of a pair of lower source / drain regions 140. The fourth lower conductive plug 128b may include a metal layer or include a material comprising, for example, W, Al, Cu, Mo, Co and / or Ru.

[0180] Instead of providing a fifth source / drain contact 112b on the upper surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140, a sixth source / drain contact 124b' is provided only on the lower surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140 (see [link to source / drain contact]). Figure 3E Both the second lower source / drain contact structure 134b' and the sixth source / drain contact 124b on the lower surface of the second lower source / drain region 140 in a pair of lower source / drain regions 140 can simplify the manufacturing process of the second lower source / drain contact structure 134b' and reduce the associated costs.

[0181] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, unless expressly defined herein, all terms shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0182] In the above description, example embodiments are described with reference to regions of a specific conductivity type. It will be understood that devices of opposite conductivity types can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Therefore, it will be understood that this disclosure covers n-channel and p-channel devices for each different device structure.

[0183] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising” and / or “including” specify the presence of the described features, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups thereof.

[0184] It will be understood that although the terms “first,” “second,” etc., are used throughout this specification to describe various elements, these elements should not be limited by these terms. Rather, these terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0185] The terms “around,” “cover,” or “fill” as used herein do not require complete surrounding, covering, or filling of the described element or layer, but may, for example, indicate partial surrounding, covering, or filling of the described element or layer. When viewed along a line extending in a particular direction or in a plane perpendicular to the particular direction, components or layers described as “overlapping” in that particular direction may at least partially obscure each other.

[0186] It will be understood that when a component (such as a layer, region, or substrate) is referred to as being "on" or extending "on" another component, it may be directly on or directly extending to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly" extending "on" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components. The term "connection" can include physical connections and / or electrical connections.

[0187] As illustrated in the accompanying drawings, spatial relative terms (such as "below," "above," "upper," "lower," "top," "bottom," or "side") may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region based on a frame of reference (e.g., a base). It will be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the accompanying drawings.

[0188] Example embodiments are described herein with reference to the accompanying drawings, which may include cross-sectional views as schematic illustrations of idealized embodiments (and intermediate structures). Many different forms and embodiments are possible without departing from the teachings of this disclosure. Therefore, this disclosure should not be construed as limited to the example embodiments set forth herein. Thus, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope defined herein. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Additionally, variations in the shapes of the illustrations may be expected due to, for example, manufacturing techniques and / or tolerances.

[0189] The subject matter disclosed above is intended to be illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of this disclosure. Therefore, to the fullest extent permitted by law, the scope will be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be bound or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, comprising: Base; as well as Metal-oxide-semiconductor capacitors, on a substrate, include: The lower semiconductor device, on a substrate, includes a pair of lower source / drain regions and a lower gate structure between the pair of lower source / drain regions; and An upper semiconductor device, situated on a lower semiconductor device, includes a pair of upper source / drain regions and an upper gate structure between the pair of upper source / drain regions. The lower gate structure is electrically connected to both of the pair of upper source / drain regions.

2. The integrated circuit device according to claim 1, wherein, The upper gate structure is electrically connected to both of the pair of lower source / drain regions.

3. The integrated circuit device according to claim 1, wherein, Metal-oxide-semiconductor capacitors also include an isolation region between the lower gate structure and the upper gate structure, and The lower gate structure is electrically separated from the upper gate structure through an isolation region.

4. The integrated circuit device according to claim 1, wherein, The lower gate structure is configured to receive a first voltage, and The upper gate structure is configured to receive a second voltage that is different from the first voltage.

5. The integrated circuit device according to claim 1, wherein, The lower semiconductor device also includes a plurality of lower channel layers between the pair of lower source / drain regions, the plurality of lower channel layers being spaced apart from each other in a direction perpendicular to the upper surface of the substrate, and The upper semiconductor device further includes a plurality of upper channel layers between the pair of upper source / drain regions, the plurality of upper channel layers being spaced apart from each other in the direction.

6. The integrated circuit device according to claim 1, wherein, The pair of lower source / drain regions have a first conductivity type, and The pair of source / drain regions have a second conductivity type that is different from the first conductivity type.

7. The integrated circuit device according to any one of claims 1 to 6, wherein, The lower gate structure and the upper gate structure are configured to receive a first voltage and a second voltage, respectively, and When the first voltage and the second voltage cause both the lower semiconductor device and the upper semiconductor device to operate in the inversion region, the metal-oxide-semiconductor capacitor is configured to have the maximum capacitance value.

8. An integrated circuit device, comprising: Base; A front-side metal oxide capacitor is located on the first surface of the substrate. as well as A back-side metal oxide capacitor is electrically connected to a front-side metal oxide capacitor on a second surface of a substrate opposite to the first surface.

9. The integrated circuit device according to claim 8, wherein, The back-side metal oxide capacitor includes an upper back-side metallization pattern, which comprises a plurality of interlaced upper back-side fingers. The plurality of interlaced upper back-side fingers extend in a first direction parallel to the first surface of the substrate and are spaced apart from each other in a second direction intersecting the first direction.

10. The integrated circuit device according to claim 9, further comprising: A semiconductor device, on a first surface of a substrate, includes a pair of source / drain regions and a gate structure between the pair of source / drain regions. The gate structure extends in the second direction and is stacked on at least one of the plurality of interlaced upper back-side fingers in a third direction perpendicular to the first surface of the substrate.

11. The integrated circuit device according to claim 9, wherein, The upper back metallization pattern includes a first upper back metallization layer and a second upper back metallization layer. The first upper back metallization layer includes a first interlaced upper back finger among the plurality of interlaced upper back fingers, and the second upper back metallization layer includes a second interlaced upper back finger among the plurality of interlaced upper back fingers. The first upper back-side metallization layer is capacitively coupled to the second upper back-side metallization layer, and The back-side metal oxide capacitor also includes an insulating layer between the first upper back-side metallization layer and the second upper back-side metallization layer.

12. The integrated circuit device according to claim 9, wherein, The back-side metal oxide capacitor also includes a lower back-side metallization pattern on the lower surface of the upper back-side metallization pattern, the lower back-side metallization pattern comprising a plurality of interlaced lower back-side fingers. The plurality of interlaced lower dorsal fingers extend in the second direction and are spaced apart from each other in the first direction.

13. The integrated circuit device according to claim 12, wherein, The back-side metal oxide capacitor also includes a back-side insulating layer in a third direction perpendicular to the first surface of the substrate, between the lower back-side metallization pattern and the upper back-side metallization pattern. In this embodiment, at least one of the plurality of interlaced upper dorsal fingers is superimposed on at least one of the plurality of interlaced lower dorsal fingers in a third direction.

14. The integrated circuit device according to any one of claims 8 to 13, wherein the integrated circuit device further comprises: A metal-oxide-semiconductor capacitor, located between a front-side metal-oxide-semiconductor capacitor and a back-side metal-oxide-semiconductor capacitor. Metal-oxide-semiconductor capacitors include: The lower semiconductor device, on a substrate, includes a pair of lower source / drain regions and a lower gate structure between the pair of lower source / drain regions; and An upper semiconductor device, on a lower semiconductor device, includes a pair of upper source / drain regions and an upper gate structure between the pair of upper source / drain regions.

15. The integrated circuit device of claim 14, further comprising: An upper source / drain contact structure extends between a front-side metal-oxide-semiconductor capacitor and a back-side metal-oxide-semiconductor capacitor, wherein a first upper source / drain region in the pair of upper source / drain regions is electrically connected to both the front-side and back-side metal-oxide-semiconductor capacitors via the upper source / drain contact structure.

16. The integrated circuit device of claim 14, further comprising: A lower source / drain contact structure extends between a front-side metal-oxide-semiconductor capacitor and a back-side metal-oxide-semiconductor capacitor, wherein a first lower source / drain region in the pair of lower source / drain regions is electrically connected to both the front-side and back-side metal-oxide-semiconductor capacitors via the lower source / drain contact structure.

17. An integrated circuit device, comprising: Base; Metal-oxide-semiconductor capacitor, on the first surface of a substrate; as well as A back-side metal oxide capacitor is electrically connected to a metal oxide semiconductor capacitor on a second surface of a substrate opposite to a first surface.

18. The integrated circuit device according to claim 17, wherein, Metal-oxide-semiconductor capacitors include: The lower semiconductor device, on a substrate, includes a pair of lower source / drain regions and a lower gate structure between the pair of lower source / drain regions; and An upper semiconductor device, on a lower semiconductor device, includes a pair of upper source / drain regions and an upper gate structure between the pair of upper source / drain regions.

19. The integrated circuit device of claim 18, further comprising: A lower gate contact extends into the substrate, wherein the lower gate structure is electrically connected to a back-side metal-oxide-semiconductor capacitor via the lower gate contact.

20. The integrated circuit device of claim 18, further comprising: A lower source / drain contact structure extends into the substrate, wherein the first lower source / drain region of the pair of lower source / drain regions is electrically connected to the back-side metal-oxide-semiconductor capacitor via the lower source / drain contact structure.

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