A method for designing and manufacturing inner layer circuit of printed circuit board

Abstract

The application discloses a kind of design and manufacture method of printed circuit board inner layer circuit, the design and manufacture method includes: determining drilling parameter, and the basic size of connection PAD is set based on drilling parameter;Tear drop-shaped gradual widening structure is generated in the transition area of connection PAD and inner layer circuit, the structure of heat dissipation PAD is designed synchronously, and inner layer circuit wiring design is completed;Form inner layer circuit film, and check film;At the same time, pre-treatment is carried out to PCB inner layer substrate;The pattern is formed by aligning the film that passes the check with inner layer substrate;Substrate is etched;The substrate after etching is cleaned, and unqualified product is identified and screened, and the qualified product is inner layer circuit product.The application solves the problem of weak connection and easy breakage of PTH hole and inner layer circuit in high-density PCB through the three-in-one technical route of structure optimization+process synergy+precision control, and improves the mechanical strength, electrical reliability and thermal management capability of the product.

Description

Technical Field

[0001] This invention relates to the technical field of printed circuit board design and manufacturing methods, and more specifically to a method for designing and manufacturing the inner layer circuitry of a printed circuit board. Background Technology

[0002] In the manufacturing process of printed circuit boards (PCBs), reliable connections between inner layer traces and plated through holes (PTHs) are crucial for ensuring the integrity of circuit functionality and the long-term stable operation of the product. Traditional inner layer connection pad designs typically employ a scheme where the film diameter is only slightly larger than the drill bit diameter. While this design saves wiring space, it results in limited copper foil area in the connection region between the PTH hole and the inner layer trace, leading to weak structural strength.

[0003] In subsequent PCB manufacturing processes, such as lamination, etching, and electroplating, as well as external forces such as thermal stress cycles, mechanical vibration, or impact experienced by the product in actual use environments, the connection area is prone to microcracks due to stress concentration, and may even experience serious failures such as connection breakage or conduction failure, affecting the electrical performance and service life of the PCB product.

[0004] To improve connection reliability, some existing technologies attempt to increase the copper foil area of ​​the connection region by simply increasing the diameter of the connection pad. However, this method has significant limitations in the high-density PCB design used in miniaturized electronic devices such as High-Density Interconnect (HDI): on the one hand, excessively large pads occupy valuable wiring space, limiting the optimization of trace density and layer count; on the other hand, simply increasing the pad area cannot effectively alleviate stress concentration problems and cannot fundamentally eliminate the risk of breakage of the connection under thermo-mechanical coupling.

[0005] With the rapid development of 5G communication, artificial intelligence, wearable devices, and high-performance computing, electronic devices are placing comprehensive demands on PCBs for higher integration, smaller size, and higher reliability. Against this backdrop, traditional inner-layer connection PAD designs are no longer sufficient to meet the stringent reliability requirements of modern high-density PCBs for the connection between PTH vias and inner-layer traces. Therefore, there is an urgent need for a new method of inner-layer trace fabrication that can enhance the strength of the connection structure, effectively distribute stress, and not significantly increase the space occupied by wiring, in order to overcome existing technological bottlenecks and ensure the long-term stable operation of high-density PCBs under complex operating conditions. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for designing and manufacturing the inner layer circuitry of a printed circuit board.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: This invention provides a method for designing and fabricating inner layer circuitry on a printed circuit board, comprising: The drilling parameters are determined according to the product design requirements, and the basic dimensions of the connecting PAD are set based on the drilling parameters, wherein the film diameter of the connecting PAD is more than 0.3mm larger than the diameter of the drill bit used for drilling. A teardrop-shaped, gradually widened structure is generated in the transition area between the connection PAD and the inner layer circuitry, which has a set basic size. This teardrop structure changes the connection between the circuitry and the connection PAD from point contact to surface contact. At the same time, the structure of the open heat dissipation PAD is designed to complete the inner layer circuitry design. The output wiring design forms an inner layer circuit film, and the dimensions of the circuit, connection PAD, teardrop structure and heat dissipation PAD on the film are verified; at the same time, the PCB inner layer substrate is pre-treated, which includes degreasing, roughening, water washing and drying processes in sequence. The qualified film is aligned with the inner substrate that has been pre-treated and coated with photoresist. Through ultraviolet light exposure and development, a pattern of lines, connecting PADs, teardrop structures and heat dissipation PADs protected by photoresist is formed on the substrate. The substrate with the pattern is etched to remove the copper layer that is not protected by photoresist, so that the inner layer circuitry is physically formed on the substrate. The etched substrate is cleaned and inspected using an automated optical inspection device. Defective products with defects in circuitry, connection pads, teardrop structures, or heat dissipation pads are identified and screened. Qualified products are the finished inner layer circuitry.

[0008] In one specific embodiment, when generating the teardrop-shaped gradient widening structure, the teardrop generation plugin in the CAD design software is called, and the teardrop parameters are set according to the quantitative specifications to achieve automated generation. After generation, the transition effect between the teardrop and the connecting PAD and inner layer circuitry is verified.

[0009] In one specific embodiment, the length L of the teardrop structure along the inner layer trace direction satisfies the following condition: L is not less than the line width W of the inner layer trace, and not greater than 1.5 times the diameter D of the connecting PAD pad.

[0010] In one specific embodiment, the width T of the teardrop structure along the vertical routing direction satisfies the following conditions: T is not less than the width W of the inner layer routing line, and satisfies any of the following upper limit conditions: T≤1.3×W; or T≤0.8×D.

[0011] In one specific embodiment, the opening width of the heat dissipation PAD is not less than 5 mil, and the radial length is not less than 6 mil.

[0012] In one specific embodiment, in the BGA or CPU hole area, at least two conductive paths are maintained between the heat dissipation PAD and GND, and the width of each conductive path is not less than 5mil.

[0013] In one specific embodiment, when performing dimensional verification on the film, an optical inspection device is used to verify the dimensional accuracy of the connecting PAD, teardrop structure, and heat dissipation PAD on the film, so as to reject unqualified films.

[0014] In one specific embodiment, when cleaning the etched substrate, deionized water is used to perform multiple cleaning operations.

[0015] In one specific embodiment, when using an automated optical inspection device for inspection, the substrate image is compared with standard CAM data to identify whether there are defects such as dimensional deviations, broken connections, short circuits, or incomplete patterns in the circuits, connection PADs, teardrop structures, or heat dissipation PADs.

[0016] In one specific embodiment, the teardrop structure is used to disperse the stress generated at the connection between the PTH hole and the inner layer circuitry during drilling, electroplating, and thermal cycling.

[0017] The design and fabrication method for the inner layer circuitry of the printed circuit board of this invention has the following advantages compared with the prior art: By improving the traditional point-contact connection method to a surface-contact teardrop transition structure, a smooth and continuous copper foil connection area is formed between the inner layer circuitry and the connecting PAD. This structure can effectively disperse the concentrated stress generated at the edge of the PTH hole during processes such as drilling, electroplating, lamination, and thermal cycling, significantly reducing the risk of microcracks, connection breakage, or conduction failure caused by stress concentration, thereby improving the mechanical strength and electrical reliability of the connection parts. In addition, by embedding the parameter specifications of the teardrop structure, connecting PAD, and open-type heat dissipation PAD into the standardized film design and photolithography process flow, and by using dual quality control methods of film size verification and automatic optical inspection (AOI), the dimensional accuracy and pattern integrity of key structures are ensured. This not only reduces rework or scrap due to connection defects, but also improves the consistency of mass production and the yield of finished products. In addition, the synchronously designed open heat dissipation PAD structure provides an effective heat conduction path for the PTH area without sacrificing the reliability of electrical connections. This helps to dissipate heat in a timely manner under high power or high frequency operating conditions, slows down material aging or performance degradation caused by heat accumulation, and further ensures the long-term stable operation of the PCB in complex operating environments.

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating the design and fabrication method of the inner layer circuitry of a printed circuit board provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0025] Please see Figure 1 The diagram shows a flowchart of the design and fabrication method for the inner layer circuitry of a printed circuit board provided by the present invention. The method includes the following steps S110 to S160.

[0026] S110. Determine the drilling parameters according to the product design requirements, and set the basic dimensions of the connecting PAD based on the drilling parameters, wherein the film diameter of the connecting PAD is more than 0.3mm larger than the diameter of the drill bit used for drilling. Specifically, in the initial PCB design phase, the location, number, and drill bit diameter (e.g., 0.25mm, 0.3mm, etc.) of the required PTH (Plated Through Hole) are determined based on factors such as circuit function, signal integrity, current carrying capacity, and subsequent assembly requirements (e.g., BGA package pin spacing). Subsequently, the film pattern dimensions for the connecting PADs (i.e., inner layer pads) are set in the CAD design software. This solution stipulates that the film diameter of the connecting PAD must be at least 0.3mm larger than the drill bit diameter used (i.e., an outward expansion of ≥0.15mm on one side). For example, if a 0.3mm drill bit is used, the film diameter for the connecting PAD should be no less than 0.6mm.

[0027] In other words, this size setting ensures that even with minor drilling deviations (typically allowing ±0.075mm) during subsequent drilling, the drill edge will still completely cover the copper foil pad area, avoiding the risk of "broken holes" (i.e., the drilled portion falling outside the pad, causing discontinuity in the copper layer connection). Simultaneously, the minimum outward expansion of 0.3mm ensures a reliable annular ring connection area while avoiding excessive pad enlargement that would waste valuable routing space, reserving more routing channels for high-density routing.

[0028] S120. A teardrop-shaped gradually widened structure is generated in the transition area between the connection PAD and the inner layer circuit with the set basic size. This teardrop structure changes the connection between the circuit and the connection PAD from point contact to surface contact. At the same time, the structure of the open heat dissipation PAD is designed to complete the inner layer circuit wiring design. Specifically, after setting the basic dimensions of the connecting PAD, a teardrop-shaped copper foil transition area is automatically inserted between the two at the intersection of the PAD and the inner layer traces using CAD software (such as Altium Designer, Cadence Allegro, etc.). This teardrop structure extends smoothly along the trace direction, gradually transitioning from the trace width W to merging with the edge of the connecting PAD. The teardrop length L and maximum width T are controlled according to preset specifications (e.g., L=1×W and L≤1.5×D; T=(1.0~1.3)×W or T≤0.8×D). Simultaneously, in areas requiring heat dissipation (such as power layers, below BGAs), open-type heat dissipation PADs are designed—that is, at least two radial openings with a width ≥5mil are created on circular or square pads, making the pads "petal-shaped." This preserves electrical connection paths and forms heat conduction paths while preventing 'voids' or 'delamination' from forming on large solid pads during lamination.

[0029] In other words, the teardrop structure transforms the originally sharp "T-shaped" or "L-shaped" right-angle connection into a smooth curved transition, reducing stress concentration at the connection corners during thermal expansion / contraction or mechanical vibration, effectively preventing copper foil tearing or breakage. Furthermore, the larger connection area improves current carrying capacity and local heat dissipation efficiency. The teardrop structure has a higher tolerance for process fluctuations such as etching deviations and alignment errors, reducing connection failures caused by minor offsets. In addition, while ensuring the reliability of the GND connection (retaining at least two conductive paths ≥5mil wide), the opening design increases the contact area between the copper foil and the dielectric layer, improving heat conduction efficiency and preventing "voids" or "delamination" from forming on large solid pads during lamination.

[0030] S130. Output the wiring design to form an inner layer circuit film, and verify the dimensions of the circuit, connection PAD, teardrop structure and heat dissipation PAD on the film; at the same time, perform pre-processing on the PCB inner layer substrate, the pre-processing including degreasing, roughening, water washing and drying processes in sequence. Specifically, after completing the wiring design, the graphic data including the circuitry, connecting pads, teardrop structures, and heat dissipation pads is output as a high-precision photoplot file (Gerber) for creating the inner layer circuitry film. After the film is created, high-resolution optical inspection equipment is used to automatically measure and compare its key dimensions (such as teardrop length L, width T, pad diameter D, and aperture width), discarding substandard films that exceed tolerance limits. Simultaneously, the copper-clad laminate (inner layer substrate) is processed sequentially as follows: Degreasing: Removes surface grease and organic contaminants; Roughening: Micro-etching or chemical treatment is used to create a rough structure on the copper surface, which enhances the adhesion of subsequent photoresist. Wash with water: Thoroughly remove any residual medication; Drying: Ensure the substrate surface is clean and dry to avoid affecting the uniformity of adhesive application.

[0031] In other words, film size verification ensures pattern accuracy from the source, preventing batch manufacturing defects caused by film flaws. Furthermore, substrate pretreatment ensures a firm bond between the photoresist and the copper surface, avoiding issues such as photoresist peeling and pattern distortion during exposure and development, thus laying the foundation for subsequent precise replication of delicate structures such as teardrops.

[0032] S140. Align the qualified film with the pre-treated and photoresist-coated inner substrate, and form a pattern of lines, connecting PADs, teardrop structures and heat dissipation PADs protected by photoresist on the substrate by ultraviolet light exposure and development. Specifically, the pre-treated substrate is uniformly coated with liquid or dry film photoresist, and then aligned with a calibrated film using a precision alignment machine (alignment accuracy is typically ≤ ±10μm). Subsequently, selective exposure is performed in an ultraviolet light exposure machine—the transparent areas of the film allow light to pass through, causing the photoresist to cross-link and cure, while the shaded areas remain soluble. The unexposed areas are then washed away with a developing solution, ultimately forming a photoresist protective film on the substrate that matches the designed pattern, covering the circuitry, PADs, teardrops, and heat dissipation PAD areas.

[0033] In other words, this photolithography process can transfer patterns containing complex teardrop curves and micro-openings onto the copper surface with high fidelity, ensuring that the structure formed by subsequent etching is completely consistent with the design intent. In particular, it ensures the realization of a smooth transition shape of the teardrop, which is a key prerequisite for exerting its stress dispersion function.

[0034] S150. The substrate with the pattern is etched to remove the copper layer that is not protected by photoresist, so that the inner layer circuit is physically formed on the substrate. Specifically, the developed substrate is fed into the etching line and sprayed with an acidic or alkaline etching solution (such as copper chloride solution) to dissolve the exposed copper layer not covered by photoresist, leaving only the protected circuit pattern. The etching process requires strict control of time, temperature, and spray pressure to avoid "undercutting," which can cause the teardrop root to narrow or the line width to be lost.

[0035] In other words, precise etching ensures that the teardrop structure has the geometry and size required by the design, maintaining its mechanical strengthening effect; at the same time, it ensures the consistency of circuit impedance and the stability of electrical performance.

[0036] S160. Clean the etched substrate and use an automatic optical inspection device to inspect the cleaned substrate. Identify and screen out defective products with defects in circuits, connection PADs, teardrop structures or heat dissipation PADs. Qualified products are the inner layer circuit finished products.

[0037] Specifically, after etching, the substrate undergoes film removal and cleaning before being sent to an AOI (Automated Optical Inspection) system. The AOI system scans the entire inner layer pattern using a high-resolution camera and performs pixel-level comparisons with standard CAM data to automatically identify any defects: Teardrop missing, broken, or missized; The connection pad has a hole or the ring width is insufficient; The opening of the heat dissipation PAD is blocked or the conduction path is insufficient; Short circuit, open circuit, or residual copper in the circuit.

[0038] Substrates with any of the above defects are marked as defective and rejected; the rest are qualified inner layer circuit products.

[0039] In other words, AOI inspection achieves 100% automated quality control of critical reliability structures (especially teardrop and heat dissipation PADs), significantly reducing the risk of human error in inspection and ensuring that the inner layer boards leaving the factory have high connection reliability, providing a solid foundation for subsequent multilayer lamination and long-term stable operation of the whole machine.

[0040] In one embodiment, when generating the teardrop-shaped gradient widening structure, the teardrop generation plugin in the CAD design software is called, and the teardrop parameters are set according to the quantitative specifications to achieve automated generation. After generation, the transition effect between the teardrop and the connecting PAD and inner layer circuitry is verified.

[0041] Specifically, after completing the initial routing of the PCB inner layers (including the placement of traces, vias, and connecting pads), the built-in or third-party integrated "Teardrop Generator" plugin in the Electronic Design Automation (EDA) software (such as Altium Designer, Cadence Allegro, MentorXpedition, etc.) is launched. This plugin is usually embedded in the routing environment in the form of scripts, macros, or graphical tools, and can perform teardrop addition operations in batches for all eligible connection nodes (i.e., the intersection of traces and via pads).

[0042] Before or during the plugin call, the user needs to input or select a set of quantitative parameters in the plugin interface according to the pre-defined process and reliability design specifications. These parameters mainly include: Teardrop length L: refers to the distance along the direction of the line from the end of the line to the widest part of the teardrop.

[0043] Teardrop maximum width T: refers to the dimension of the widest part of the teardrop perpendicular to the routing direction.

[0044] Teardrop shape type: You can choose from curved (smooth Bézier curve), straight conical or mixed type. Curved type is usually preferred to achieve uniform stress distribution.

[0045] Applicable object selection criteria: For example, only generate teardrops for nodes with line width ≤ 6mil, connection PAD diameter ≤ 0.6mm, or located in high stress areas of BGA / CPU, to avoid redundant addition in non-critical areas.

[0046] The plugin automatically scans the entire inner layer design based on the above parameters, identifies all trace-PAD connection points that meet the preset conditions, and automatically generates a teardrop copper foil pattern that conforms to geometric specifications at each connection point. This process eliminates the need for manual hand-drawing and can complete the addition of teardrops for thousands of connection points on the entire board in seconds to minutes, significantly improving design efficiency.

[0047] After a teardrop is generated, the system can automatically perform the following verification steps: DRC (Design Rule Check): Verifies that all teardrops meet electrical rules such as minimum spacing, minimum line width, and no short circuits with adjacent elements; Visual verification: By zooming in and out, view the teardrop shape of typical areas (such as high-density BGA areas and thin-line width areas) to confirm that it forms a smooth, continuous, and non-sharp-angled transition with the traces and PADs; Simulation-assisted verification: In high-reliability products, the teardrop-shaped local structure can be imported into thermo-mechanical coupling simulation software (such as ANSYS) to evaluate whether its stress distribution under thermal cycling is significantly better than that of traditional right-angle connections.

[0048] If individual teardrops are found to be deformed or overlapping due to space constraints, they can be manually adjusted in local wiring or fine-tuned in parameters and then regenerated.

[0049] In other words, by using parameterized automatic generation based on quantitative specifications, problems such as inconsistent sizes and irregular shapes caused by experience differences, fatigue, or negligence in traditional manual teardrop drawing are avoided. This ensures that all teardrops on the entire board are highly uniform in geometry and size proportions, providing a stable and reliable graphic foundation for subsequent manufacturing. Furthermore, automated plug-in can complete the addition of large-scale teardrops in a very short time, especially suitable for highly complex PCBs with thousands of PTH connection points (such as server motherboards and communication backplanes). This not only shortens the design cycle but also reduces the risk of human error in missing critical connection points, improving the first-time success rate and manufacturability. In addition, the curved teardrop shape combined with precise size control ensures that stress is distributed in a gradient across the connection area rather than concentrated at a single point. The verified smooth transition effect directly determines whether it can effectively suppress copper foil cracking in actual manufacturing processes (such as lamination thermal stress and drilling impact) and operating environments (such as temperature cycling and vibration), thereby fundamentally improving the long-term reliability of PTH inner layer connections.

[0050] In one embodiment, the length L of the teardrop structure along the inner layer trace direction satisfies the following condition: L is not less than the line width W of the inner layer trace, and not greater than 1.5 times the diameter D of the connecting PAD pad.

[0051] Specifically, in the PCB inner layer circuit design phase, two basic parameters are first defined: Inner layer line width W: Determined based on current carrying capacity, impedance control requirements, and process capabilities (such as minimum etch line width), with common values ​​ranging from 3mil (0.076mm) to 8mil (0.203mm). The diameter D of the PAD pad is determined by the diameter of the drill bit used for drilling (e.g., 0.25mm) plus the requirement of the annular ring (usually ≥0.15mm per side). Therefore, D is generally 0.55mm to 0.8mm.

[0052] According to the technical specifications of this solution, when configuring the teardrop generation plugin in the CAD design software, a double boundary constraint is applied to the extension length L of the teardrop along the routing direction: Lower limit constraint: L≥W, to ensure that the teardrop has a sufficient transition area and avoids the inability to form an effective stress buffer due to insufficient length; Upper limit constraint: L≤1.5×D, to prevent teardrops from excessively extending and intruding into adjacent traces, vias or component pads, causing DRC (Design Rule Check) violations or physical short circuit risks.

[0053] In practical engineering applications, one of the following two preferred ranges is used for automation setup (typically selected based on wiring density and reliability level): The preferred range based on linewidth is: L = (1.5~3.0)×W. This is suitable for high-density wiring areas (such as under BGAs and around fine-pitch ICs). In this case, W is relatively small (such as 4mil). Even if the upper limit of 3.0×W (12mil≈0.305mm) is taken, the teardrop length can still be controlled, which can provide sufficient transition area without significantly encroaching on the limited wiring channel. The preferred range based on pad diameter is: L = (0.5~1.0)×D. This is suitable for medium-low density areas or high-current routing scenarios, where D is relatively large (e.g., 0.7mm). 0.5D (0.35mm) can form an effective teardrop, while 1.0D (0.7mm) is used for high reliability requirements (e.g., power plane, high-frequency signal vias).

[0054] When calling the teardrop plugin, you can specify the appropriate L calculation strategy for different network types (such as signal, power, ground) or different regions (high-density areas vs. sparse areas) to achieve differentiated optimization.

[0055] After the teardrop is automatically generated, the system automatically performs space analysis: Check whether the distance between the tip of the teardrop and adjacent traces, vias, test points or out-of-cover areas is less than the minimum safe distance (e.g., 4 mil). If a potential conflict exists, L will be automatically reduced to the maximum allowable value that does not violate the spacing rules, or manual intervention will be prompted to adjust the local wiring. For extremely crowded areas, teardrop generation can be temporarily disabled, or a "micro teardrop" (which only satisfies L=W) can be used as a compromise.

[0056] In other words, by strictly limiting L to between W and 1.5D, and preferably within a narrower range of (1.5–3.0)W or (0.5–1.0)D, the teardrop is ensured to extend only within the necessary range. For example, when W=4mil and D=0.6mm (≈24mil): if L is arbitrarily set to 1.0mm (≈40mil) according to conventional experience, it is very easy to conflict with the surrounding structure; while the preferred L=2.5×W=10mil (0.254mm) or L=0.7×D≈17mil (0.43mm) is much smaller than 1.5D (36mil) and provides a sufficient stress transition zone. This fine control reduces the risk of wiring congestion in high-density areas. In addition, excessively long teardrops may cause the copper foil to "creep" into adjacent conductors during photolithography or etching due to film collapse, uneven development, or side etching effects, forming micro-short circuits. By limiting L≤1.5D and combining it with DRC verification, such hidden dangers are eliminated from the design source, improving manufacturing yield.

[0057] In one embodiment, the width T of the teardrop structure along the vertical routing direction satisfies the following conditions: T is not less than the width W of the inner layer routing line, and satisfies any of the following upper limits: T≤1.3×W; or T≤0.8×D.

[0058] Specifically, the maximum width of the teardrop structure perpendicular to the trace direction is denoted as T. According to the technical specifications of this solution, T must simultaneously meet the following conditions: Lower limit requirement: T≥W, to ensure that the teardrop is not narrower than the original trace in the lateral direction, so as to avoid forming a "bottleneck" that weakens the conductivity or mechanical properties; Upper limit dual selection condition (meeting either one is sufficient): Condition 1: T≤1.3×W; Condition 2: T≤0.8×D.

[0059] This means that the actual value of T must not exceed the smaller of the two upper limits mentioned above, provided that T≥W, or the upper limit can be actively chosen according to the design strategy.

[0060] When using teardrop generation plugins (such as Altium Designer's "Teardrops" feature or CadenceAllegro's "Pad-to-Trace Connect" optimization module), the following rules need to be configured in the parameter settings interface: Enable the "Adaptive Width Control" option; Enter typical values ​​or allowed ranges for W and D; Select the "Prioritize linewidth limitations" or "Prioritize pad size limitations" strategy.

[0061] The software will dynamically calculate the maximum allowable value of T based on the actual W and D values ​​of each connection point, and generate a teardrop profile that conforms to the constraint.

[0062] For example: If W = 4 mil (0.102 mm), D = 0.6 mm (≈24 mil): 1.3 × W = 5.2 mil, 0.8 × D ≈ 19.2 mil → Taking the more stringent 1.3 × W as the upper limit, therefore T ∈ [4 mil, 5.2 mil]; If W = 8 mil (0.203 mm), D = 0.5 mm (≈20 mil): 1.3 × W = 10.4 mil, 0.8 × D = 16 mil → still limited to 1.3 × W; If W=10mil, D=0.4mm (≈16mil, for small drilling scenarios): 1.3×W=13mil, 0.8×D≈12.8mil → At this point, 0.8×D is more stringent, and the upper limit of T is 12.8mil.

[0063] After a teardrop is generated, the system automatically performs the following checks: Check whether the distance between the widest part of the teardrop and adjacent traces, vias, test points or out-of-wiring areas is less than the minimum safe distance (e.g., 4 mil). If generating T according to the theoretical upper limit would result in a spacing violation, T will be automatically reduced to a compliant value, or marked as an area requiring manual review. For high-density areas (such as BGA fan-out areas), a T≤1.3×W strategy can be preset to maximize the preservation of lateral routing channels.

[0064] In other words, in high-density PCBs, trace spacing is often compressed to 4-5 mil. If the teardrop width T expands unrestricted to both sides (as in traditional designs, it may reach 1.5W or even larger), it can easily intrude into adjacent networks, causing short circuits or DRC violations. By setting T ≤ 1.3 × W (i.e., a maximum expansion of 0.15W on one side), the lateral encroachment is controlled within a very small range (for example, when W = 4 mil, T is only 5.2 mil at most, a single-side increase of 0.6 mil), reducing the risk of wiring interference. In addition, in microvia or fine-pitch applications (such as HDI boards using a 0.2mm drill bit, D ≈ 0.5mm), if T is controlled only according to the trace width ratio, a large W (such as 8 mil) may result in T = 10.4 mil > 0.8 × D (≈ 16 mil × 0.8 = 12.8 mil), which may seem safe. However, in extreme cases (e.g., D=0.4mm, 0.8D=12.8mil), if W=12mil, then 1.3W=15.6mil>0.8D. In this case, if T≤0.8D is not limited, the teardrop may exceed the effective coverage area of ​​the pad, forming a suspended copper wing after etching, which is prone to breakage during subsequent lamination or thermal shock. Introducing T≤0.8×D as a second upper limit ensures that the teardrop always falls completely within the pad projection area, guaranteeing pattern integrity and connection strength. Furthermore, T≥W ensures that the cross-sectional area of ​​the teardrop region is not less than the original trace, avoiding increased resistance, accelerated temperature rise, or excessive current density due to local necking. Simultaneously, moderate widening (up to 1.3W) can slightly improve local current carrying capacity, providing auxiliary heat dissipation for power supplies or high-current signal paths without causing manufacturing defects due to excessive widening.

[0065] In one embodiment, the opening width of the heat dissipation PAD is not less than 5 mil, and the radial length is not less than 6 mil.

[0066] Specifically, to avoid "cold soldering" or delamination due to excessive heat capacity during the welding or lamination of large-area solid copper foil, while taking into account the requirements of electrical connection and heat conduction, an open structure is adopted—that is, several symmetrically distributed slits (called "openings" or "thermal spokes") are opened radially on the circular or square pads, making the pads "petal-shaped" or "cross-shaped".

[0067] Spoke Width: This refers to the width of the copper foil bridge between the outer edge of each connecting pad and the center hole (or the inner layer trace connection point), measured tangentially along the circumference, in mils (1 mil = 0.0254 mm). This invention specifies that it should not be less than 5 mils (≈0.127 mm). Radial Length (Spoke Length): refers to the length of the copper foil bridge from the outer edge of the pad to the edge of the center hole (or the connection start point), measured along the radial direction, and specified to be not less than 6mil (≈0.152mm).

[0068] During the PCB design phase, when setting inner layer pad properties using EDA tools (such as Altium Designer, Cadence Allegro, etc.), select the "Thermal Relief" type and enter the following parameters: Total diameter D of the pads (e.g., 0.6mm); Number of openings (usually 4, symmetrically distributed at 90°); Each copper foil bridge (spoke) is ≥5mil wide; Each copper foil bridge has a radial extension length ≥6mil from the outer ring to the inner hole.

[0069] The software will automatically generate a standard open-type heat dissipation PAD pattern based on this. For example, if D=0.6mm (≈24mil) and the center hole diameter is 0.3mm (≈12mil), then the remaining ring width is (24-12) / 2=6mil, and the radial length is exactly 6mil, which meets the lower limit requirement. If a larger radial length is required, the pad diameter needs to be increased or the hole diameter needs to be reduced.

[0070] After the design is completed, the system will automatically run DRC for key verifications: Are the copper foil bridge widths of all heat dissipation PADs ≥ 5mil? Is the radial projection length of the copper foil bridge ≥ 6 mil? Whether the spacing between each copper foil bridge and with adjacent conductors meets the minimum safe distance (e.g., 4mil). At the same time, send the Gerber file to CAM for manufacturing capability assessment to confirm that a width of 5mil and a length of 6mil can be stably etched and formed under the current process (e.g., minimum linewidth / spacing capability of 3mil) without the risk of broken bridges or short circuits.

[0071] In other words, the 5mil width limit ensures that each copper foil bridge has a sufficient cross-sectional area. Based on a typical 1oz (35μm) copper thickness, the cross-sectional area of ​​a single 5mil × 35μm conductor is approximately 0.0045mm². 2 Four parallel lines can achieve a thickness of 0.018mm. 2The width is sufficient to carry several amperes of current (according to the IPC-2152 temperature rise profile), meeting the connection requirements of most signals and small to medium power supplies. If the width is less than 5 mil (e.g., 3 mil), "necks" or even open circuits are prone to occur under etching deviations (±10%) or excessive micro-etching, especially after multiple thermal cycles due to accelerated electromigration failure. Setting 5 mil as the lower limit provides a safety margin for process fluctuations and improves long-term electrical reliability. In addition, the 6 mil radial length lower limit ensures that heat can be effectively conducted from the central hole area to the outer ring pads and further diffused to the inner power / ground plane. If the radial length is too short (e.g., <4 mil), the thermal resistance increases significantly, causing heat to be unable to dissipate in time during soldering, easily leading to cold solder joints; and during equipment operation, the heat generated by the chip cannot be efficiently dissipated, causing excessive local temperature rise; at the same time, the opening structure itself retains about 50% to 70% of the copper connection area (depending on the number and width of the openings), which, while limiting the heat capacity, still provides sufficient heat path to achieve "controllable heat dissipation" rather than "complete thermal insulation".

[0072] In one embodiment, in the BGA or CPU hole area, at least two conductive paths are maintained between the heat dissipation PAD and GND, and the width of each conductive path is not less than 5mil.

[0073] Specifically, in PCB design, the area containing the BGA (Ball Grid Array) or CPU (Central Processing Unit) is first identified as a critical region for high-density interconnects and high heat flux. These areas typically contain densely packed PTHs (Plasma Through-Hole) for signal, power, and ground connections. For ground vias connected to the inner GND plane, the corresponding inner layer pads use open-type thermal relief pads instead of solid pads to balance solderability and thermal management.

[0074] For each grounding heat dissipation PAD in the aforementioned critical areas, the following is mandated: The number of conductive paths (i.e., copper foil bridges, spokes) is ≥2: usually a symmetrical layout is adopted (such as 2 bridges facing each other at 180°, or 4 bridges distributed at 90°) to ensure current path redundancy; The width of each conductive path is ≥5mil (≈0.127mm): This width refers to the minimum line width of the copper connection segment along the circumference tangentially; The conductive path must be directly connected to the complete inner GND plane and must not be interrupted, narrowed, or isolated by other networks.

[0075] In other words, at least two independent conductive paths are set up to create current path redundancy. Even if one path partially breaks due to manufacturing defects (such as excessive micro-etching, dry film pinholes) or long-term thermal stress fatigue, the other path can still maintain the GND connection, avoiding "floating ground" or impedance abrupt changes, thereby ensuring signal integrity (SI) and power integrity (PI). In addition, each copper bridge with a width of ≥5mil (with a copper thickness of 1oz) can carry approximately 1 to 1.5A of current (according to IPC-2152 temperature rise standard). Two in parallel can support 2 to 3A, fully meeting the return current requirements of high-frequency switching current in the BGA / CPU area. At the same time, the increase in the total conductive cross-sectional area effectively reduces the DC resistance and high-frequency inductance of the grounding path, suppressing ground bounce and EMI noise.

[0076] In one embodiment, when dimensionally verifying the film, an optical inspection device is used to verify the dimensional accuracy of the connecting PAD, teardrop structure, and heat dissipation PAD on the film, so as to reject unqualified films.

[0077] Specifically, the dimensional accuracy of the connecting PAD, teardrop structure, and heat dissipation PAD on the film is verified using optical inspection equipment, including the following steps: 1. Before formal testing, a standardized calibration procedure must be performed on the high-precision optical inspection equipment (such as an automated optical inspection (AOI) system or a dedicated film measuring instrument): Verify the device's resolution (typically ≥1μm / pixel), repeatability (≤±0.5μm), and grayscale contrast sensitivity using NIST-traceable standard calibration patches (containing known line width, spacing, circle diameter, and other micron-level features); The film to be inspected (usually a 1:1 scale photoplotting film made of polyester film) is flattened and fixed using a vacuum adsorption platform or stress-free clamp to avoid image distortion caused by wrinkles or warping. Extract theoretical geometric data for connection pads, teardrop structures, and heat dissipation pads from PCB design databases (such as Gerber, ODB++, or IPC-2581 format), including: PAD diameter / shape, hole position coordinates; The teardrop's length L, width T, and transition curvature; The number of openings, spoke width (≥5mil), and radial length (≥6mil) of the heat dissipation PAD; At the same time, the tolerance standards specified by the enterprise or customer (such as line width tolerance ±10%, position tolerance ±25μm, roundness deviation ≤15μm, etc.) are imported as the basis for judgment.

[0078] 2. After the equipment is started, its high-resolution linear or area array CCD / CMOS camera, in conjunction with a precision motion platform, automatically scans the entire film (common size such as 24"×28") line by line or section by section: Use backlighting or coaxial illumination modes to enhance the contrast between the copper graphic and the transparent substrate; Set the resolution to be sufficient to identify the smallest features (e.g., a 3mil line width requires ≥5μm / pixel); Key areas (such as BGA / CPU via areas and high-frequency signal trace areas) can be set to local magnified scanning to improve detail capture capabilities; The system synchronously acquires complete image data of the connected PAD, teardrop, heat dissipation PAD and its surrounding traces, vias, solder mask openings and other related structures, and constructs a high-fidelity digital mapping.

[0079] 3. Based on the acquired images, the device's built-in algorithm performs multi-dimensional geometric measurements and comparisons: Connecting PADs: Measure the actual diameter, center position, and edge roughness, and compare them with the design values ​​to check whether the requirements of the annular ring are met; Teardrop structure: Automatically identify the starting point and end of the teardrop, measure the length L along the path direction (verify whether W≤L≤1.5D and the preferred range are satisfied), the width T in the vertical direction (verify T≥W and T≤min(1.3W, 0.8D)), and analyze the continuity and smoothness of the transition curve; Heat dissipation PAD: Identify the number of each spoke, measure the width of each spoke (whether it is ≥5mil) and the radial extension length (whether it is ≥6mil), and verify that it is symmetrically distributed and not cut by adjacent graphics; At the same time, verify whether the relative positions and spacing between the three types of structures conform to the DRC rules (such as the distance from PAD to the teardrop starting point, the gap between the heat dissipation PAD and the adjacent trace, etc.).

[0080] 4. The system compares the measured data with the design tolerance limits in real time and automatically identifies the following typical defects: Dimensional deviations: e.g., teardrop L=1.6D (exceeding the 1.5D upper limit), heat dissipation PAD copper foil bridge (spoke) width=4.2mil (less than 5mil); Position offset: The PAD center offset exceeds ±25μm in design coordinates; Graphical distortion: The teardrop outline appears jagged, broken, or asymmetrically bulged; Structural defects: The heat dissipation PAD should have 4 spokes, but only 2 were actually generated; For each anomaly, the system marks the location with a colored highlight box on the digital image and overlays the deviation value (e.g., "Spoke Width: 4.3mil (Δ=-0.7mil)"), generating a defect list.

[0081] 5. The automatic detection results are submitted to the quality control engineer for a second review: Examine the marked areas one by one on a high-magnification monitor to rule out false alarms (such as false defects caused by dust or scratches). Manually fine-tune measurements to confirm critical values ​​(e.g., 5.01 mil vs. 5.00 mil); Once approved, the system automatically generates a structured validation report, which includes: Film serial number, product model, and testing date; Measured data table of key structures; Defect distribution map and statistical summary (such as pass rate, major failure modes); Electronic signatures for operators and auditors; All original images, measurement logs, and report files are encrypted and archived to meet ISO 9001 or IATF 16949 traceability requirements.

[0082] 6. Implement closed-loop management based on the judgment results: Unqualified film: Label it "Reject" and return it to the photoplotting department for analysis of the cause (such as laser exposure parameter drift or insufficient development time), re-output a new film and resubmit it for inspection; Qualified film: Affix a unique QR code label, record the release time and responsible person, and automatically trigger the release of the work order for the next process (such as inner layer graphic transfer, alignment exposure); The system synchronously updates the MES (Manufacturing Execution System) status to ensure that non-conforming products cannot flow into subsequent processes.

[0083] In other words, this solution improves the dimensional control accuracy of key structures such as connecting pads, teardrops, and heat dissipation pads to the ±2-5μm level through high-resolution optical inspection and automated comparison. This ensures that each film strictly conforms to the design intent, fundamentally eliminating manufacturing defects such as internal layer short circuits, open circuits, and impedance deviations caused by film distortion. Furthermore, if problems such as insufficient teardrop length or missing heat dissipation pad pathways are not detected during the film production stage, they will form irreparable internal layer defects after lamination, leading to the scrapping of the entire board.

[0084] In one embodiment, when cleaning the etched substrate, deionized water is used to perform multiple cleaning operations.

[0085] Specifically, the characteristics of the objects to be cleaned and the sources of contamination should be clearly defined: After the etching process, the following contaminants may remain on the surface and in the microstructure of the PCB substrate (usually a copper-clad laminate after pattern transfer, acidic or alkaline etching): Etching solution components: such as copper chloride, ferric chloride, ammonia complex, etc., which are highly corrosive and conductive; Photoresist (dry or wet film) residue: polymer fragments that have not been completely removed, especially prone to getting stuck in high-density line gaps, BGA pad edges or teardrop transition areas; Metal ion byproducts: such as Cu 2+ Fe 3+ Sn 2+ In subsequent high-temperature or humid environments, these substances can undergo catalytic oxidation or electrochemical migration; Particulate impurities: dust, fibers, organic debris, etc., from equipment, air, or previous processes.

[0086] If these residues are not removed, they will seriously affect subsequent solder resist printing, surface treatments (such as immersion gold and OSP), soldering reliability, and long-term insulation performance.

[0087] High-purity deionized water is selected as the cleaning medium: the entire cleaning process uses deionized water with a resistivity ≥15MΩ·cm (preferably ≥18.2MΩ·cm), which has the following characteristics: Almost no Na + Ca 2+ Cl - SO4 2- Plasma impurities are eliminated to prevent secondary contamination. It has low surface tension and good wettability, and can effectively penetrate into micron-level line gaps; Inorganic salts have strong dissolving power and can efficiently dilute and remove etching byproducts.

[0088] Constructing a multi-stage, series-connected cleaning process: Cleaning is not a single operation, but is completed through a multi-tank, multi-stage, counter-current automated cleaning line. A typical process is as follows: First stage: Pre-rinse (rough wash) Use room temperature (20-25℃) deionized water to spray or immerse, quickly rinse away most of the free etching solution and large particles of residue, with a large water flow rate (e.g., 2-3L / min / board) and a time of about 30-60 seconds; Level 2: Main cleaning (fine cleaning) Use deionized water heated to 40-50°C (heating can reduce viscosity and enhance dissolution and diffusion rate), combined with ultrasonic waves (frequency 28-40kHz) or a high-pressure fan nozzle (pressure 0.2-0.4MPa), to thoroughly remove stubborn adhesive residue and metal salt crystals from the bottom of the circuit, the hole walls, and the edges of the PAD for 60-90 seconds. Third stage: Final rinsing (high-purity rinsing) Use fresh, low-temperature (≤25℃), high resistivity (≥18MΩ·cm) deionized water for static soaking or low-disturbance spraying to replace the trace ions remaining in the first two stages and prevent water marks or salt crystallization after drying. The time is 30-60 seconds. Implementation of process parameter monitoring and water quality management: Each cleaning tank is equipped with an online conductivity meter and pH sensor to monitor water quality in real time. The electrical conductivity of the pre-wash tank is ≤50μS / cm; Main washing tank ≤20μS / cm; Final rinsing tank ≤1μS / cm (corresponding to resistivity ≥1MΩ·cm, ideally ≤0.1μS / cm, corresponding to resistivity ≥10MΩ·cm); Regularly replace or regenerate deionized water; the water replacement program is automatically triggered based on the cumulative number of treated plates or when the water quality exceeds the standard. After cleaning, the water contact angle on the substrate surface is ≤30°, which is used as the standard for judging that the substrate surface has good hydrophilicity and no hydrophobic organic residue.

[0089] Supported drying and clean transfer: After cleaning, the substrate is immediately placed in the hot air drying section (temperature 70-90℃, wind speed 2-3m / s) or vacuum drying chamber to ensure no water stains remain; then it is transferred to the next process (such as AOI inspection, solder mask printing) in a Class 10000 or higher cleanliness environment to prevent recontamination.

[0090] In other words, Cl in the etching solution - NH4 + If plasma residue remains on the substrate, it can form electrolyte channels in a humid environment, inducing electrochemical migration (ECM) and leading to dendrite growth and short-circuit failure between adjacent lines. Repeated deionized water rinsing can reduce the ion concentration to the ppb level, improving the product's lifespan in high-temperature and high-humidity environments.

[0091] In one embodiment, when using an automated optical inspection device for inspection, the substrate image is compared with standard CAM data to identify defects such as dimensional deviations, broken connections, short circuits, or incomplete patterns in the circuitry, connection pads, teardrop structures, or heat dissipation pads.

[0092] Specifically, the comparison steps are as follows: 1. Preparation and preprocessing of standard CAM data Before AOI inspection, reference data for comparison is first extracted and standardized from the PCB design stage: Export theoretical graphic data of inner or outer layers from original design files (such as Gerber RS-274X, ODB++, IPC-2581, etc.), including geometric information such as traces, pads, vias, teardrops, and thermal relief pads for all copper layers. The CAM data is compensated by adding process compensation values ​​(such as line width +10%, hole diameter -0.05mm) based on the current process capabilities (such as etching factor, minimum line width / spacing, and alignment tolerance) to generate an "expected manufacturable pattern" as a comparison benchmark. The baseline data is converted into a high-precision vector template or pixel-level Golden Image that can be recognized by AOI equipment. The resolution is usually matched or higher than that of the actual detection image (e.g., 1μm / pixel).

[0093] 2. High-fidelity acquisition of substrate images After the substrate to be inspected (which has undergone pattern transfer, etching, and film removal processes) is sent into the AOI equipment, the following imaging operations are performed: The substrate is fixed by a vacuum adsorption platform to ensure it is flat and free of warping; A high-resolution line scan camera (CCD / CMOS) combined with a precision motion control system scans the entire board line by line. Multi-angle lighting (coaxial lighting, low-angle oblique lighting, and backlighting) is used to enhance the contrast of different features: Coaxial light highlights the outline of the copper pattern on the surface; Oblique light highlights minute notches, burrs, or height differences; Backlight assists in identifying transparent areas (such as the edge of solder mask openings); The image resolution is set to be able to clearly distinguish the smallest design features (e.g., ≥5μm / pixel for a 3mil linewidth), typically ranging from 1 to 10μm / pixel. The system synchronously records the physical coordinates of each image, constructing a high-precision digital mapping of the entire board.

[0094] Intelligent comparison and analysis of images and CAM data The core algorithm of the AOI system performs multi-dimensional and multi-level comparisons between the measured images and standard CAM templates, focusing on the following structural and defect types: Trace: Measure the actual line width and spacing to determine if they exceed the tolerance (e.g., if the design is 4mil, but the actual measurement is <3.5mil, it is considered a "thin line"). Detecting for open circuits: a lack of continuous copper in the middle of the circuit; Identify a short circuit: There is an unwanted copper bridging between adjacent lines.

[0095] Connect the PAD (Pad): Verify the diameter, shape, and position offset (alignment with the drilling center); Check for insufficient annular ring or missing PAD.

[0096] Teardrop structure: Automatically identify the starting and ending points of the teardrop, and measure the length L, width T, and transition arc; Determine whether it is not generated, insufficient in size (e.g., L < W), or asymmetrically fractured.

[0097] Thermal Relief PAD: Identify the number of spokes, width (whether ≥ 5 mil), and radial length (whether ≥ 6 mil); Detect whether there are missing spokes, cut off by adjacent traces, or asymmetric openings.

[0098] Missing Feature: The entire pad, teardrop, or a group of spokes are completely undeveloped or over-etched and disappeared.

[0099] Defect classification, location, and visual marking The system makes intelligent judgments on suspected abnormalities based on a preset rule library and machine learning models (such as CNN classifiers): Distinguish real defects from process noise (such as minor burrs, water stain reflections); Classify the confirmed defects by type (Open / Short / Missing / Size Error), and accurately mark the positions on the image with colored boxes (e.g., red = short circuit, blue = open circuit); Output deviation values (such as "Line Width: 3.2 mil (Design: 4.0 mil, Δ = -0.8 mil)"); Generate a heat map of defect distribution to assist process analysis.

[0100] 5. Manual review and result output The initial AOI inspection results are handed over to the quality inspection engineer for review on a high-resolution workstation, which can be magnified up to 200 times to view details and avoid false alarms (such as dust, scratches); After confirmation, the system automatically generates a structured inspection report, including: Board number, layer, inspection time; Defect list (type, coordinates, severity level); Full-board defect distribution map; Pass / Fail determination; Data is synchronously uploaded to the MES / QMS system, supporting SPC statistics and traceability.

[0101] In other words, by intelligently comparing high-resolution measured images with standard CAM data after process compensation, an automated, high-precision, and traceable defect identification system covering key elements such as circuits, PADs, teardrops, and heat dissipation PADs has been constructed. This not only realizes the upgrade of the quality control paradigm from "human eye judgment" to "data-driven", but also plays an irreplaceable "quality gate" role in the manufacturing of high-density, high-performance, and high-reliability PCBs.

[0102] In one embodiment, the teardrop structure is used to disperse the stress generated at the connection between the PTH via and the inner layer circuitry during drilling, electroplating, and thermal cycling.

[0103] Specifically, by introducing a teardrop structure with specific geometric parameters at the connection between the PTH hole and the trace, the stress distribution during manufacturing and use is actively intervened from the perspective of mechanical design. This not only solves the structural fragility problem under the coupling effect of multiple physical fields such as drilling, electroplating, and thermal cycling, but also becomes a core design element supporting the manufacturing of high-density, high-performance, and high-reliability PCBs.

[0104] The aforementioned design and fabrication method for the inner layer circuitry of printed circuit boards (PCBs) fundamentally solves the core problem of weak and easily broken connections between PTH vias and inner layer circuitry in high-density PCBs through a three-pronged technical approach of "structural optimization + process collaboration + precise control," without significantly increasing the wiring area. It not only improves the product's mechanical strength, electrical reliability, and thermal management capabilities, but also ensures high yield and consistency in large-scale production through standardized and automated processes, perfectly aligning with the current industry trend of miniaturization, high integration, and high reliability in electronic devices.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for designing and fabricating inner layer circuitry of a printed circuit board, characterized in that, include: The drilling parameters are determined according to the product design requirements, and the basic dimensions of the connecting PAD are set based on the drilling parameters, wherein the film diameter of the connecting PAD is more than 0.3mm larger than the diameter of the drill bit used for drilling. A teardrop-shaped, gradually widened structure is generated in the transition area between the connection PAD and the inner layer circuitry, which has a set basic size. This teardrop structure changes the connection between the circuitry and the connection PAD from point contact to surface contact. At the same time, the structure of the open heat dissipation PAD is designed to complete the inner layer circuitry design. The output wiring design forms an inner layer circuit film, and the dimensions of the circuit, connection PAD, teardrop structure and heat dissipation PAD on the film are verified; at the same time, the PCB inner layer substrate is pre-treated, which includes degreasing, roughening, water washing and drying processes in sequence. The qualified film is aligned with the inner substrate that has been pre-treated and coated with photoresist. Through ultraviolet light exposure and development, a pattern of lines, connecting PADs, teardrop structures and heat dissipation PADs protected by photoresist is formed on the substrate. The substrate with the pattern is etched to remove the copper layer that is not protected by photoresist, so that the inner layer circuitry is physically formed on the substrate. The etched substrate is cleaned and inspected using an automated optical inspection device. Defective products with defects in circuitry, connection pads, teardrop structures, or heat dissipation pads are identified and screened. Qualified products are the finished inner layer circuitry.

2. The method for designing and fabricating inner layer circuits of a printed circuit board according to claim 1, characterized in that, When generating the teardrop-shaped gradient widening structure, the teardrop generation plugin in the CAD design software is called, and the teardrop parameters are set according to the quantitative specifications to achieve automated generation. After generation, the transition effect between the teardrop and the connecting PAD and inner layer circuitry is verified.

3. The method for designing and fabricating inner layer circuits of a printed circuit board according to claim 1, characterized in that, The length L of the teardrop structure along the inner layer trace direction satisfies the following conditions: L is not less than the line width W of the inner layer trace, and not greater than 1.5 times the diameter D of the connecting PAD pad.

4. The method for designing and fabricating inner layer circuits of a printed circuit board according to claim 3, characterized in that, The width T of the teardrop structure along the vertical routing direction satisfies the following conditions: T is not less than the width W of the inner layer routing line, and satisfies any of the following upper limit conditions: T≤1.3×W; or T≤0.8×D.

5. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 1, characterized in that, The opening width of the heat dissipation PAD is not less than 5mil, and the radial length is not less than 6mil.

6. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 5, characterized in that, In the BGA or CPU hole area, at least two conductive paths shall be maintained between the heat dissipation PAD and GND, and the width of each conductive path shall not be less than 5mil.

7. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 1, characterized in that, When performing dimensional verification on the film, optical inspection equipment is used to verify the dimensional accuracy of the connecting PAD, teardrop structure and heat dissipation PAD on the film, so as to reject unqualified films.

8. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 1, characterized in that, When cleaning the etched substrate, deionized water is used to perform multiple cleaning operations.

9. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 1, characterized in that, When using automated optical inspection equipment for inspection, the substrate image is compared with standard CAM data to identify defects such as dimensional deviations, broken connections, short circuits, or incomplete patterns in the circuitry, connection pads, teardrop structures, or heat dissipation pads.

10. The method for designing and fabricating inner layer circuitry of a printed circuit board according to claim 1, characterized in that, The teardrop structure is used to disperse the stress generated during drilling, electroplating, and thermal cycling at the connection points between the PTH via and the inner layer circuitry.

Images