Integrated circuit

Abstract

The embodiment of the utility model provides an integrated circuit. The integrated circuit comprises a first IC chip connected to a second IC chip. The first IC chip includes a plurality of photodetectors disposed in the first substrate and the first bonding structure. The first bonding structure includes a first plurality of bonding contacts disposed on the first plurality of conductive bonding pads. The second IC chip includes a second bonding structure and a second substrate. The first bonding interface is disposed between the first bonding structure and the second bonding structure. The second bonding structure includes a second plurality of bonding contacts. The first bonding structure also includes a first plurality of shielding structures between adjacent ones of the first plurality of conductive bonding pads. The shielding structure blocks an electromagnetic field between adjacent conductive bonding pads, thereby reducing parasitic capacitance and inductance between the conductive bonding pads of the bonding structure.

Description

Technical Field

[0001] An embodiment of the utility model relates to an integrated circuit, and in particular to an integrated circuit including a bonding structure of a shielding structure. Background Art

[0002] Many modern electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include image sensors. An image sensor includes one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation. An image sensor may include stacked chips to reduce the occupied area of ​​each pixel and increase device density. Utility Model Content

[0003] An embodiment of the utility model provides an integrated circuit including a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip includes a plurality of photodetectors arranged in a first substrate and a first bonding structure, wherein the first bonding structure includes a first plurality of bonding contacts arranged on a first plurality of conductive bonding pads. The second integrated circuit chip includes a second bonding structure and a second substrate, wherein a first bonding interface is arranged between the first bonding structure and the second bonding structure, wherein the second bonding structure includes a second plurality of bonding contacts, wherein the first bonding structure also includes a first plurality of shielding structures arranged between adjacent conductive bonding pads in the first plurality of conductive bonding pads.

[0004] An embodiment of the utility model provides a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip includes a first substrate, a first internal wiring structure on the first substrate, a first bonding structure on the first internal wiring structure, and a first pixel, wherein the first pixel includes a plurality of photodetectors arranged in the first substrate and a floating diffusion node arranged at the intersection of the plurality of photodetectors. The second integrated circuit chip includes a second substrate, a second internal wiring structure on the second substrate, and a second bonding structure arranged on the second internal wiring structure, wherein the first bonding structure contacts the second bonding structure at a first bonding interface, wherein the first bonding structure includes a first plurality of bonding contacts, a first plurality of conductive bonding pads, and a first plurality of shielding structures, wherein the first plurality of conductive bonding pads include a first conductive bonding pad directly below the floating diffusion node and a second conductive bonding pad laterally adjacent to the first conductive bonding pad, wherein the first plurality of shielding structures include a first shielding structure laterally arranged between the first conductive bonding pad and the second conductive bonding pad.

[0005] Based on the above, the shielding structure of the embodiment of the utility model is arranged between adjacent conductive bonding pads in the first bonding structure. The shielding structure blocks and / or hinders the electromagnetic field between adjacent conductive bonding pads, thereby reducing the parasitic capacitance and inductance between the conductive bonding pads of the first bonding structure. Thus, the crosstalk between adjacent conductive bonding pads is reduced. Therefore, the device features of the stacked integrated circuit device can be scaled while increasing the overall performance of the stacked integrated circuit device, such as increasing the accuracy of the image generated by the stacked integrated circuit device.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B Various views of some embodiments of a stacked integrated circuit (IC) device including a bonding structure with a shielding structure are shown.

[0008] Figure 2A and Figure 2B Shows Figure 1A and Figure 1B Various cross-sectional views of some other embodiments of stacked IC devices.

[0009] Figure 3A-3E Shows Figure 1A and Figure 1B Various top views of some other embodiments of stacked IC devices.

[0010] Figure 4A-4C Various cross-sectional views of some embodiments including stacked IC devices with shielding structures and dummy bond pads are shown.

[0011] Figure 5 Shows Figure 4A-4C A top view of some embodiments of a stacked IC device.

[0012] Fig. 6A Cross-sectional views of some embodiments of a stacked IC device are shown that include a plurality of photodetectors disposed on a first IC that is electrically coupled to a second IC chip through a bonding structure having a shielding structure.

[0013] Figure 6B Shown along Fig. 6A The line A-A' intercepts Fig. 6A A top view of some embodiments of a stacked IC device.

[0014] Figure 6C Shown along Fig. 6A The line B-B' intercepts Fig. 6A A top view of some embodiments of a stacked IC device.

[0015] Fig. 7A and Figure 7B Shows Fig. 6A Various cross-sectional views of some other embodiments of stacked IC devices.

[0016] Figure 8A-8D Circuit diagrams of some embodiments of a stacked IC device are shown that include a first IC chip electrically coupled to a second IC chip through a first bonding interface.

[0017] Figure 9-Figure 21 Various views of some embodiments of methods of forming a stacked IC device including a bonding structure with a shielding structure are shown.

[0018] Fig. 22 A flow chart is shown according to some embodiments of a method for forming a stacked IC device including a bonding structure with a shielding structure.

[0019] Description of Reference Numerals

[0020] 100a, 200a, 200b, 400a, 400b, 400c, 600a, 700a, 700b, 900, 1000, 1100, 1200, 1300, 1400a, 1500, 1600, 1700, 1800, 1900, 2000, 2100: cross-sectional view; 101: first substrate; 101b, 103b: back side; 101f, 103f, 641f: front side; 102: first IC chip; 103: second substrate; 104: second IC chip; 105: first bonding interface; 106: first bonding structure; 108: second bonding structure; 110: first dielectric structure; 111: second dielectric structure; 112: first A plurality of conductive bonding pads / conductive bonding pads; 112a: a first conductive bonding pad; 114, 132: a first plurality of shielding structures / shielding structures; 114a: a first shielding structure; 114b: a second shielding structure; 114l: an elongated shielding structure; 114s: a shortened shielding structure; 118: a first plurality of bonding contacts; 120: a second plurality of bonding contacts; 122: a conductive wire; 124: a photodetector; 126: a pixel; 126a: a first pixel; 128: a semiconductor device; 130a: a first column; 130b: a second column; 130c: a third column; 202: a second plurality of shielding structures; 204, 704: a first dielectric layer; 206: a second plurality of conductive bonding pads; 208, 706: second dielectric layer; 300a, 300b, 300c, 300d, 300e, 500, 600b, 600c, 1400b: top view; 302: first circular path; 304: first distance; 306: second distance; 307, 610: first plurality of transistors; 402: first plurality of dummy bonding pads; 404: second plurality of dummy bonding pads; 602: third IC chip; 604: first interconnect structure; 606: interconnect dielectric structure; 608: via; 611: second plurality of transistors; 611a: reset transistor; 611b: source follower transistor; 611c: select transistor; 612: floating diffusion node; 612a: first floating diffusion node; 614: Well; 618: isolation structure; 620: grid structure; 622: filter; 624: microlens; 626: first bonding dielectric structure; 628: second bonding dielectric structure; 630: second internal connection structure; 632, 708: substrate through hole / TSV; 634: third bonding structure; 636: third bonding dielectric structure; 638: third plurality of bonding contacts; 640: third plurality of conductive bonding pads; 641: third substrate; 642: third internal connection structure; 644: fourth bonding structure; 646: fourth bonding dielectric structure; 648: fourth plurality of bonding contacts; 650: third plurality of shielding structures; 651: second bonding interface; 652: third plurality of transistors; 702: dielectric structure;800a, 800b, 800c, 800d: circuit diagram; 802: ASIC; 804: circuit inside pixel; 2200: method; 2202, 2204, 2206, 2208, 2210, 2212, 2214, 2216, 2218: action; A-A', BB': line; D: diameter; L: length; RST: reset signal; TX: transmission signal; Vdd: power supply voltage; Vrst: reset voltage; W: width. ; DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the scope of the present invention. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present invention may reuse component numbers and / or letters in each example. Such repetition is for the purpose of simplifying and clearly describing the present invention, rather than for defining the relationship between various embodiments and / or configurations.

[0022] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one component or feature to another (other) component or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used therein may be interpreted in a similar manner.

[0023] A stacked complementary metal oxide semiconductor (CMOS) image sensor may include a stacked first integrated circuit (IC) chip and a second IC chip. The first IC chip includes a plurality of pixels arranged in multiple columns and multiple rows. The pixel includes a photodetector and a floating diffusion node disposed in a first substrate of the first IC chip. In addition, a transfer transistor is disposed on the first substrate and each is configured to transfer accumulated charge from the photodetector to a corresponding floating diffusion node. The first IC chip also includes a first bonding structure, which includes a first plurality of bonding contacts disposed on a first plurality of conductive bonding pads. The second IC chip includes a second bonding structure, which includes a second plurality of bonding contacts disposed on a second plurality of conductive bonding pads. The first plurality of conductive bonding pads are in contact with the second plurality of conductive bonding pads at a bonding interface. In addition, the first plurality of conductive bonding pads are electrically coupled to individual pixels in the plurality of pixels, respectively.

[0024] In one example, a plurality of readout transistors independent of the pixels are disposed on the first substrate. The readout transistors include a source-follower transistor, a reset transistor, and a select transistor, which are configured to perform a readout of the photodetector so that the charge accumulated by the photodetector from the incident radiation can be read out as a corresponding electrical signal at the output of the readout transistor (e.g., at the source / drain terminal of the select transistor). An application specific integrated circuit (ASIC) is disposed on the second IC chip and includes a plurality of semiconductor devices (e.g., transistors) configured to receive the electrical signal from the readout transistor and perform image signal processing. The plurality of semiconductor devices are electrically coupled to the first IC chip via conductive bonding pads.

[0025] During operation of the stacked CMOS image sensor, the conductive bonding pad of the first bonding structure transmits an electrical signal from the selection transistor, which corresponds to the charge magnitude accumulated by the photodetector of each pixel column by column. For example, the photodetector of the first pixel coupled to the first conductive bonding pad in the first column is read, and then the photodetector of the second pixel coupled to the second conductive bonding pad in the second column is read, and so on. Since the conductive bonding pads in the first plurality of conductive bonding pads are very close, there may be parasitic capacitance and / or parasitic inductance between adjacent conductive bonding pads. The parasitic capacitance and / or parasitic inductance generate crosstalk between adjacent conductive bonding pads. As the features of the stacked CMOS image sensor are scaled down, the crosstalk will increase. This partially reduces the overall performance of the stacked CMOS image sensor and reduces the accuracy of the image produced by the stacked CMOS image sensor.

[0026] In another example, in order to facilitate the scaling of pixels without reducing the size of the photodetector, a plurality of readout transistors may be disposed on a second substrate of a second IC chip. In this embodiment, one or more floating diffusion nodes of each pixel are directly electrically coupled to respective conductive pads of a first plurality of conductive pads. The first plurality of conductive pads are configured to transfer accumulated charge from the photodetector (e.g., via one or more floating diffusion nodes) to the gates of a plurality of source follower transistors. However, the pixels are read out on a column-by-column basis and the conductive pads of the first plurality of conductive pads are very close together, so that crosstalk may occur between adjacent conductive pads. Thus, the overall performance of the image sensor is reduced.

[0027] In addition, the first and second bonding structures each include two or more conductive bonding layers. For example, the second bonding structure has a first conductive bonding layer including a second plurality of bonding contacts and a second conductive bonding layer including a second plurality of conductive bonding pads. Having two or more conductive bonding layers in the first and second bonding structures may increase the resistivity between the first IC chip and the second IC chip and / or may increase manufacturing costs in the image sensor.

[0028] Therefore, various embodiments of the utility model relate to a stacked IC device having a bonding structure configured to reduce signal interference between adjacent conductive bonding pads. The stacked IC device includes a first IC chip stacked with a second IC chip. A plurality of pixels are arranged on the first IC chip and include a plurality of photodetectors arranged in a first substrate of the first IC chip. The first bonding structure is arranged on the first substrate and includes a first plurality of bonding contacts arranged on a plurality of conductive bonding pads. The conductive bonding pads are coupled to components and / or structures of the pixels. The plurality of conductive bonding pads are bonded to a second bonding structure of the second IC chip, wherein the second bonding structure includes a single layer of conductive bonding features. For example, the single layer of conductive bonding features can be a second plurality of bonding contacts. In addition, the first bonding structure includes a plurality of shielding structures.

[0029] The shielding structure is disposed between adjacent conductive bonding pads in the first bonding structure. The shielding structure blocks and / or hinders the electromagnetic field between adjacent conductive bonding pads, thereby reducing the parasitic capacitance and inductance between the conductive bonding pads of the first bonding structure. Thus, the crosstalk between adjacent conductive bonding pads is reduced. Therefore, the device features of the stacked IC device can be scaled while increasing the overall performance of the stacked IC device (e.g., increasing the accuracy of the image generated by the stacked IC device). In addition, by virtue of the second bonding structure including a single layer of conductive bonding features, the number of conductive structures in the stacked IC device is reduced, thereby reducing the resistivity between the first and second IC chips and reducing the manufacturing cost of the stacked IC device.

[0030] Figure 1A and Figure 1B Various views (100a and 100b) of some embodiments of a stacked IC device including a bonding structure with a shielding structure are shown. Figure 1A Shown along Figure 1B A cross-sectional view 100a of some embodiments of a stacked IC device is shown taken along line AA′ in FIG. Figure 1B Shown along Figure 1A FIG. 1 is a top view 100 b of some embodiments of a stacked IC device taken along line AA′ in FIG.

[0031] The stacked IC device includes a first IC chip 102 having a first bonding structure 106 and a second IC chip 104 having a second bonding structure 108. The first and second bonding structures (106, 108) intersect at a first bonding interface 105. The first IC chip 102 also includes a first substrate 101 and a plurality of pixels 126, each pixel 126 including a plurality of photodetectors 124 disposed within the first substrate 101. The first bonding structure 106 is disposed between the first substrate 101 and the second IC chip 104. The first bonding structure 106 includes a first plurality of conductive bonding pads 112 and a first plurality of bonding contacts 118 disposed within a first dielectric structure 110. The conductive bonding pads 112 of the first bonding structure 106 are electrically coupled to a plurality of wires 122 of the first IC chip 102 through the plurality of bonding contacts 118. In some embodiments, the first plurality of conductive bonding pads 112 are electrically coupled to the pixels 126 (e.g., through a first internal wiring structure (not shown) disposed on the first substrate 101).

[0032] The second IC chip 104 includes a second substrate 103 and a plurality of semiconductor devices 128 disposed on the second substrate 103. For example, the plurality of semiconductor devices 128 may be or include readout transistors (e.g., including one or more source follower transistors, one or more selection transistors, one or more reset transistors, etc.), logic devices, other suitable semiconductor devices, etc. The second bonding structure 108 overlies the second substrate 103 and is electrically coupled to the semiconductor device 128 (e.g., through a second interconnect structure (not shown) disposed on the second substrate 103).

[0033] The second bonding structure 108 includes a second plurality of bonding contacts 120 disposed within the second dielectric structure 111. The second plurality of bonding contacts 120 of the second bonding structure 108 are electrically coupled to a plurality of wires 122 of the second IC chip 104. The first plurality of conductive bonding pads 112 and the second plurality of bonding contacts 120 are bonded to each other at the first bonding interface 105. Therefore, the first plurality of conductive bonding pads 112 and the second plurality of bonding contacts 120 facilitate electrical coupling between the first and second IC chips 102, 104. In addition, the first and second dielectric structures (110, 111) are bonded to each other at the first bonding interface 105. Therefore, the first bonding interface 105 includes one or more dielectric to dielectric bonding interfaces and one or more conductor to conductive bonding interfaces.

[0034] The first bonding structure 106 also includes a first plurality of shield structures 114 disposed within the first dielectric structure 110 and between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112. In some embodiments, the first plurality of shield structures 114 are electrically coupled to ground (e.g., electrically coupled to 0 volts). In other embodiments, the first plurality of shield structures 114 are electrically coupled to a voltage source (not shown) that is configured to apply a voltage to the shield structures 114. In various embodiments, the first plurality of shield structures 114 are electrically floating.

[0035] like Figure 1B As shown in the top view 100b of FIG. 1 , the plurality of pixels 126 are arranged in an array, the array including a plurality of rows and a plurality of columns (130a-c). The plurality of columns (130a-c) include a first column 130a of pixels, a second column 130b of pixels, and a third column 130c of pixels. During operation of the stacked IC device, an electrical signal (e.g., voltage, current, etc.) is transmitted through the first plurality of conductive bonding pads 112 and the second plurality of bonding contacts 120 (e.g., from the photodetector 124 to the semiconductor device ( Figure 1A 128) from the first IC chip 102 to the second IC chip 104. For example, the readout operation on the plurality of pixels 126 can be completed column by column, so that the electrical signals from the pixels in the first column 130a can be read first, the electrical signals from the pixels in the second column 130b can be read second, and so on. The first plurality of conductive bonding pads 112 are configured to transmit the electrical signals from each pixel in the corresponding column (130a-c) during the readout operation. When the readout operation is performed on the pixels in a single column, the pixels in the adjacent columns can be set to a high voltage. For example, during the readout of the pixels in the first column 130a, the pixels in the second and third columns (130b-c) are set to a high voltage.

[0036] By virtue of adjacent conductive pads in the first plurality of conductive pads 112 being laterally separated from each other by one or more shielding structures 114, parasitic capacitance and inductance between adjacent conductive pads are reduced. Figure 1BAs shown, the first plurality of conductive pads 112 include a first conductive pad 112a, which is surrounded by a first subset of shielding structures 132 as part of a first plurality of shielding structures 132. The first subset of shielding structures 132 is disposed around the periphery of the first conductive pad 112a and separates the first conductive pad 112a from other conductive pads in the first plurality of conductive pads 112. The shielding structures 114 in the first subset of shielding structures 132 block and / or hinder electromagnetic fields between the first conductive pad 112a and other adjacent conductive pads. For example, the first plurality of shielding structures 114 can be electrically coupled to ground, electrically coupled to a voltage source, or electrically floated during readout of the pixel 126, thereby reducing parasitic capacitance between the conductive pads 112 in adjacent columns. In another example, the first plurality of shielding structures 114 may include a dielectric material and be configured to reduce the effective dielectric constant between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112, thereby reducing parasitic capacitance between conductive bonding pads 112 in adjacent columns. Therefore, the influence of the electrical signal transmitted by the first conductive bonding pad 112a on other adjacent conductive bonding pads in the conductive bonding pad 112 is reduced. Thus, problems caused by the proximity between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112 (e.g., problems related to crosstalk) are reduced, thereby reducing signal interference between the first and second IC chips (102, 104). As a result, the overall effectiveness of the stacked IC device is increased (e.g., the output accuracy of the stacked IC device is increased). For example, the quality of the image produced by the pixel 126 is improved by virtue of the first bonding structure 106 including a shielding structure 114 surrounding the periphery of each conductive bonding pad 112.

[0037] In addition, if Figure 1A As shown in the cross-sectional view 100a of FIG. 1 , the second bonding structure 108 includes a single layer of conductive features (e.g., a second plurality of bonding contacts 120). Therefore, the layout of the first bonding structure 106 is asymmetric to the layout of the second bonding structure 108. Further, the second bonding structure 108 including a single layer of conductive features reduces the number of conductive structures in the stacked IC, thereby reducing the resistivity and RC delay between the first IC chip 102 and the second IC chip 104. In addition, having fewer conductive structures in a stacked IC device is beneficial for reducing the size and / or spacing between conductive structures in the stacked IC device, thereby facilitating device scaling.

[0038] In some embodiments, the shielding structure 114 includes a dielectric material such as silicon dioxide, a low-k dielectric material, some other dielectric materials, or any combination thereof. As described herein, a low-k dielectric material is a dielectric having a dielectric constant less than about 3.9. The first plurality of shielding structures 114 including dielectric materials reduce the effective dielectric constant between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112, thereby reducing the parasitic capacitance in the first IC chip 102. In some embodiments, the dielectric constant of the first plurality of shielding structures 114 is less than the dielectric constant of the first dielectric structure 110. In other embodiments, the shielding structure 114 includes a conductive material, such as copper, aluminum, tungsten, silver, gold, some other conductive materials, or any combination thereof. In some embodiments, the first plurality of shielding structures 114 including conductive materials are conducive to grounding and / or biasing the shielding structure 114, thereby increasing the ability of the shielding structure 114 to block and / or hinder the electromagnetic field between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112. In further embodiments, the height of the shielding structure 114 is equal to the height of the conductive bonding pad 112 .

[0039] The first plurality of conductive pads 112 may be, for example, or include, copper, aluminum, tungsten, silver, gold, some other conductive material, or any combination thereof. In various embodiments, the size or area of ​​each shielding structure 114 is in the range of about 10% to 80% of the size or area of ​​an individual conductive pad in the first plurality of conductive pads 112. For example, Figure 1B As shown in the top view of FIG. 1 , the diameter of each shielding structure 114 is in the range of about 10% to 80% of the diameter of the individual conductive pads in the first plurality of conductive pads 112. This helps to form the shielding structure 114 around each conductive pad without reducing the size of the first plurality of conductive pads 112.

[0040] The first plurality of bonding contacts 118 and the second plurality of bonding contacts 120 may be, for example, or include copper, aluminum, tungsten, titanium nitride, tantalum nitride, some conductive material, or any combination thereof. In some embodiments, the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114 include the same conductive material (e.g., copper, aluminum, tungsten, silver, gold, etc.). In further embodiments, the first plurality of conductive bonding pads 112 include a first material (e.g., copper, aluminum, tungsten, silver, gold, etc.), and the first plurality of shielding structures 114 include a second material different from the first material (e.g., silicon dioxide, a low-k dielectric material, etc.).

[0041] Figure 2A Shows Figure 1A and Figure 1BFIG. 2 is a cross-sectional view 200 a of some other embodiments of a stacked IC device, wherein the second bonding structure 108 includes a second plurality of shielding structures 202 disposed within the second dielectric structure 111 .

[0042] The second plurality of shield structures 202 are disposed between adjacent bonding contacts in the second plurality of bonding contacts 120. In addition, the second plurality of shield structures 202 and the first plurality of shield structures 114 may include the same material and have the same layout. For example, when viewed from a top view (e.g., Figure 1B In the embodiment shown and / or described above, the second plurality of shield structures 202 may have the same layout as the first plurality of shield structures 114. The second plurality of shield structures 202 are bonded to the first plurality of shield structures 114. Since the layout of the second plurality of shield structures 202 is symmetrical to the layout of the first plurality of shield structures 114, gas between the first and second IC chips (102, 104) may be more easily vented during the bonding process, thereby reducing blistering along the first bonding interface 105. Therefore, the bonding adhesion between the first and second IC chips (102, 104) is increased.

[0043] In addition, the second plurality of shielding structures 202 reduces signal interference (e.g., due to parasitic capacitance and / or inductance) between adjacent bonding contacts in the second plurality of bonding contacts 120. Therefore, crosstalk between bonding contacts in the second plurality of bonding contacts 120 is reduced. In some embodiments, the second plurality of shielding structures 202 includes a dielectric material such as silicon dioxide, a low-k dielectric material, some or other dielectric materials, or any combination of the foregoing. In yet another embodiment, the second plurality of shielding structures 202 includes a conductive material such as copper, aluminum, tungsten, silver, gold, some other conductive material, or any combination of the foregoing.

[0044] Figure 2B Shows Figure 1A and Figure 1B FIG. 2 is a cross-sectional view 200 b of some other embodiments of a stacked IC device, wherein the first bonding structure 106 further includes a second plurality of conductive bonding pads 206 disposed within the first dielectric layer 204 .

[0045] In some embodiments, the second plurality of conductive bonding pads 206 are bonded to the second plurality of bonding contacts 120 at the first bonding interface 105. The second bonding structure 108 also includes a second dielectric layer 208 disposed around the second plurality of bonding contacts 120. The first dielectric layer 204 is bonded to the second dielectric layer 208 at the first bonding interface 105. In some embodiments, the first and second dielectric layers (204, 208) may be, for example, or include silicon oxide, silicon oxynitride, silicon nitride, some other dielectric material, etc. In addition, the first dielectric layer 204 is disposed between the first plurality of shielding structures 114 and the first bonding interface 105. By disposing the first dielectric layer 204 between the first plurality of shielding structures 114 and the second dielectric layer 208, the first dielectric layer 204 is directly bonded to the second dielectric layer 208, thereby increasing the bonding adhesion along the first bonding interface 105. In various embodiments, the thickness of the second plurality of conductive bonding pads 206 is less than the thickness of the first plurality of conductive bonding pads 112. In further embodiments, the thickness of the second plurality of conductive pads 206 is greater than the thickness of the first plurality of conductive pads 112 (not shown). The second plurality of conductive pads 206 may be or include, for example, copper, aluminum, tungsten, silver, gold, some other conductive material, or any combination thereof.

[0046] Figure 3A-3E Shows Figure 1A , Figure 2A or Figure 2B Various top views (300a-e) of some other embodiments of stacked IC devices. Figure 3A-3E Shown along Figure 1A , Figure 2A or Figure 2B Top views (300a-e) of some embodiments of stacked IC devices taken along line AA' in FIG.

[0047] like Figure 3AAs shown in the top view 300a of , a subset of shielding structures in the first plurality of shielding structures 114 are arranged around the periphery of each conductive bonding pad in the first plurality of conductive bonding pads 112. The subset of shielding structures in the first plurality of shielding structures 114 are arranged along a circular path concentric with the center of the corresponding bonding pad. For example, the shielding structure 114 around the first conductive bonding pad 112a is arranged along a first circular path 302 concentric with the center of the first conductive bonding pad 112a. In some embodiments, the center of the shielding structure 114 around the first conductive bonding pad 112a is arranged at a different point of the first circular path 302. Therefore, the distance between the shielding structure 114 around the first conductive bonding pad 112a and the periphery of the first conductive bonding pad 112a is equal. For example, the first distance 304 between the first shielding structure 114a and the periphery of the first conductive bonding pad 112a is equal to the second distance 306 between the second shielding structure 114b and the periphery of the first conductive bonding pad 112a.

[0048] like Figure 3B As shown in the top view 300b of , the first plurality of shielding structures 114 have a first shape and the first plurality of conductive bonding pads 112 have a second shape different from the first shape. In some embodiments, the first shape may be rectangular and the second shape may be circular. In further embodiments, the width of the shielding structure 114 is in the range of about 10% to about 80% of the length or diameter of the conductive bonding pad 112. In some embodiments, the length of the shielding structure 114 is in the range of about 10% to about 200% of the length or diameter of the conductive bonding pad 112. For example, the width W of the first shielding structure 114a is in the range of about 10% to about 80% of the diameter D of the first conductive bonding pad 112a, and the length L of the first shielding structure 114a is in the range of about 10% to about 200% of the diameter D of the first conductive bonding pad 112a.

[0049] like Figure 3C As shown in the top view 300c of FIG. 1 , the first plurality of shielding structures 114 have a first shape and the first plurality of conductive bonding pads 112 have a second shape different from the first shape. In some embodiments, the first shape may be a cross and the second shape may be a circle.

[0050] like Figure 3DAs shown in the top view 300d of , the first plurality of shielding structures 114 include an elongated shielding structure 114l extending continuously in a first direction and a shortened shielding structure 114s extending continuously in a second direction orthogonal to the first direction. The shortened shielding structure 114s extends continuously between adjacent elongated shielding structures 114l. In various embodiments, the elongated shielding structure 114l and the shortened shielding structure 114s are a single continuous structure, so that the first plurality of shielding structures 114 have a grid pattern including openings, wherein the first plurality of conductive bonding pads 112 are disposed within the openings. Therefore, in some embodiments, the first plurality of shielding structures 114 continuously surround the periphery of each conductive bonding pad in the first plurality of conductive bonding pads 112 in an uninterrupted path.

[0051] like Figure 3E As shown in the top view 300e of FIG. 1 , the first plurality of shielding structures 114 and the first plurality of conductive bonding pads 112 each have a first shape. In some embodiments, the first shape may be rectangular, square, circular, or the like.

[0052] Figure 4A Shows Figure 1A and Figure 1B 400a of some other embodiments of the stacked IC device, wherein the first bonding structure 106 further includes a first plurality of dummy bonding pads 402 disposed between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112. It should be understood that although Figure 4A A single dummy bonding pad of the first plurality of dummy bonding pads 402 is shown, but other dummy bonding pads (not shown) not shown are disposed within the first dielectric structure 110 (see, for example, Figure 5 ).

[0053] The first plurality of dummy bonding pads 402 are configured to block and / or hinder the electromagnetic field between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112, thereby further reducing the crosstalk between the conductive bonding pads 112. In some embodiments, the first plurality of dummy bonding pads 402 are electrically coupled to ground (e.g., electrically coupled to 0 volts). In other embodiments, the first plurality of dummy bonding pads 402 are electrically coupled to a voltage source (not shown), which is configured to apply a voltage to the first plurality of dummy bonding pads 402. In various embodiments, the first plurality of dummy bonding pads 402 are electrically floating. In some embodiments, the first plurality of dummy bonding pads 402 include dielectric materials such as silicon dioxide, low dielectric constant dielectric materials, some other dielectric materials, or any combination of the above. In yet another embodiment, the first plurality of dummy bonding pads 402 include conductive materials such as copper, aluminum, tungsten, silver, gold, some other conductive materials, or any combination of the above. In some embodiments, the first plurality of dummy bonding pads 402 have the same size as the first plurality of conductive bonding pads 112.

[0054] Figure 4B Shows Figure 2A 400b of some other embodiments of stacked IC devices, wherein the first bonding structure 106 further includes a first plurality of dummy bonding pads 402 and the second bonding structure 108 includes a second plurality of dummy bonding pads 404. It should be understood that although Figure 4B A single dummy bonding pad of the second plurality of dummy bonding pads 404 is shown, but other dummy bonding pads (not shown) not shown are disposed within the second dielectric structure 111 (eg, within the second dielectric structure 111). Figure 5 4. The dummy bonding pads 402 are directly below the first plurality of dummy bonding pads 402.

[0055] In various embodiments, the second plurality of dummy bonding pads 404 are bonded to the first plurality of dummy bonding pads 402 at the first bonding interface 105. In some embodiments, the second plurality of dummy bonding pads 404 include dielectric materials such as silicon dioxide, low-k dielectric materials, some other dielectric materials, or any combination thereof. In yet another embodiment, the second plurality of dummy bonding pads 404 include conductive materials such as copper, aluminum, tungsten, silver, gold, some other conductive materials, or any combination thereof.

[0056] Figure 4C Shows Figure 2B FIG. 4 is a cross-sectional view 400 c of some other embodiments of a stacked IC device, wherein the first plurality of dummy bonding pads 402 are separated from the first bonding interface 105 by the first dielectric layer 204 .

[0057] Figure 5 Shown along Figure 4A-4C The line A-A' intercepts Figure 4A-4C A top view 500 of some embodiments of a stacked IC device.

[0058] like Figure 5 As shown, each dummy bonding pad in the first plurality of dummy bonding pads 402 is disposed between diagonally separated conductive bonding pads in the first plurality of conductive bonding pads 112. Figure 4B 108) includes a second plurality of dummy bonding pads ( Figure 4B In an embodiment of 404), a single dummy bonding pad ( Figure 4B 404) is located under each dummy bonding pad in the first plurality of dummy bonding pads 402. In this embodiment, the second plurality of dummy bonding pads ( Figure 4B The layout of 404) is symmetrical to the layout of the first plurality of dummy bonding pads 402.

[0059] Fig. 6AA cross-sectional view 600a of some embodiments of a stacked IC device is shown that includes a plurality of photodetectors disposed on a first IC chip that is electrically coupled to a second IC chip via a bonding structure that includes a shielding structure.

[0060] The stacked IC device includes a first IC chip 102 bonded to a second IC chip 104 at a first bonding interface 105 and a third IC chip 602 bonded to the second IC chip 104 at a second bonding interface 651. In some embodiments, the first IC chip 102 is configured as an imaging chip including a plurality of photodetectors 124 and a first plurality of transistors 610, the second IC chip 104 is configured as a pixel device chip including a second plurality of transistors 611, and the third IC chip 602 is configured as an ASIC chip including a third plurality of transistors 652. In various embodiments, a plurality of pixels 126 spans across the first and second IC chips (102, 104), wherein each pixel 126 includes a photodetector from the plurality of photodetectors 124 and a transistor from the first plurality of transistors 610 and the second plurality of transistors 611.

[0061] The first IC chip 102 includes a first substrate 101, a first interconnect structure 604 disposed on the front side 101f of the first substrate, and a first bonding structure 106 disposed on the first interconnect structure 604. The first substrate 101 may be, for example, or include silicon, single crystal silicon, CMOS bulk, silicon germanium, silicon-on-insulator (SOI) substrate, or some other semiconductor substrate and have a first doping type (e.g., p-type). A plurality of photodetectors 124 are disposed in the first substrate 101 and may have a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type). In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In addition, a plurality of floating diffusion nodes 612 are disposed in the first substrate 101. The floating diffusion nodes 612 may each be disposed at the intersection of adjacent photodetectors 124. In addition, the floating diffusion nodes 612 include a second doping type (e.g., n-type).

[0062] The isolation structure 618 extends into the back side 101b of the first substrate 101. The isolation structure 618 can be configured as a backside deep trench isolation (DTI) structure and can be or include a dielectric material (e.g., silicon dioxide, silicon nitride, metal oxide, etc.), a metal material (e.g., tungsten, aluminum, titanium nitride, etc.), some other suitable material, or any combination thereof. A plurality of wells 614 are disposed in the first substrate 101 between adjacent floating diffusion nodes 612. The wells 614 include a first doping type (e.g., p-type) and are configured to increase electrical isolation between adjacent pixels in the plurality of pixels 126. A grid structure 620 overlies the back side 101b of the first substrate 101 and includes sidewalls defining a plurality of grid openings above each photodetector 124. A plurality of filters 622 (e.g., filters) overlie the back side 101b of the first substrate 101 and are disposed in the plurality of grid openings. Additionally, a plurality of microlenses 624 overlie the filter 622 and are configured to focus incident light onto the photodetector 124 below.

[0063] The first plurality of transistors 610 are disposed on the front side 101f of the first substrate 101. The first plurality of transistors 610 are configured as transfer transistors, which are configured to transfer accumulated charge from the photodetector 124 to the corresponding floating diffusion node 612. For example, the first plurality of transistors 610 can be biased to selectively form one or more conductive channels within the first substrate 101 between the photodetector 124 and the corresponding floating diffusion node 612. Therefore, the first plurality of transistors 610 can selectively electrically couple the photodetector 124 to the corresponding floating diffusion node 612. The first plurality of transistors 610 include a single gate dielectric structure stack and a single gate electrode (not labeled), wherein the gate dielectric structure is disposed between the first substrate 101 and the gate electrode. In some embodiments, the first plurality of transistors 610 can be configured as vertical transistors.

[0064] The second IC chip 104 is located below the first IC chip 102. In some embodiments, the second IC chip 104 includes a second substrate 103, a second interconnect structure 630 disposed on the front side 103f of the second substrate 103, and a second bonding structure 108 disposed on the second interconnect structure 630. The second substrate 103 may be, for example, or include silicon, single crystal silicon, CMOS bulk, silicon germanium, SOI substrate, or some other semiconductor substrate. A second plurality of transistors 611 are disposed on the front side 103f of the second substrate 103. In some embodiments, the second plurality of transistors 611 are configured as readout transistors. The second plurality of transistors 611 are configured to read out the accumulated charge of the photodetector 124. In some embodiments, the second plurality of transistors 611 include a single reset transistor, a source follower transistor, and a select transistor for each pixel in the plurality of pixels 126. For example, the second plurality of transistors 611 include a single reset transistor 611a and a source follower transistor 611b and a select transistor 611c for a first pixel 126a in the plurality of pixels 126. The second plurality of transistors 611 each include a single gate dielectric structure stacked with a single gate electrode (not labeled) and a pair of source / drain regions (not labeled) disposed on opposite sides of the single gate electrode. One or more source / drain regions may refer to a source or a drain individually or collectively, depending on the context. In some embodiments, the first plurality of transistors 610 and / or the second plurality of transistors 611 are metal-oxide-semiconductor field-effector transistors (MOSFETs), fin field-effect transistors (FinFETs), gate-all-around FETs (GAA FETs), nanosheet field-effect transistors, etc., or any combination thereof.

[0065] In some embodiments, the first and second interconnect structures (604, 630) include a plurality of conductive lines 122 and a plurality of vias 608 disposed in an interconnect dielectric structure 606, respectively. The interconnect dielectric structure 606 may include a plurality of dielectric layers, which may be, for example, or include silicon dioxide, a low-k dielectric material, an ultra-low-k dielectric material, some other dielectric material, or any combination thereof. The vias and conductive lines (608, 122) may be, for example, or include copper, aluminum, titanium nitride, tantalum nitride, tungsten, ruthenium, some other conductive material, or any combination thereof.

[0066] In some embodiments, the first bonding structure 106 includes a first plurality of conductive bonding pads 112, a first plurality of bonding contacts 118, and a first plurality of shielding structures 114 disposed within the first bonding dielectric structure 626. The first plurality of shielding structures 114 are disposed between adjacent conductive bonding pads in the first plurality of conductive bonding pads 112. In further embodiments, the second bonding structure 108 includes a second plurality of bonding contacts 120 disposed within the second bonding dielectric structure 628. Thus, the second bonding structure 108 includes a single layer of conductive bonding features. The first bonding structure 106 is bonded to the second bonding structure 108 at the first bonding interface 105. In addition, the first bonding structure 106 and / or the second bonding structure 108 may be as shown in FIG. Figure 1A-1B , Figure 2A-2B , Figure 3A-3E , Figure 4A-4C or Figure 5 Configured as shown and / or described in .

[0067] The first IC chip 102 is electrically coupled to the second IC chip 104 through the first and second bonding structures (106, 108). In some embodiments, the floating diffusion node 612 of the pixel 126 can be directly electrically coupled to a corresponding transistor in the second plurality of transistors 611 through the interconnect structure (604, 630) and the bonding structure (106, 108). For example, the first floating diffusion node 612a of the first pixel 126a can be directly electrically coupled to the gate of the source follower transistor 611b through the first conductive bonding pad 112a.

[0068] During operation of the stacked IC device, the accumulated charge from the photodetectors of the pixels 126 can be read out column by column. For example, the accumulated charge from the photodetector of the first pixel 126a can be transferred from the first floating diffusion node 612a to the gate of the source follower transistor 611b through the first conductive pad 112a. By disposing the first plurality of shielding structures 114 between the first conductive pad 112a and the adjacent conductive pads, the parasitic capacitance and inductance between the first conductive pad 112a and the adjacent conductive pads are reduced. Therefore, during readout, the influence of the accumulated charge transferred through the first conductive pad 112a on other adjacent conductive pads in the first plurality of conductive pads 112 is reduced. Thus, the crosstalk between adjacent conductive pads in the first plurality of conductive pads 112 is reduced. As a result, the overall performance of the stacked IC device is increased (e.g., the accuracy of the image output from the plurality of pixels 126).

[0069] In various embodiments, a single conductive bonding pad of the first plurality of conductive bonding pads 112 is directly located under a floating diffusion node of a corresponding pixel. For example, the first conductive bonding pad 112a is directly located under the first floating diffusion node 612a of the first pixel 126a. By disposing the first plurality of conductive bonding pads 112 directly under the floating diffusion nodes of the corresponding pixels, the complexity of electrical routing in the first and second IC chips (102, 104) is reduced. This can reduce the number of conductive structures in the first and / or second interconnect structures (604, 630) and / or reduce the complexity of the stacked IC device design.

[0070] The second IC chip 104 also includes a third bonding structure 634 disposed on the back side 103b of the second substrate 103 and a plurality of through substrate vias (TSVs) 632 extending through the second substrate 103. The TSVs 632 are configured to electrically couple the third bonding structure 634 to the second internal wiring structure 630. In some embodiments, the third bonding structure 634 includes a third plurality of conductive bonding pads 640, a third plurality of bonding contacts 638, and a third plurality of shielding structures 650 disposed within the third bonding dielectric structure 636. The third plurality of conductive bonding pads 640 can be electrically coupled to the wires 122 of the second internal wiring structure 630 through the TSVs 632 and the third plurality of bonding contacts 638. In various embodiments, the third plurality of shielding structures 650 are disposed between adjacent conductive bonding pads in the third plurality of conductive bonding pads 640. The third plurality of shielding structures 650 are configured to reduce parasitic capacitance and inductance between adjacent conductive bonding pads in the third plurality of conductive bonding pads 640, thereby reducing crosstalk between adjacent conductive bonding pads.

[0071] In various embodiments, the third IC chip 602 includes a third substrate 641, a third interconnect structure 642 disposed on the front side 641f of the third substrate 641, and a fourth bonding structure 644 disposed on the third interconnect structure 642. A third plurality of transistors 652 are disposed on the front side 641f of the third substrate 641. In some embodiments, the third plurality of transistors 652 are MOSFETs, FinFETs, GAAFETs, nanosheet field effect transistors, etc. or any combination thereof. In some embodiments, the third plurality of transistors 652 are part of an ASIC configured to perform image signal processing (ISP) on corresponding electrical signals from pixels 126. The fourth bonding structure 644 is configured to electrically couple the second IC chip 104 to the third plurality of transistors 652. In some embodiments, the third interconnect structure 642 includes a plurality of wires 122 and a plurality of vias 608 disposed in the interconnect dielectric structure 606. In some embodiments, the fourth bonding structure 644 includes a fourth plurality of bonding contacts 648 disposed in the fourth bonding dielectric structure 646. The third bonding structure 634 intersects with the fourth bonding structure 644 at the second bonding interface 651, and the second bonding interface 651 includes a dielectric to dielectric bond and a conductor to conductor bond. In various embodiments, the fourth bonding structure 644 includes a single layer of conductive bonding features (e.g., a fourth plurality of bonding contacts 648). In various embodiments, the third bonding structure 634 can be configured as the first bonding structure 106, and the fourth bonding structure 644 can be configured as the second bonding structure 108. In another embodiment, the layout of the third and fourth bonding structures (634, 644) can be the same as each other and can be different from the first and second bonding structures (106, 108).

[0072] Figure 6B Shown along Fig. 6A The line A-A' intercepts Fig. 6A A top view 600b of some embodiments of a stacked IC device.

[0073] like Figure 6B As shown, each pixel 126 has a 2x2 pixel layout including 4 photodetectors. In various embodiments, the pixel 126 may include 4 photodetectors arranged in a 2x2 array, 8 photodetectors arranged in a 2x4 array, or some other suitable layout. The floating diffusion node 612 is respectively arranged at the intersection of the 4 photodetectors of each pixel. For example, the first pixel 126a includes a first floating diffusion node 612a arranged at the intersection of the photodetector of the first pixel 126a. In addition, the transistors in the first plurality of transistors 610 overlie and / or are adjacent to each photodetector in the plurality of photodetectors 124.

[0074] Figure 6C Shown along Fig. 6A The line B-B' intercepts Fig. 6A 600c of some embodiments of stacked IC devices. It should be understood that for ease of illustration, Figure 6C The top view 600c of FIG. 6 omits the Fig. 6A Various structures (eg Fig. 6A The first interconnect structure 604 and the first bonding dielectric structure 626).

[0075] like Figure 6C As shown, a single conductive bonding pad of the first plurality of conductive bonding pads 112 is directly located under a corresponding floating diffusion node of the plurality of floating diffusion nodes 612. For example, the first conductive bonding pad 112a is directly located under the first floating diffusion node 612a.

[0076] Fig. 7A Shows Fig. 6A A cross-sectional view 700a of some other embodiments of stacked IC devices is shown.

[0077] In various embodiments, such as Fig. 7A As shown, the first IC chip 102 includes a plurality of photodetectors 124, a first plurality of transistors 610, and a dielectric structure 702. The second IC chip 104 includes a second plurality of transistors 611, a second interconnect structure 630, and a first bonding structure 106. The third IC chip 602 includes a third plurality of transistors 652, a third interconnect structure 642, and a second bonding structure 108. The first bonding structure 106 is disposed on the second interconnect structure 630, and the second bonding structure 108 is disposed on the third interconnect structure 642. The first and second bonding structures (106, 108) intersect at the first bonding interface 105.

[0078] The dielectric structure 702 includes a first dielectric layer 704 disposed on the front side 101f of the first substrate 101 and a second dielectric layer 706 disposed on the first dielectric layer 704. The second dielectric layer 706 is bonded to the back side 103b of the second substrate 103. A plurality of through-substrate vias (TSVs) 708 extend continuously from the conductive lines 122 in the second interconnect structure 630 through the second substrate 103 and the dielectric structure 702 to the devices (e.g., the first plurality of transistors 610) and doped regions (e.g., the floating diffusion nodes 612 and the well 614) of the first IC chip 102. The TSVs 708 include conductive materials (e.g., copper, aluminum, titanium nitride, tungsten, etc.) and are configured to electrically couple the first IC chip 102 directly to the second IC chip 104. For example, the TSVs 708 electrically couple the floating diffusion nodes 612 directly to transistors in the second plurality of transistors 611 (e.g., to one or more reset transistors and / or one or more source-follower transistors).

[0079] Figure 7B Shows Fig. 6A Cross-sectional view 700b of some other embodiments of stacked IC devices.

[0080] In various embodiments, such as Figure 7B As shown, the first IC chip 102 includes a plurality of photodetectors 124, a first plurality of transistors 610, a second plurality of transistors 611, a first interconnect structure 604, and a first bonding structure 106. In addition, the second IC chip 104 includes a third plurality of transistors 652, a second interconnect structure 630, and a second bonding structure 108. The first plurality of conductive bonding pads 112 of the first bonding structure 106 directly electrically couples transistors in the second plurality of transistors 611 to transistors in the third plurality of transistors 652.

[0081] Fig. 8A Circuit diagram 800a of some embodiments of a stacked IC device including a first IC chip bonded to a second IC chip is shown. In some embodiments, Fig. 8A The circuit diagram 800a may correspond to Figure 6A-6C Some embodiments of stacked IC devices.

[0082] The pixel 126 has a 2x2 pixel layout and spans the first and second IC chips (102, 104). The pixel 126 includes a first plurality of transistors 610, a photodetector 124, and a floating diffusion node 612 disposed on the first IC chip 102, and a second plurality of transistors 611 disposed on the second IC chip 104. It should be understood that although the circuit diagram 800a shows a single transistor for a group of four photodetectors 124, the first plurality of transistors 307 has a single transistor coupled between each photodetector 124 and the floating diffusion node 612. The third IC chip 602 includes an ASIC 802. In various embodiments, the first and second IC chips (102, 104) are configured to conduct readout of the photodetector 124 so that the charge accumulated by the photodetector 124 from the incident radiation can be read out as a corresponding electrical signal. The electrical signal can be provided to the ASIC 802 for downstream signal processing. For example, the ASIC 802 can be configured to perform analog-to-digital conversion (ADC), image processing, buffering, etc., or any combination of the above.

[0083] The first plurality of transistors 610 are selected by the transfer signal TX and are configured to selectively transfer the charge accumulated at the photodetector 124 to the floating diffusion node 612. The second plurality of transistors 611 include a reset transistor 611a, a source follower transistor 611b and a selection transistor 611c. The reset transistor 611a is coupled between the floating diffusion node 612 and the reset voltage Vrst. The reset transistor 611a is selected by the reset signal RST and is configured to selectively electrically couple the floating diffusion node 612 to the reset voltage Vrst to reset the floating diffusion node 612. In addition, the reset transistor 611a can be configured to selectively electrically couple the photodetector 124 to the reset voltage Vrst by coordinating with the first plurality of transistors 610.

[0084] The source follower transistor 611b is gated by the charge at the floating diffusion node 612. For example, the gate of the source follower transistor 611b is directly electrically coupled to the floating diffusion node 612 through the first bonding interface 105. The source follower transistor 611b is coupled between the power supply voltage Vdd and the source / drain region of the select transistor 611c. The source follower transistor 611b is configured to buffer and / or amplify the voltage at the floating diffusion node 612 to read the voltage. The select transistor 611c is configured to selectively transmit the buffered and / or amplified voltage from the source follower transistor 611b to the output of the pixel 126. The output of the pixel 126 is electrically coupled to the ASIC 802 through the second bonding interface 651.

[0085] The first bonding structure ( Fig. 6AA single conductive bonding pad (106) Fig. 6A 112a) is configured to electrically couple the floating diffusion node 612 directly to the gate of the source follower transistor 611b and / or the source / drain region of the reset transistor 611a at the first bonding interface 105. Fig. 6A 114) are provided on separate conductive bonding pads ( Fig. 6A On the opposite side of the pixel 112a), signal interference read out of the second floating diffusion node (not shown) of another pixel (not shown) adjacent to the pixel 126 at the first bonding interface 105 is reduced. Therefore, the image quality of the stacked IC device is improved.

[0086] Figure 8B Shows Fig. 8A 800 b of some other embodiments of stacked IC devices, wherein the second IC chip 104 further includes an in-pixel circuit 804 electrically coupled between the second plurality of transistors 611 and the ASIC 802. In some embodiments, the in-pixel circuit 804 may include one or more additional transistors (e.g., logic transistors) and is configured to perform additional processing on the electrical signal from the select transistor 611 c before transmitting the electrical signal to the ASIC 802.

[0087] Figure 8C Show Figure 8B The circuit diagram 800 c of some other embodiments of the stacked IC device, wherein the second plurality of transistors 611 are disposed on the first IC chip 102 .

[0088] Fig.8D Shows Fig. 8A 800d of some other embodiments of the stacked IC device, wherein the third IC chip ( Fig. 8A 602), the second plurality of transistors 611 are disposed on the first IC chip 102 and the ASIC 802 is disposed on the second IC chip 104. In some embodiments, the circuit diagram 800d may correspond to Figure 7B Some embodiments of stacked IC devices.

[0089] Figure 9-Figure 21 Various views (900, 1000, 1100, 1200, 1300, 1400a, 1400b, 1500, 1600, 1700, 1800, 1900, 2000, 2100) of some embodiments of methods of forming a stacked IC device including a bonded structure having a shielding structure are shown. Figure 9-Figure 21The various views (900, 1000, 1100, 1200, 1300, 1400a, 1400b, 1500, 1600, 1700, 1800, 1900, 2000, 2100) shown in FIG. 1 are described with reference to this method, but it should be understood that Figure 9-Figure 21 The structure shown in is not limited to this method, but can be independent of this method. Figure 9-Figure 21 It is described as a series of actions, but it should be understood that it is not limited to these actions. In other embodiments, the order of actions can be changed, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0090] like Fig. 9 As shown in the cross-sectional view 900 of , a plurality of photodetectors 124 are formed in the first substrate 101. For example, the first substrate 101 may be or include silicon, single crystal silicon, epitaxial silicon germanium, silicon germanium, another semiconductor material, etc., and may have a first doping type (e.g., p-type). In some embodiments, the process for forming the photodetectors 124 includes performing a selective ion implantation process. The selective ion implantation process may include implanting one or more dopants in the first substrate 101 according to a mask layer (not shown). In various embodiments, the photodetectors 124 include a second doping type (e.g., n-type) opposite to the first doping type (e.g., p-type).

[0091] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a plurality of wells 614 are formed in the first substrate 101. The wells 614 include a first doping type (eg, p-type) having a higher doping concentration than adjacent regions of the first substrate 101. In some embodiments, the wells 614 are formed by a selective ion implantation process.

[0092] like Fig.11As shown in the cross-sectional view 1100 of FIG. 1 , the first plurality of transistors 610 and the plurality of floating diffusion nodes 612 are formed on and / or in the front side 101f of the first substrate 101. In some embodiments, a process for forming the first plurality of transistors 610 includes: selectively etching the front side 101f of the first substrate 101 to form trenches extending into the front side 101f of the first substrate 101; depositing (e.g., by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.) a gate dielectric layer on the first substrate 101 and lining the trenches; depositing (e.g., by PVD, CVD, sputtering, plating, etc.) a gate electrode on the gate dielectric layer and in the trenches; performing a patterning process on the gate electrode and the gate dielectric layer; and forming a sidewall spacer structure on the sidewalls of the gate electrode and the gate dielectric layer. The process for forming the floating diffusion node 612 includes selectively implanting one or more dopants in the first substrate 101. The floating diffusion node 612 includes a second doping type (eg, n-type). In some embodiments, the floating diffusion node 612 can be formed after forming the first plurality of transistors 610 so that the floating diffusion node 612 can be aligned with sidewalls of the first plurality of transistors 610 .

[0093] like Fig.12 As shown in the cross-sectional view 1200 of the first substrate 101, a first interconnect structure 604 is formed on the front side 101f of the first substrate 101. The first interconnect structure 604 includes a plurality of conductive lines 122 and a plurality of vias 608 disposed in an interconnect dielectric structure 606. The interconnect dielectric structure 606 may be formed by one or more deposition processes, such as one or more PVD processes, one or more CVD processes, one or more ALD processes, one or more other suitable growth and / or deposition processes, or any combination thereof. In some embodiments, the plurality of vias 608 and the plurality of conductive lines 122 are formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, some other suitable one or more manufacturing processes, or any combination thereof. For example, the plurality of vias 608 and the plurality of conductive lines 122 may be formed by a single damascene process, a dual damascene process, or the like.

[0094] like Fig.13As shown in the cross-sectional view 1300 of , a first bonding dielectric structure 626 and a first plurality of bonding contacts 118 are formed on the first interconnect structure 604. The first bonding dielectric structure 626 is formed on the first interconnect structure 604 by a PVD process, a CVD process, an ALD process, etc. The first bonding dielectric structure 626 may be, for example, or include silicon oxynitride, silicon dioxide, silicon carbide, some other dielectric material, or any combination thereof. In some embodiments, a process for forming the first plurality of bonding contacts 118 includes: forming a mask layer (not shown) on the first bonding dielectric structure 626; etching the first bonding dielectric structure 626 with the mask layer positioned to form a plurality of openings in the first bonding dielectric structure 626; depositing (e.g., by CVD, PVD, ALD, sputtering, electroplating, etc.) a conductive material (e.g., copper, aluminum, tungsten, another conductive material, or any combination thereof) in the opening; and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) on the conductive material.

[0095] like Fig.14A The cross-sectional view 1400a and along Fig.14A The cross-sectional view 1400a is taken along the line AA' Fig. 14B 1400b, a first plurality of conductive bonding pads 112 and a first plurality of shielding structures 114 are formed on the first plurality of bonding contacts 118, thereby defining the first bonding structure 106 and the first IC chip 102. In some embodiments, a process for forming the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114 includes: depositing (e.g., by CVD, PVD, ALD, etc.) an upper dielectric layer on the first plurality of bonding contacts 118; forming a mask layer (not shown) on the upper dielectric layer; etching the upper dielectric layer according to the mask layer to form a plurality of bonding feature openings in the upper dielectric layer; performing a deposition process to deposit the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114 in the bonding feature openings; and performing a planarization process (e.g., a CMP process) on the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114. The upper dielectric layer is part of the first bonding dielectric structure 626 and may be, for example, or include silicon oxynitride, silicon dioxide, silicon carbide, some other dielectric material, or any combination thereof.

[0096] In further embodiments, the deposition process includes: performing a first deposition process (e.g., CVD, PVD, ALD, electroplating, electroless plating, etc.) to deposit a conductive bonding pad material (e.g., copper, aluminum, tungsten, etc.) in a first opening of the plurality of bonding feature openings, which corresponds to the first plurality of conductive bonding pads 112; and performing a second deposition process (e.g., CVD, PVD, ALD, electroplating, electroless plating, etc.) to deposit a shielding structure material (e.g., a metal material (e.g., copper, aluminum, tungsten) or a dielectric material (e.g., silicon dioxide, a low-k dielectric material, etc.)) in a second opening of the plurality of bonding feature openings, which corresponds to the first plurality of shielding structures 114. In some embodiments, the first deposition process is different from the second deposition process.

[0097] In various embodiments, the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114 include the same conductive material (e.g., copper, aluminum, gold, silver, tungsten, etc.). In other embodiments, the first plurality of shielding structures 114 include a dielectric material (e.g., silicon dioxide, a low-k dielectric material, etc.) that is different from the conductive material (e.g., copper, aluminum, gold, silver, tungsten, etc.) of the first plurality of conductive bonding pads 112. In some embodiments, the first plurality of conductive bonding pads 112 and the first plurality of shielding structures 114 are formed simultaneously. Furthermore, in some embodiments, the first bonding structure 106 may be formed such that the first bonding structure 106 has a dielectric material such as Figure 1B , Figure 3A-3E or Figure 5 A top view or layout of any one of the ones shown and / or described.

[0098] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a second substrate 103 is provided and a second plurality of transistors 611 and a second interconnect structure 630 are formed on the front side 103f of the second substrate 103. In some examples, the second plurality of transistors 611 and the second interconnect structure 630 are connected by the above-mentioned Fig.11 and Fig.12 The structures of the cross-sectional view 1100 and the cross-sectional view 1200 are formed by one or more processes that are substantially similar.

[0099] like Fig.16As shown in the cross-sectional view 1600 of FIG. 1 , a second bonding structure 108 is formed on the second interconnect structure 630, thereby forming a second IC chip 104. In some embodiments, the second bonding structure 108 includes a second plurality of bonding contacts 120 disposed in a second bonding dielectric structure 628. The second bonding dielectric structure 628 is formed on the second interconnect structure 630 by a PVD process, a CVD process, an ALD process, etc. The second bonding dielectric structure 628 may be, for example, or include silicon oxynitride, silicon dioxide, silicon carbide, some other dielectric material, or any combination thereof. In some embodiments, a process for forming the second plurality of bonding contacts 120 includes: forming a mask layer (not shown) on the second bonding dielectric structure 628; etching the second bonding dielectric structure 628 with the mask layer in place to form a plurality of openings in the second bonding dielectric structure 628; depositing (e.g., by CVD, PVD, ALD, sputtering, plating, etc.) a conductive material (e.g., copper, aluminum, tungsten, another conductive material, or any combination thereof) within the openings; and performing a planarization process (e.g., a CMP process) on the conductive material. In various embodiments, the second bonding structure 108 includes a single layer of conductive bonding features (e.g., the second plurality of bonding contacts 120).

[0100] like Fig.17 As shown in the cross-sectional view 1700 of , the first IC chip 102 is bonded to the second IC chip 104. Bonding the first IC chip 102 to the second IC chip 104 includes: flipping the first IC chip 102 and aligning the first IC chip 102 with the second IC chip 104; applying pressure to the first and / or second IC chips 102, 104; and performing an annealing process on the first and second IC chips (102, 104) to form a first bonding interface 105. The first bonding interface 105 includes a dielectric-to-dielectric bond and a conductor-to-conductor bond.

[0101] like Fig.18 As shown in the cross-sectional view 1800 of FIG. 1 , a plurality of through substrate vias (TSVs) 632 and a third bonding structure 634 are formed on and / or within the second substrate 103. The TSVs 632 extend continuously through the second substrate 103 and electrically couple the third bonding structure 634 to the second interconnect structure 630. In some embodiments, the third bonding structure 634 includes a third plurality of conductive bonding pads 640, a third plurality of bonding contacts 638, and a third plurality of shielding structures 650 disposed within a third bonding dielectric structure 636. In various embodiments, the third bonding structure 634 is formed by one or more processes (e.g., Fig.13 , Fig.14A and Fig. 14B ) are formed by a process substantially similar to that shown and / or described in .

[0102] like Fig.19 As shown in the cross-sectional view 1900 of FIG. 1 , the first and second IC chips (102, 104) are bonded to the third IC chip 602. In various embodiments, the third IC chip 602 is Fig. 6A In some embodiments, bonding the third IC chip 602 to the first and second IC chips (102, 104) includes: aligning the third IC chip 602 with the first and second IC chips (102, 104); applying pressure to the first and second IC chips 102, 104 and / or the third IC chip 602; and performing an annealing process to form a second bonding interface 651 between the second and third IC chips (104, 602).

[0103] like Fig. 20 As shown in the cross-sectional view 2000 of FIG. 1 , an isolation structure 618 extending into the back side 101b of the first substrate 101 is formed. In some embodiments, a process for forming the isolation structure 618 includes: selectively etching the back side 101b of the first substrate 101 to form a trench disposed between adjacent photodetectors 124; depositing (e.g., by CVD, PVD, ALD, etc.) an isolation structure material in the trench and on the first substrate 101; and performing a planarization process (e.g., a CMP process, an etching process, etc.) on the isolation structure material.

[0104] like Fig.21 As shown in the cross-sectional view 2100 of FIG. 1 , a grid structure 620, a plurality of color filters 622, and a plurality of microlenses 624 are formed on the back side 101b of the first substrate 101. The grid structure 620 is formed by depositing a grid material over the first substrate 101 and patterning the grid material to form the grid structure 620. The color filter 622 can be formed by depositing and patterning a single color filter layer corresponding to the color filter 622. The microlenses 624 are formed by depositing a microlens material on the color filter 622 and patterning the microlens material to form a plurality of microlenses 624.

[0105] Fig. 22 Some embodiments of a method 2200 for forming a stacked IC device including a bonding structure with a shielding structure are shown. Although method 2200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from the order shown and / or may be performed simultaneously. Further, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed in a time-sharing or simultaneous manner with other actions or sub-actions. In some embodiments, the actions and events shown may be omitted, and other actions and events not shown may also be included.

[0106] At act 2202, a plurality of photodetectors are formed within a first substrate of a first integrated circuit (IC) chip. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 2202 is shown.

[0107] At act 2204, a first plurality of transistors and a plurality of floating diffusion nodes are formed on and / or within a front side of a first substrate. Fig.11 Cross-sectional view 1100 is shown corresponding to some embodiments of act 2204 .

[0108] At act 2206, a first interconnect structure is formed on the front side of the first substrate. Fig.12 Cross-sectional view 1200 is shown corresponding to some embodiments of act 2206 .

[0109] At activity 2208, a first bonding structure is formed on the first interconnect structure. The first bonding structure includes a first plurality of bonding contacts, a first plurality of conductive bonding pads, and a first plurality of shielding structures disposed between adjacent conductive bonding pads in the first plurality of conductive bonding pads. Fig.13 , Fig.14A and Fig. 14B Various views 1300 , 1400 a , and 1400 b are shown corresponding to some embodiments of action 2208 .

[0110] At act 2210, a second plurality of transistors and a second interconnect structure are formed on a front side of a second substrate of a second IC chip. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 2210 is shown.

[0111] At act 2212 , a second bonding structure is formed on the second interconnect structure, wherein the second bonding structure includes a second plurality of bonding contacts. Fig.16 Cross-sectional view 1600 is shown corresponding to some embodiments of act 2212 .

[0112] At act 2214, the first IC chip is bonded to the second IC chip such that the first bonding structure intersects the second bonding structure at a first bonding interface. The first plurality of conductive bonding pads contacts the second plurality of bonding contacts at the first bonding interface. Fig.17 Cross-sectional view 1700 is shown corresponding to some embodiments of act 2214 .

[0113] At act 2216 , the second IC chip is bonded to the third IC chip such that the second and third IC chips intersect at a second bonding interface. Fig.19 Cross-sectional view 1900 is shown corresponding to some embodiments of act 2216 .

[0114] At act 2218, a grid structure, a plurality of filters, and a plurality of microlenses are formed on the back side of the first substrate. Fig. 20 Cross-sectional view 2000 corresponding to some embodiments of act 2218 is shown.

[0115] Therefore, in some embodiments, the present invention is directed to a stacked IC device including a first IC chip having a first bonding structure bonded to a second bonding structure of a second IC chip, wherein the first bonding structure includes a shielding structure disposed between adjacent conductive bonding pads.

[0116] In some embodiments, the utility model provides an integrated circuit (IC), comprising: a first IC chip including a plurality of photodetectors arranged in a first substrate and a first bonding structure, wherein the first bonding structure includes a first plurality of bonding contacts arranged on a first plurality of conductive bonding pads; a second IC chip including a second bonding structure and a second substrate, wherein a first bonding interface is arranged between the first bonding structure and the second bonding structure, wherein the second bonding structure includes a second plurality of bonding contacts; and wherein the first bonding structure also includes a first plurality of shielding structures arranged between adjacent conductive bonding pads among the first plurality of conductive bonding pads.

[0117] In some embodiments, the bottom surface of the first plurality of shielding structures is aligned with the bottom surface of the first plurality of conductive bonding pads, and the height of the first plurality of shielding structures is equal to the height of the first plurality of conductive bonding pads. In some embodiments, the width or diameter of each shielding structure in the first plurality of shielding structures is less than the width or diameter of the conductive bonding pad in the first plurality of conductive bonding pads. In some embodiments, the first plurality of conductive bonding pads include a first conductive bonding pad, wherein a first subset of shielding structures in the first plurality of shielding structures is arranged around the periphery of the first conductive bonding pad. In some embodiments, the center of the shielding structure in the first subset of the shielding structures is arranged along a circular path concentric with the center of the first conductive bonding pad, wherein the distance between each shielding structure in the first subset of the shielding structures and the periphery of the first conductive bonding pad is equal to each other. In some embodiments, in a cross-sectional view, the first plurality of shielding structures and the first plurality of conductive bonding pads have a first shape, and in a top view, the first plurality of conductive bonding pads have a second shape different from the first shape. In some embodiments, in the top view, the first plurality of shielding structures have a third shape different from the second shape. In some embodiments, the second bonding structure further comprises a second plurality of shielding structures disposed between adjacent bonding contacts in the second plurality of bonding contacts, wherein the first plurality of shielding structures are in contact with the second plurality of shielding structures at the first bonding interface, wherein a layout of the first plurality of shielding structures is symmetrical to a layout of the second plurality of shielding structures. In some embodiments, the integrated circuit further comprises a pixel comprising a first subset of the plurality of photodetectors and a floating diffusion node disposed at an intersection of the first subset of the plurality of photodetectors, wherein the first plurality of conductive bonding pads comprises a first conductive bonding pad directly below the floating diffusion node and directly electrically coupled to the floating diffusion node.

[0118] In some embodiments, the utility model provides an integrated circuit (IC), comprising: a first IC chip including a first substrate, a first internal wiring structure on the first substrate, a first bonding structure on the first internal wiring structure, and a first pixel, wherein the first pixel includes a plurality of photodetectors arranged in the first substrate and a floating diffusion node arranged at the intersection of the plurality of photodetectors; and a second IC chip including a second substrate, a second internal wiring structure on the second substrate, and a second bonding structure arranged on the second internal wiring structure, wherein the first bonding structure contacts the second bonding structure at a first bonding interface; and wherein the first bonding structure includes a first plurality of bonding contacts, a first plurality of conductive bonding pads, and a first plurality of shielding structures, wherein the first plurality of conductive bonding pads include a first conductive bonding pad directly below the floating diffusion node and a second conductive bonding pad laterally adjacent to the first conductive bonding pad, wherein the first plurality of shielding structures include a first shielding structure laterally arranged between the first conductive bonding pad and the second conductive bonding pad.

[0119] In some embodiments, the first plurality of shielding structures include at least four shielding structures arranged at the periphery of the first conductive bonding pad. In some embodiments, the first bonding structure also includes a first plurality of dummy bonding pads arranged between the conductive bonding pads diagonally opposite to each other in the first plurality of conductive bonding pads, wherein the first plurality of shielding structures also include a third conductive bonding pad diagonally opposite to the first conductive bonding pad, and wherein the first plurality of dummy bonding pads include a first dummy bonding pad arranged between the first conductive bonding pad and the third conductive bonding pad. In some embodiments, the area of ​​the first plurality of dummy bonding pads is equal to the area of ​​the first plurality of conductive bonding pads, and wherein the area of ​​the first plurality of shielding structures is less than the area of ​​the first plurality of dummy bonding pads. In some embodiments, the first bonding structure includes a second plurality of conductive bonding pads arranged in a first dielectric layer, wherein the second plurality of conductive bonding pads are arranged between the first plurality of conductive bonding pads and the second bonding structure, wherein the second bonding structure includes a second plurality of bonding contacts arranged in a second dielectric layer, wherein the second plurality of bonding contacts directly contact the second plurality of conductive bonding pads at the first bonding interface, wherein the first plurality of shielding structures are vertically offset from the second bonding structure through the first dielectric layer. In some embodiments, a first readout transistor is disposed on the front side of the second substrate, wherein the first conductive bonding pad electrically couples the floating diffusion node directly to a gate of the first readout transistor.

[0120] In various embodiments, the utility model provides a method for forming an integrated circuit (IC), the method comprising: forming a plurality of photodetectors within a first substrate; forming a first internal wiring structure on the front side of the first substrate; forming a first bonding structure on the first internal wiring structure, wherein the first bonding structure comprises a first plurality of bonding contacts, a first plurality of conductive bonding pads, and a first plurality of shielding structures disposed within the first bonding dielectric structure, wherein the first plurality of shielding structures are disposed between adjacent conductive bonding pads among the first plurality of conductive bonding pads; forming a second internal wiring structure on a second substrate; forming a second bonding structure on the second internal wiring structure; and bonding the first bonding structure to the second bonding structure at a first bonding interface.

[0121] In some embodiments, the first plurality of conductive bonding pads includes a first conductive bonding pad, wherein a first subset of the first plurality of shielding structures is disposed around the periphery of the first conductive bonding pad, wherein a width or diameter of each shielding structure in the first subset of the first plurality of shielding structures is less than a width or diameter of the first conductive bonding pad. In some embodiments, the first plurality of conductive bonding pads includes a first material and the first plurality of shielding structures includes a second material different from the first material. In some embodiments, the method further includes: performing an ion implantation process to form a floating diffusion node at the intersection of the plurality of photodetectors; forming a readout transistor on the second substrate, wherein the readout transistor includes a gate electrode above a gate dielectric layer; and wherein the first plurality of conductive bonding pads includes a first conductive bonding pad directly below the floating diffusion node, and wherein the first conductive bonding pad electrically couples the floating diffusion node directly to the gate electrode of the readout transistor. In some embodiments, the second bonding structure includes a single layer of conductive bonding features disposed within a second bonding dielectric structure, wherein the first plurality of shielding structures are bonded to the second bonding dielectric structure at the first bonding interface.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the utility model, rather than to limit them. Although the embodiments of the utility model are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the embodiments of the utility model.

Claims

1. An integrated circuit, characterized in that: include: a first integrated circuit chip comprising a plurality of photodetectors disposed in a first substrate and a first bonding structure, wherein the first bonding structure comprises a first plurality of bonding contacts disposed on a first plurality of conductive bonding pads; as well as a second integrated circuit chip comprising a second bonding structure and a second substrate, wherein a first bonding interface is disposed between the first bonding structure and the second bonding structure, wherein the second bonding structure comprises a second plurality of bonding contacts, The first bonding structure further includes a first plurality of shielding structures disposed between adjacent conductive bonding pads in the first plurality of conductive bonding pads.

2. The integrated circuit according to claim 1, characterized in that The bottom surfaces of the first plurality of shielding structures are aligned with the bottom surfaces of the first plurality of conductive bonding pads, and the heights of the first plurality of shielding structures are equal to the heights of the first plurality of conductive bonding pads.

3. The integrated circuit according to claim 1, characterized in that The first plurality of conductive bonding pads includes a first conductive bonding pad, wherein a first subset of shield structures in the first plurality of shield structures is disposed around a periphery of the first conductive bonding pad.

4. The integrated circuit according to claim 1, characterized in that Wherein in the cross-sectional view, the first plurality of shielding structures and the first plurality of conductive bonding pads have a first shape, and in the top view, the first plurality of conductive bonding pads have a second shape different from the first shape.

5. The integrated circuit according to claim 1, characterized in that The second bonding structure also includes a second plurality of shielding structures arranged between adjacent bonding contacts in the second plurality of bonding contacts, wherein the first plurality of shielding structures are in contact with the second plurality of shielding structures at the first bonding interface, and wherein the layout of the first plurality of shielding structures is symmetrical to the layout of the second plurality of shielding structures.

6. The integrated circuit according to claim 1, characterized in that Also includes: a pixel comprising a first subset of the plurality of photodetectors and a floating diffusion node disposed at an intersection of the first subset of the plurality of photodetectors, The first plurality of conductive bonding pads includes a first conductive bonding pad directly below the floating diffusion node and directly electrically coupled to the floating diffusion node.

7. An integrated circuit, characterized in that: include: A first integrated circuit chip, comprising a first substrate, a first interconnect structure on the first substrate, a first bonding structure on the first interconnect structure, and a first pixel, wherein the first pixel comprises a plurality of photodetectors disposed in the first substrate and a floating diffusion node disposed at intersections of the plurality of photodetectors; as well as The second integrated circuit chip comprises a second substrate, a second internal connection structure on the second substrate, and a second bonding structure disposed on the second internal connection structure, wherein the first bonding structure contacts the second bonding structure at a first bonding interface. The first bonding structure includes a first plurality of bonding contacts, a first plurality of conductive bonding pads and a first plurality of shielding structures, wherein the first plurality of conductive bonding pads include a first conductive bonding pad directly below the floating diffusion node and a second conductive bonding pad laterally adjacent to the first conductive bonding pad, wherein the first plurality of shielding structures include a first shielding structure laterally disposed between the first conductive bonding pad and the second conductive bonding pad.

8. The integrated circuit according to claim 7, characterized in that Wherein the first bonding structure further includes a first plurality of dummy bonding pads arranged between conductive bonding pads diagonally opposite to each other among the first plurality of conductive bonding pads, wherein the first plurality of shielding structures further include a third conductive bonding pad diagonally opposite to the first conductive bonding pad, and wherein the first plurality of dummy bonding pads includes a first dummy bonding pad arranged between the first conductive bonding pad and the third conductive bonding pad.

9. The integrated circuit according to claim 7, characterized in that: wherein the first bonding structure comprises a second plurality of conductive bonding pads disposed within a first dielectric layer, wherein the second plurality of conductive bonding pads are disposed between the first plurality of conductive bonding pads and the second bonding structure, wherein the second bonding structure comprises a second plurality of bonding contacts disposed within a second dielectric layer, wherein the second plurality of bonding contacts directly contact the second plurality of conductive bonding pads at the first bonding interface, and wherein the first plurality of shielding structures are vertically offset from the second bonding structure through the first dielectric layer.

10. The integrated circuit according to claim 7, characterized in that: A first readout transistor is disposed on the front side of the second substrate, wherein the first conductive bonding pad electrically couples the floating diffusion node directly to a gate of the first readout transistor.

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