Chip for ultrasonic transducer, ultrasonic transducer and equipment

Abstract

The embodiment of the utility model provides a chip for an ultrasonic transducer, the ultrasonic transducer and equipment, the chip is arranged below an acoustic layer, and the chip comprises a substrate; a circuit module, wherein the circuit module is arranged in the substrate; the conductive shielding layer is arranged between the circuit module and the acoustic layer, the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is grounded. According to the embodiment of the invention, the situation that the small-spacing metal blocks and the suspended metal blocks in the circuit module are easy to break down due to relatively high voltage generated in the polarization process of the acoustic layer is reduced, and the yield of chips is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of sensor technology, and in particular to a chip, an ultrasonic transducer, and a device for an ultrasonic transducer. Background Art

[0002] An ultrasonic transducer consists of an acoustic layer and a chip. The acoustic layer includes a piezoelectric layer, an electrode on the piezoelectric layer, and a protective layer. In transmit mode, the chip drives the piezoelectric layer to vibrate, emitting ultrasonic waves toward the target. In receive mode, the chip uses the acoustic wave signals reflected from the acoustic path to identify the surface structure of the detected object.

[0003] In the actual application of ultrasonic transducers, since the circuit module of the chip is set in the substrate below the acoustic layer, the polarization of the acoustic layer of the ultrasonic transducer requires a higher voltage. Therefore, the higher voltage will make the small-pitch metal blocks and suspended metal blocks in the circuit module easily broken down, affecting the yield of the chip. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a chip, an ultrasonic transducer, and a device for an ultrasonic transducer, which at least partially solve the above technical problems.

[0005] According to the first aspect of the present application, an embodiment provides a chip for an ultrasonic transducer, wherein the chip is arranged below an acoustic layer, and the chip includes: a substrate; a circuit module, wherein the circuit module is arranged in the substrate; a conductive shielding layer, wherein the conductive shielding layer is arranged between the circuit module and the acoustic layer, and the projection of the conductive shielding layer on the substrate at least covers the projection of the circuit module on the substrate, and the conductive shielding layer is grounded.

[0006] According to the second aspect of the present application, an embodiment provides an ultrasonic transducer, including: the above chip and an acoustic layer.

[0007] According to a third aspect of the present application, an electronic device is provided, comprising: a screen and the above-mentioned ultrasonic transducer, wherein the ultrasonic transducer is attached to the screen via a substrate of the ultrasonic transducer.

[0008] Embodiments of the present application provide a chip, ultrasonic transducer, device, and preparation method for an ultrasonic transducer. A conductive shielding layer is disposed between a circuit module and an acoustic layer within a substrate, with the projection of the conductive shielding layer on the substrate at least covering the projection of the circuit module on the substrate. The conductive shielding layer directs induced charge from above the acoustic layer of the ultrasonic transducer to ground. Embodiments of the present application reduce the risk of breakdown of small-pitch metal blocks and suspended metal blocks within the circuit module due to the high voltage generated during polarization of the acoustic layer, thereby improving the chip's yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0010] Figure 1 is a top view of an embodiment of an ultrasonic transducer according to the present application;

[0011] Figure 2 for Figure 1 Cross-section at AA;

[0012] Figure 3 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0013] Figure 4 for Figure 3 Cross-section at AA;

[0014] Figure 5 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0015] Figure 6 for Figure 5 Cross-section at AA;

[0016] Figure 7 for Figure 5 Another cross-sectional view at AA in the middle;

[0017] Figure 8 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0018] Figure 9 for Figure 8 Cross-section at AA;

[0019] Figure 10 is a top view of yet another embodiment of an ultrasonic transducer according to the present application;

[0020] Figure 11 for Figure 10 Cross-section at AA;

[0021] Figure 12 for Figure 10 Cross-section at AA;

[0022] Figure 13 for Figure 10 Cross-section at AA;

[0023] Figure 14 for Figure 10Cross-section at AA;

[0024] Figure 15 is a schematic diagram of an embodiment of an electronic device.

[0025] Description of reference numerals:

[0026] Chip 1000;

[0027] Pixel circuit area 100; pixel electrode 110;

[0028] Chip ground module 200; circuit module 300; metal pad area 400;

[0029] substrate 500;

[0030] Metal layer 510; top metal layer 5101; multiple metal layers 5102;

[0031] Passivation layer 520; first window 5201; second window 5202;

[0032] Conductive shielding layer 600; conductive layer 610; dielectric layer 620;

[0033] Acoustic layer 2000;

[0034] Piezoelectric layer 2100; electrode 2200 on the piezoelectric layer; protective layer 2300. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0036] The following instructions Figures 1-15 The structure of the chip 1000 according to the embodiment of the present application is described in detail. In order to facilitate the observation of the structure of the chip 1000, Figure 1 、 Figure 3 、 Figure 5 、 Figure 7 、 Figure 9 、 Figure 11 、 Figure 13 The acoustic layer 2000 is omitted.

[0037] See also Figure 1 and Figure 2 , Figure 2 for Figure 1The ultrasonic transducer includes an acoustic layer 2000 and a chip 1000. The acoustic layer 2000 includes a piezoelectric layer 2100, a piezoelectric layer top electrode 2200, and a protective layer 2300. The chip 1000 is disposed below the piezoelectric layer 2100 of the acoustic layer 2000. The chip 1000 includes a substrate 500, a pixel circuit region 100, a chip ground module 200, a circuit module 300, a metal pad region 400, and an excitation electrode (not shown). Figure 2 The metal layer 510 above the middle metal pad region 400 is a metal pad, and the passivation layer above the metal pad region 510 is provided with a window to expose a portion of the metal pad.

[0038] Specifically, substrate 500 is a silicon-based substrate, and includes a top metal layer 5101 above substrate 500, and a passivation layer 520 above top metal layer 5101. Substrate 500 includes a number of transistor units (such as N-type or P-type metal oxide semiconductor field effect transistors, and complementary metal oxide semiconductor field effect transistors composed of both), intra-layer metal traces for interconnection, inter-layer vias, and multi-layer metal layers 5102. In the figure, only "..." is used to represent the above-mentioned transistor units, metal traces, inter-layer vias, and multi-layer metal layers 5102.

[0039] See also Figure 3 and Figure 4 , Figure 4 for Figure 3 Schematic diagram of the lateral structure cut along the AA section. The passivation layer 520 of the pixel circuit area 100 is provided with a second window 5202 to form the pixel electrode 110. The pixel circuit area 100 is an area of ​​the ultrasonic transducer imaging array composed of a plurality of pixel electrodes 110, called the Active Area (abbreviated as AA area). The chip ground module 200 is located outside the pixel circuit area 100 and is used to isolate the pixel circuit area 100 to prevent the pixel circuit area 100 from being interfered with by peripheral signals. The chip ground module 200 and the circuit module 300 are arranged side by side in the substrate 500. The circuit module 300 is provided with a large number of metal traces and functional circuits, such as power management, clock, ADC circuit, etc.

[0040] When the ultrasonic transducer is applied to the field of fingerprint recognition, the finger is placed on the screen cover, the ultrasonic transducer is in the transmitting mode, the pixel electrode 110 generates a lower voltage V1, and the excitation electrode (not shown in the figure) drives the upper electrode 2200 of the piezoelectric layer to generate an upper voltage V2. The upper voltage V2 minus the lower voltage V1 obtains a differential voltage, and the differential voltage drives the piezoelectric layer 2100 to vibrate and emit ultrasonic waves. The ultrasonic wave reaches the surface of the finger through the screen cover, and the intensity of the transmitted echo signal of the sound wave at the fingerprint-cover interface varies due to the "valley" and "ridge" structure of the fingerprint. When the ultrasonic transducer is in the receiving mode, the pixel electrode 110 receives the reflected echo signal carrying the fingerprint information and transmits the received reflected echo signal to the circuit module 300. The circuit module 300 is used to perform signal processing on the reflected echo signal collected by the pixel electrode.

[0041] Specifically, the circuit module includes: an analog-to-digital conversion circuit for performing analog-to-digital conversion on the reflected echo signal collected by the pixel electrode; a storage circuit for storing the reflected echo signal after the analog-to-digital conversion; and a fingerprint recognition circuit for processing the reflected echo signal to confirm whether it is the target fingerprint. The analog-to-digital conversion circuit, storage circuit, and fingerprint recognition circuit are not shown in the figure. In some embodiments, the fingerprint recognition circuit can also be implemented by another chip, which can be provided in connection with the ultrasonic transducer.

[0042] In the embodiment of the present application, an ultrasonic transducer is placed inside the display device, and the above process is used to perform biometric identification and recognition for user authentication.

[0043] In the embodiment of the present application, the pixel electrode 110 is grounded through the metal wiring, interlayer vias and multi-layer metal layer 5102 below the pixel electrode 110 , thereby preventing the pixel electrode 110 from being interfered by the voltage signal of the acoustic layer 200 .

[0044] In order to make the piezoelectric layer 2100 emit ultrasonic waves, it is usually necessary to apply a high-voltage signal of tens to hundreds of volts to the electrode 2200 on the piezoelectric layer. Since a higher voltage is required to polarize the piezoelectric layer 2100, the higher voltage will make the small-pitch metal blocks and suspended metal blocks of the circuit module 300 easily broken down, affecting the yield of the chip.

[0045] In addition, the circuit module 300 and the acoustic layer 2000 overlap in their projected areas on the substrate 500. The circuit module 300 is easily interfered with by the high-voltage signal generated by the electrode 2200 on the piezoelectric layer, resulting in an increase in the time domain noise of the signal in the circuit module and a reduction in the signal-to-noise ratio.

[0046] See also Figure 5 and Figure 6 , Figure 6 for Figure 5Description of the lateral structure along the AA cross-section. A chip 1000 according to an embodiment of the present application is disposed below an acoustic layer 2000. The acoustic layer 2000 includes a piezoelectric layer 2100, an electrode 2200 on the piezoelectric layer, and a protective layer 2300. The chip 1000 includes: a substrate 500, a circuit module 300, and a conductive shielding layer 600. The conductive shielding layer 600 is disposed between the circuit module 300 and the acoustic layer 2000, and the projection of the conductive shielding layer 600 on the substrate 500 at least covers the projection of the circuit module 300 on the substrate 500. The conductive shielding layer 600 is grounded.

[0047] According to an embodiment of the present application, the chip 1000 is provided with a conductive shielding layer 600, which is disposed between the circuit module 300 and the acoustic layer 2000. The projection of the conductive shielding layer 600 on the substrate 500 at least covers the projection of the circuit module 300 on the substrate 500, and the conductive shielding layer 600 is connected to the chip ground module 200. During the polarization process of the acoustic layer 2000, the presence of the conductive shielding layer 600 also effectively reduces the occurrence of breakdown of the fine-pitch metal blocks and the suspended metal blocks in the circuit module 300, thereby ensuring the chip manufacturing yield.

[0048] In other specific implementations of the present invention, the circuit module 300 is disposed within the substrate 500, with at least a portion of the circuit module 300 located below the acoustic layer. When the acoustic layer 2000 generates an ultrasonic signal, the induced charge above the acoustic layer 2000 is connected to ground through the conductive shielding layer 600. This reduces interference with the circuit module 300 from the high voltage signal generated by the electrode 2200 on the piezoelectric layer of the chip 1000, thereby improving the signal-to-noise ratio.

[0049] In some specific implementations of the embodiments of this application, see Figure 5 and Figure 6 The chip ground module 200 and the circuit module 300 are arranged side by side in the substrate 500. A first window 5201 is set in the passivation layer 520 above the chip ground module 200, and the metal layer 510 above the chip ground module 200 is exposed through the first window 5201. At least part of the conductive shielding layer 600 passes through the first window 5201 to connect to the metal layer 510 above the chip ground module 200. The conductive shielding layer 600 is grounded through the metal layer 510 above the chip ground module 200.

[0050] In the embodiment of the present application, a first window 5201 is simply provided on the passivation layer above the chip ground module 200 , so that the conductive shielding layer 600 can be grounded through the metal layer 510 of the chip ground module 200 , which simplifies the manufacturing process.

[0051] In some embodiments of the present invention, the thickness of the conductive shielding layer 600 is no greater than 10 microns. Specifically, the thickness of the conductive shielding layer 600 is preferably less than 1 micron. This can prevent the thick conductive shielding layer 600 from affecting the uniformity of the piezoelectric layer 2100.

[0052] In some embodiments of the present invention, the conductive shielding layer 600 may include one of a metal material, a metal oxide semiconductor material, an organic conductive material, a nano-metal conductive material, or a carbon nano-conductive material.

[0053] Specifically, the metal material can be a common metal material such as aluminum, titanium, copper, tungsten, etc. Metal oxide semiconductor materials can be tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). Organic conductive materials can be polythiophene and poly (p-phenylene glycol) (PEDOT), poly (3,4-ethylenedioxythiophene)-polystyrene sulfonic acid (PEDOT:PSS). Nanometal conductive materials can be silver nanowires (AgNWs) and metal mesh. Carbon nanoconductive materials can be graphene and carbon nanotubes.

[0054] In some specific implementations of the embodiments of the present application, such as Figure 7 As shown, the conductive shielding layer 600 includes a conductive layer 610 and a dielectric layer 620, both of which are shaped to fit the circuit module 300. The conductive layer 610 is disposed between the circuit module 300 and the dielectric layer 620, which in turn is disposed between the conductive layer 610 and the acoustic layer 2000 (piezoelectric layer 2100). As can be seen, at least a portion of the conductive layer 610 is connected to the chip ground module 200 and separates the circuit module 300 from the acoustic layer 2000. This allows the induced charge above the acoustic layer 2000 to be directed to ground through the conductive shielding layer when the acoustic layer 2000 generates an ultrasonic signal, reducing interference with the circuit module 300. The dielectric layer 620 covers the conductive layer 610, and its shape matches that of the conductive layer 610. This prevents problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610.

[0055] Specifically, dielectric layer 620 may be at least one of silicon oxide, silicon nitride, a high-K dielectric constant material, and a polymer dielectric material. The high-K dielectric constant of a high-K dielectric constant material is defined relative to the relative dielectric constant of the material. High-K dielectric constant materials may include titanium oxide, zirconium oxide, hafnium oxide, etc. Polymer dielectric materials may include polyimide, etc.

[0056] In some specific implementations of the embodiments of the present application, such as Figure 8 and Figure 9 As shown, Figure 9for Figure 8 Description of the lateral structure cut along the AA section. The conductive shielding layer 600 is at least a part of the top metal layer 5101 above the circuit module 300, and the conductive shielding layer 600 is grounded through the intra-layer routing of the substrate 500 (not shown in the figure). The embodiment of the present application reuses the top metal layer 5101 above the circuit module 300, and the conductive shielding layer 600 is formed synchronously with the top metal layer 5101 above the circuit module 300. There is no need to set up a separate conductive shielding layer 600, which makes the process simpler, improves manufacturing efficiency, and reduces costs. In addition, the conductive shielding layer 600 is at least a part of the top metal layer 5101 above the circuit module 300, and there is no need to set up a dielectric layer to avoid problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610.

[0057] In some specific implementations of the embodiments of the present application, such as Figures 10 to 14 As shown, Figures 11 to 14 for Figure 10 The conductive shielding layer 600 includes at least a portion of the multi-layer metal layer 5102 in the substrate 500. The multi-layer metal layer 5102 is grounded through a portion of at least one metal layer 510. The multi-layer metal layer 5102 is located in multiple parallel planes.

[0058] The projection of the multi-layer metal layer 5102 on the substrate 500 covers the projection of the circuit module 300, thereby increasing the flexibility of the layout of the multi-layer metal layer 5102 according to the actual design of the chip 1000. In other words, the multi-layer metal layer 5102 is arranged at different positions on the chip 1000, which not only ensures the protection of the circuit module 300 but also allows for flexible layout.

[0059] Specifically, at least one of the multi-layer metal layers 5102 in the embodiment of the present application is grounded through an intra-layer routing (not shown in the figure), and the remaining ones are connected to the grounded metal layer 5102 through intra-layer routing (not shown in the figure), or each metal layer 5102 is grounded through an intra-layer routing (not shown in the figure).

[0060] If a single metal layer 5102 cannot cover the circuit module 300, another metal layer 5102 can be arranged to overlap the projection area of ​​the previous metal layer 5102 on the substrate 500, so that the projections of the two metal layers 5102 on the substrate 500 can cover the projection of the circuit module 300 on the substrate 500. Similarly, the arrangement of three metal layers 5102 and four metal layers 5102 has the same effect.

[0061] Furthermore, if Figure 11-14As shown, the projections of the multiple metal layers 5102 on the substrate 500 overlap with each other. Therefore, the projections of the multiple metal layers 5102 on the substrate 500 can completely cover the projection of the circuit module 300 on the substrate 500, thereby preventing gaps between the projections of the multiple metal layers 5102 on the substrate 500, which would reduce the protection effect on the circuit module 300.

[0062] In some embodiments of the present invention, the number of metal layers 5102 can be any number and can be adjusted according to the actual structural layout of the chip 1000.

[0063] like Figure 11 As shown, the conductive shielding layer 600 includes five metal layers 5102, and a portion of the five metal layers 5102 is grounded (the grounding position is not shown in the figure). At the same time, the projection area on the substrate formed by the grounded portions of each metal layer 5102 completely covers the projection of the circuit module 300 on the substrate. Therefore, through this arrangement, the conductive shielding layer 600 composed of the five metal layers 5102 protects the circuit module 300. Figure 12 As shown, the conductive shielding layer 600 may further include four metal layers 5102. Figure 13 As shown, the conductive shielding layer 600 may further include three metal layers 5102. Figure 14 As shown, the conductive shielding layer 600 also includes three metal layers 5102. Figure 14 The layout of the three metal layers 5102 is similar to Figure 13 The layout of the three metal layers 5102 is different. It can be understood that the layout of the multiple metal layers 5102 can be diverse, thereby achieving the diversity of the structure of the chip 1000.

[0064] In addition, the number of metal layers 5102 is not limited to five or three in the above embodiments, and can be arranged in different numbers according to actual usage requirements, specifically depending on the design of the chip 1000.

[0065] Specifically, when the conductive shielding layer 600 is part of the multi-layer metal layer 5102 in the substrate 500, a dielectric layer (not shown in the figure) is set between the conductive shielding layer 600 and the passivation layer 520. The dielectric layer in the substrate can be a silicon oxide layer.

[0066] Furthermore, the conductive shielding layer 600 includes at least a portion of the multi-layer metal layer 5102 in the substrate 500 , and there is no need to provide a dielectric layer to avoid problems such as poor bonding between the piezoelectric layer 2100 of the acoustic layer 2000 and the conductive layer 610 .

[0067] In some embodiments of the present invention, the sheet resistance of the conductive shielding layer 600 is between 0.1Ω / □ and MΩ / □. Specifically, the sheet resistance of the conductive shielding layer 600 can be selected based on actual use to ensure effective shielding of the induced charge of the operating voltage of the acoustic layer 2000.

[0068] In addition, the film forming method of the conductive shielding layer 600 of the chip 1000 of the embodiment of the present application can be, for example, using a metal material or a metal oxide semiconductor material, which can be formed by physical deposition (PVD), such as sputtering or evaporation. It can also be formed by chemical assisted deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), etc. It can also be formed by atomic layer deposition (ALD). If an organic conductive material, a nano-metal conductive material or a carbon nano-material is selected, it can also be formed by a series of solution coating methods such as spin coating, spray coating, roller coating, and slit coating. The patterning of the conductive shielding layer 600 can be achieved by lift-off, dry etching or wet etching. Among them, the lift-off method can be understood as a stripping process (lift-off), which is to obtain a patterned photoresist structure or a metal mask (shadow mask) on the substrate using a photolithography process, and then use a coating process to coat the target coating on the mask. Then, a stripping solution (also called a stripping solution) is used to dissolve the photoresist or mechanically remove the metal hard mask to obtain a target graphic structure consistent with the pattern.

[0069] See also Figures 1-14 , an embodiment of the present application further provides an ultrasonic transducer, comprising: a chip 1000 and an acoustic layer 2000 , wherein the chip 1000 is the chip 1000 described in any of the above embodiments.

[0070] See also Figure 15 An embodiment of the present application further provides an electronic device, comprising: a screen 180 and the above-mentioned ultrasonic transducer, wherein the ultrasonic transducer is attached to the screen 180 through the substrate 500 of the ultrasonic transducer.

[0071] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A chip for an ultrasonic transducer, the chip being arranged below an acoustic layer, characterized in that: The chip comprises: substrate; A circuit module, wherein the circuit module is disposed in the substrate; A conductive shielding layer is disposed between the circuit module and the acoustic layer, and a projection of the conductive shielding layer on the substrate at least covers a projection of the circuit module on the substrate, and the conductive shielding layer is grounded.

2. The chip according to claim 1, characterized in that: At least part of the circuit module is located below the acoustic layer.

3. The chip according to claim 1, characterized in that: The chip further comprises: a chip ground module, wherein the chip ground module and the circuit module are arranged in parallel in the substrate; A first window is set in the passivation layer above the chip ground module, and the metal layer above the chip ground module is exposed through the first window. At least part of the conductive shielding layer passes through the first window to connect to the metal layer above the chip ground module, and the conductive shielding layer is grounded through the metal layer above the chip ground module.

4. The chip according to claim 1, characterized in that: The conductive shielding layer comprises a conductive layer and a dielectric layer with adapted shapes, wherein the conductive layer is arranged between the circuit module and the dielectric layer, and the dielectric layer is arranged between the conductive layer and the acoustic layer.

5. The chip according to claim 1, characterized in that: The conductive shielding layer is at least a portion of the top metal layer above the circuit module, and the conductive shielding layer is grounded through an intra-layer routing of the substrate.

6. The chip according to claim 1, characterized in that: The conductive shielding layer is at least a part of the multi-layer metal layer above the circuit module. The multi-layer metal layer is grounded through a part of at least one of the metal layers. The multi-layer metal layers are in multiple planes parallel to each other. A dielectric layer in the substrate is arranged between the conductive shielding layer and the passivation layer above it.

7. The chip according to claim 6, characterized in that: The projections of the multiple metal layers on the substrate overlap each other.

8. The chip according to claim 1, characterized in that: The chip further comprises: A pixel circuit region, wherein a second window is provided on the passivation layer above the pixel circuit region, and a metal layer above the pixel circuit region is exposed through the second window to form a pixel electrode, and the chip ground is provided at the periphery of the pixel circuit region; In the transmitting mode, the pixel electrode outputs a driving signal to drive the piezoelectric layer to vibrate and emit ultrasonic waves. In the receiving mode, the pixel electrode receives a reflected echo signal and transmits the reflected echo signal to the circuit module for signal processing.

9. The chip according to claim 8, characterized in that: The circuit module comprises: An analog-to-digital conversion circuit, used for performing analog-to-digital conversion on the reflected echo signal collected by the pixel electrode; The circuit module also includes a storage circuit for storing the reflected echo signal after the analog-to-digital conversion; The circuit module also includes a fingerprint recognition circuit for processing the reflected echo signal to confirm whether it is a target fingerprint.

10. The chip according to claim 9, characterized in that: The acoustic layer includes a piezoelectric layer, an electrode on the piezoelectric layer and a protective layer. The chip is arranged below the piezoelectric layer. The excitation electrode drives the electrode on the piezoelectric layer to generate an upper voltage, and the pixel electrode generates a lower voltage. The upper voltage minus the lower voltage obtains a differential voltage. The differential voltage drives the piezoelectric layer to vibrate and emit ultrasonic waves to the outside.

11. The chip according to claim 1, characterized in that: The square resistance of the conductive shielding layer is between 0.1Ω / □ and MΩ / □.

12. The chip according to claim 1, characterized in that: The thickness of the conductive shielding layer is less than 1 micron.

13. An ultrasonic transducer, characterized in that: include: A chip and an acoustic layer, wherein the chip is the chip described in any one of claims 1 to 12.

14. A device, characterized in that include: A screen and the ultrasonic transducer as claimed in claim 13, wherein the ultrasonic transducer is attached to the screen via a substrate of the ultrasonic transducer.

Images