Chip high and low temperature batch test system

Abstract

The utility model provides a chip high and low temperature batch test system, comprising an incubator internal unit, a programmable general input and output pin controller on a chip test substrate, and a power supply demultiplexer, a signal demultiplexer and N chips to be tested which are connected with the programmable general input and output pin controller; and the incubator external unit comprises a power supply, test equipment and a microcontroller substrate. According to the utility model, the external microcontroller substrate is adopted to control the programmable general input / output pin controller in the incubator so as to drive the power supply demultiplexer, the signal demultiplexer and the N chips to be tested, so that the chips to be tested in corresponding channels execute required test items under corresponding power supplies; the problem of low efficiency during high-temperature and low-temperature testing of the chips is solved, the number of the chips to be tested in a single-time incubator is increased, the testing throughput rate is increased, the average testing time is shortened, the chip testing cost is effectively reduced, and huge economic benefits are brought.

Description

Technical Field

[0001] The utility model relates to the field of chip testing, and more specifically to a chip high and low temperature batch testing system. Background Art

[0002] With the vigorous development of information technology, chips, as the cornerstone of electronic information systems, play an increasingly important role. Power chips are often used to power electronic systems. They generally have fewer functional pins and are tested using a single-wire interface. In order to ensure the reliability of power chips, high and low temperature tests must be performed on the finished products after packaging. For example, the operating temperature range of industrial-grade chips is -40℃ to +85℃, and the operating temperature range of automotive-grade chips is -40℃ to +125℃.

[0003] At present, the high and low temperature test of chips mostly places the chip and substrate in an incubator, and the external substrate with a microcontroller, power supply, test instrument, etc. are connected to the substrate inside the incubator through cables. When the chip heats up or cools down to the target temperature, the microcontroller generates a communication signal to put the chip into test mode. The chip is powered by the power supply device, and various indicators are measured by the test equipment. The measurement mode is changed through the communication signal to obtain different measurement results.

[0004] The existing test scheme can basically complete the high and low temperature test of the chip, but it has obvious disadvantages. Since the heating and cooling of the chip is a slow process, for example, it takes about 20 minutes to heat up from 25℃ to 125℃, and it takes about 25 minutes to cool down from 25℃ to -40℃, which means that on average, the high and low temperature test of each chip takes 20 to 25 minutes. This is a very slow process. One method is to place more chips and substrates in the incubator, but the incubator cables are very limited and cannot directly control more substrates. Moreover, the cables need to be punched into the incubator. Adding cables will cause the incubator temperature to leak, affecting the test accuracy. Utility Model Content

[0005] The utility model aims to solve the problem that the existing chip temperature test cannot be carried out in batches, and proposes a chip high and low temperature batch test system.

[0006] The technical solution of the utility model is:

[0007] The utility model provides a chip high and low temperature batch testing system, the system comprising:

[0008] The incubator internal unit is placed inside the incubator and includes a chip test substrate, wherein the chip test substrate includes a programmable general purpose input and output pin controller and a power multiplexer, a signal multiplexer and N chips to be tested connected thereto;

[0009] The external unit of the temperature chamber is placed outside the temperature chamber, including a power supply, a test device and a microcontroller substrate;

[0010] The power supply is connected to a power multiplexer, and is connected to a power supply terminal of each chip to be tested through the power multiplexer, so as to supply power to the chip to be tested;

[0011] The test device is connected to the signal demultiplexer and connected to the signal end of each chip to be tested through the signal demultiplexer, and is used to provide test signal excitation and receive response signal for the chip to be tested;

[0012] The microcontroller substrate is connected to a programmable general purpose input and output pin controller and is used to drive each chip to be tested, a power multiplexer and a signal multiplexer.

[0013] Furthermore, the power supply is connected to a power multiplexer via a cable; the test equipment is connected to a signal multiplexer via a cable; and the microcontroller substrate is connected to a programmable general purpose input and output pin controller via a cable.

[0014] Furthermore, the testing device includes a signal generator and a monitoring module.

[0015] Furthermore, the monitoring module includes an oscilloscope, a voltmeter and / or an ammeter.

[0016] Furthermore, the communication terminal of each chip to be tested is connected to a programmable general purpose input and output pin controller, the power terminal is connected to a power multiplexer, and the signal terminal is connected to a signal multiplexer.

[0017] Beneficial effects of the utility model:

[0018] The batch testing system of the utility model adopts an external microcontroller substrate to control a programmable general-purpose input-output pin controller located inside a temperature chamber to drive a power multiplexer, a signal multiplexer and N chips to be tested, so that the chips to be tested in corresponding paths execute the required test items under the corresponding power supply; it solves the problem of low efficiency during high and low temperature testing of chips, improves the test throughput rate by increasing the number of chips to be tested in a single temperature chamber, reduces the average test time, effectively reduces the chip testing cost, and brings huge economic benefits.

[0019] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present invention.

[0021] Figure 1 A system block diagram according to an embodiment of the utility model is shown. DETAILED DESCRIPTION

[0022] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein.

[0023] like Figure 1 As shown, the utility model provides a chip high and low temperature batch testing system, the system comprising:

[0024] The incubator internal unit is placed inside the incubator and includes a chip test substrate, wherein the chip test substrate includes a programmable general purpose input and output pin controller 4 and a power multiplexer 5, a signal multiplexer 6 and N chips to be tested connected thereto;

[0025] The temperature chamber external unit is placed outside the temperature chamber and includes a power supply 2, a test device 3 and a microcontroller substrate 1;

[0026] The power supply 2 is connected to the power multiplexer 5, and is connected to the power supply terminal of each chip to be tested through the power multiplexer 5, so as to supply power to the chip to be tested;

[0027] The test device 3 is connected to the signal demultiplexer 6, and is connected to the signal end of each chip to be tested through the signal demultiplexer 6, and is used to provide test signal excitation and receive response signal for the chip to be tested;

[0028] The microcontroller substrate 1 is connected to a programmable general purpose input / output pin controller 4 for driving each chip to be tested, a power multiplexer 5 and a signal multiplexer 6 .

[0029] Further, the power supply 2 is connected to the power multiplexer 5 through a cable; the test equipment 3 is connected to the signal multiplexer 6 through a cable; the microcontroller substrate 1 is connected to the programmable general purpose input and output pin controller 4 through a cable;

[0030] The testing device 3 includes a signal generator and a monitoring module; the monitoring module includes an oscilloscope, a voltmeter and / or an ammeter.

[0031] The communication end of each chip to be tested is connected to a programmable general purpose input / output pin controller 4 , the power end is connected to a power multiplexer 5 , and the signal end is connected to a signal multiplexer 6 .

[0032] When implementing:

[0033] After the system is connected, the temperature of the thermostat can be raised or lowered.

[0034] After the temperature reaches the target temperature, the microcontroller substrate 1 generates I 2 C control signal, and tests are performed on the corresponding chips in turn; the communication signal is fully compatible with single-chip testing, ensuring the consistency and reusability of the test program.

[0035] Microcontroller base board 1 through I 2 C is connected to the programmable general purpose input and output pin controller 4 to drive the target chip to be tested to enter the test mode.

[0036] The microcontroller substrate 1 controls the power multiplexer 5 to load power to the target chip to be tested.

[0037] The microcontroller substrate 1 controls the signal demultiplexer 6 to load the test signal onto the target chip to be tested and monitor the output value of the target chip to be tested.

[0038] The test of a chip can be completed in the above manner.

[0039] Repeat the above steps and test the corresponding chips in turn until all chips are tested. Since the heating and cooling time is 20 to 25 minutes, the test of a chip takes hundreds of milliseconds. 2 The communication time introduced by C and the time for testing multiple chips internally are negligible compared to the tens of minutes of temperature rise and fall time. The entire system completes the test of N chips in the time it originally took to test one chip, greatly improving the test efficiency.

[0040] The various embodiments of the utility model have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A chip high and low temperature batch testing system, characterized in that: The system includes: The incubator internal unit is placed inside the incubator and includes a chip test substrate, wherein the chip test substrate includes a programmable general purpose input / output pin controller (4) and a power multiplexer (5), a signal multiplexer (6) and N chips to be tested connected thereto; The temperature chamber external unit is placed outside the temperature chamber and includes a power supply (2), a test device (3) and a microcontroller substrate (1); The power supply (2) is connected to a power multiplexer (5), and is connected to the power supply terminal of each chip to be tested via the power multiplexer (5), so as to supply power to the chip to be tested; The test device (3) is connected to a signal demultiplexer (6), and is connected to a signal terminal of each chip to be tested via the signal demultiplexer (6), and is used to provide a test signal stimulus to the chip to be tested and receive a response signal; The microcontroller substrate (1) is connected to a programmable general purpose input / output pin controller (4) and is used to drive each chip to be tested, a power multiplexer (5) and a signal multiplexer (6).

2. The chip high and low temperature batch testing system according to claim 1, characterized in that: The power supply (2) is connected to a power multiplexer (5) via a cable; the test equipment (3) is connected to a signal multiplexer (6) via a cable; and the microcontroller substrate (1) is connected to a programmable general purpose input / output pin controller (4) via a cable.

3. The chip high and low temperature batch testing system according to claim 1, characterized in that: The testing device (3) comprises a signal generator and a monitoring module.

4. The chip high and low temperature batch testing system according to claim 3, characterized in that: The monitoring module includes an oscilloscope, a voltmeter and / or an ammeter.

5. The chip high and low temperature batch testing system according to claim 1, characterized in that: The communication end of each chip to be tested is connected to a programmable general purpose input / output pin controller (4), the power supply end is connected to a power multiplexer (5), and the signal end is connected to a signal multiplexer (6).

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