Display device and mobile electronic device

Abstract

The utility model relates to a display device and a mobile electronic device, and the display device comprises a semiconductor backboard which comprises a semiconductor substrate; a light-emitting element back plate disposed on the semiconductor back plate; and a light-emitting element layer disposed on the light-emitting element backplane, the light-emitting element layer including: a pixel defining film dividing a plurality of sub-pixels; a first electrode of each sub-pixel disposed in the opening of the pixel defining film; an intermediate layer covering the first electrode in the opening portion and covering the pixel defining film between the sub-pixels arranged adjacent to each other, a portion of the intermediate layer being broken; and a second electrode covering the intermediate layer and disposed in common to the plurality of sub-pixels, the intermediate layer including an imprint region in which a part of the imprint region is imprint between the sub-pixels disposed adjacent to each other.

Description

Technical Field

[0001] The utility model relates to a display device and a mobile electronic device Background Art

[0002] A wearable device is being developed in the form of glasses or helmets that forms a focal point close to the user's eyes. For example, the wearable device may be an HMD (head mounted display) device or AR glasses. This wearable device provides an augmented reality (AR) screen or a virtual reality (VR) screen to the user.

[0003] In order for users to use wearable devices such as HMD devices or AR glasses for a long time without dizziness, a display specification of at least 2000 PPI (pixels per inch) is required. For this reason, high-resolution small organic light-emitting display devices, namely OLEDoS (Organic Light Emitting Diode on Silicon) technology, are emerging. OLEDoS (Organic Light Emitting Diode on Silicon) is a technology that configures organic light-emitting diodes (OLED) on a semiconductor wafer substrate configured with CMOS (Complementary Metal Oxide Semiconductor).

[0004] As the interval between pixels of a display panel using OLEDoS technology becomes narrower, unexpected leakage current may be generated between adjacent pixels. It is known that leakage current may be generated through a portion of the conductive layer in the intermediate layer between the pixel electrode (e.g., anode electrode) and the common electrode (e.g., cathode electrode), which is known to be the cause of color crosstalk between adjacent pixels. Utility Model Content

[0005] The problem to be solved by the utility model is to provide a display device and a mobile electronic device, which prevent leakage current and color crosstalk by disconnecting at least a part of an intermediate layer arranged between a pixel electrode and a common electrode between adjacent pixels.

[0006] The problems of the present invention are not limited to the problems mentioned above, and those skilled in the art can clearly understand other problems not mentioned from the following description.

[0007] A display device according to one embodiment for solving the above-mentioned problem includes: a semiconductor backplane including a semiconductor substrate; a light-emitting element backplane arranged on the semiconductor backplane; and a light-emitting element layer arranged on the light-emitting element backplane, wherein the light-emitting element layer includes: a pixel defining film dividing a plurality of sub-pixels; a first electrode of each of the sub-pixels arranged in an opening of the pixel defining film; an intermediate layer covering the first electrode in the opening and covering the pixel defining film between adjacently arranged sub-pixels, and a portion of the intermediate layer being disconnected; and a second electrode covering the intermediate layer and being commonly arranged on the plurality of sub-pixels.

[0008] The intermediate layer includes an embossed region, a portion of which is embossed between the adjacent sub-pixels.

[0009] In the embossed region of the intermediate layer, at least one conductive layer included in the intermediate layer is disconnected.

[0010] A method for manufacturing a display device according to one embodiment for solving the above-mentioned problem comprises: a step of forming a driving element layer on a substrate; a step of forming a wiring layer on the driving element layer; and a step of forming a light-emitting element layer on the wiring layer, wherein the step of forming the light-emitting element layer comprises: a step of forming a first electrode for each of a plurality of sub-pixels and a pixel defining film for dividing the plurality of sub-pixels on the wiring layer; a step of vapor depositing an intermediate layer; a step of aligning a Joule heating device on the substrate on which the intermediate layer is vapor deposited, and using the heating wiring of the Joule heating device to remove a portion of the intermediate layer corresponding to adjacent sub-pixels; and a step of vapor depositing a second electrode.

[0011] The Joule heating device includes: a board having a power supply wiring for applying a heating voltage; an insulating layer arranged on the board; and a heating wiring arranged on the insulating layer and electrically connected to the power supply wiring via a through hole penetrating the insulating layer.

[0012] The step of removing a portion of the intermediate layer includes: a step of aligning the Joule heating device on the substrate on which the intermediate layer is evaporated; a step of applying the heating voltage to the power wiring to heat the heating wiring; and a step of bringing the heating wiring and the intermediate layer into contact if the heating wiring reaches a specified temperature, thereby removing a portion of the intermediate layer.

[0013] The specified temperature is greater than or equal to 400°C.

[0014] The step of removing a portion of the intermediate layer includes: a step of aligning the Joule heating device on the substrate on which the intermediate layer is evaporated; a step of bringing the heating wiring into contact with the intermediate layer; a step of applying the heating voltage to the power wiring to heat the heating wiring; and a step of causing the heating wiring to reach a specified temperature, thereby removing a portion of the intermediate layer.

[0015] The specified temperature is greater than or equal to 400°C.

[0016] The material of the heat generating wiring includes at least one of Ti, Mo, W, TiN and TiW.

[0017] The substrate is a semiconductor substrate.

[0018] The driving element layer is a semiconductor backplane including MOSFETs.

[0019] The wiring layer includes a light emitting element backplane, which electrically connects the semiconductor backplane and the light emitting element layer.

[0020] A method for manufacturing a display device according to one embodiment for solving the above-mentioned problem comprises: a step of forming a driving element layer on a substrate; a step of forming a wiring layer on the driving element layer; and a step of forming a light-emitting element layer on the wiring layer, wherein the step of forming the light-emitting element layer comprises: a step of forming a first electrode for each of a plurality of sub-pixels and a pixel defining film for dividing the plurality of sub-pixels on the wiring layer; a step of vapor depositing an intermediate layer; a step of aligning a stamping device on the substrate on which the intermediate layer is vapor deposited, and using a stamping component of the stamping device to stamp a portion of the intermediate layer corresponding to adjacent sub-pixels; and a step of vapor depositing a second electrode.

[0021] The stamping device comprises: a board; an insulating layer arranged on the board; and a stamping component arranged on the insulating layer.

[0022] The step of imprinting a portion of the intermediate layer includes: a step of aligning the imprinting device on the substrate on which the intermediate layer is evaporated; and a step of the imprinting component pressing the substrate with the imprinting device so as to press a portion of the intermediate layer corresponding to the adjacent sub-pixels.

[0023] The distal end of the stamping member has a pointed conical form.

[0024] In the step of embossing a portion of the intermediate layer, the intermediate layer forms an embossed region in which a portion thereof is embossed between the adjacently arranged sub-pixels.

[0025] In the embossed region of the intermediate layer, at least one conductive layer included in the intermediate layer is disconnected.

[0026] At least one included in the intermediate layer includes at least one layer of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), a charge generation layer (CGL), and a P-doped layer (PHIL).

[0027] Details of other embodiments are included in the detailed description and drawings.

[0028] According to the display device and the manufacturing method thereof of the embodiment, at least a portion of the intermediate layer disposed between the pixel electrode and the common electrode is disconnected between adjacent pixels, thereby preventing leakage current and color crosstalk.

[0029] The effects according to the embodiments are not limited to the contents of the above examples, and more diverse effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a head mounted display device according to an embodiment.

[0031] Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted display device.

[0032] Figure 3 is a perspective view showing a head mounted display device according to an embodiment.

[0033] Figure 4 is an exploded perspective view showing a display device according to an embodiment.

[0034] Figure 5 It is shown Figure 4 A layout diagram of an example of a display panel shown.

[0035] Figure 6 is a block diagram showing a display device according to an embodiment.

[0036] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0037] Figure 8 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0038] Fig. 9 It is shown that the Figure 8 A cross-sectional view of an example of a display device.

[0039] Fig.10 is a flow chart illustrating a method for manufacturing a display device according to an embodiment.

[0040] Figures 11 to 16 are cross-sectional views sequentially illustrating processes of a method for manufacturing a display device according to an embodiment.

[0041] Fig.17 is a flow chart illustrating a method for manufacturing a display device according to an embodiment.

[0042] Figures 18 to 23 are cross-sectional views sequentially illustrating processes of a method for manufacturing a display device according to an embodiment.

[0043] (Explanation of Reference Numerals)

[0044] SSUB: Semiconductor Substrate

[0045] SBP: Semiconductor Backplane

[0046] EBP: Light Emitting Element Backplane

[0047] EML: Emission Element Layer

[0048] 1300: Joule heating equipment

[0049] 1310: Plate

[0050] 1311: Power wiring

[0051] 1312: Through hole

[0052] 1320: Insulation layer

[0053] 1330: Heating Wiring DETAILED DESCRIPTION

[0054] If you refer to the attached Figure 1 The advantages and features of the utility model and the methods for achieving them will become clear from the detailed embodiments described below. However, the utility model is not limited to the embodiments disclosed below, and will be implemented in a variety of different forms. The embodiments are only provided to make the disclosure of the utility model complete and to fully inform the scope of the utility model to those who have common knowledge in the technical field to which the utility model belongs. The utility model is only defined by the scope of the claims.

[0055] Reference to an element or layer being "on" another element or layer includes all situations where the element is directly on top of the other element or has another layer or other element in between. The same reference numerals throughout the specification refer to the same components. The shapes, sizes, ratios, angles, quantities, etc. disclosed in the drawings used to illustrate the embodiments are exemplary, and the present invention is not limited to the matters shown in the drawings.

[0056] Although the terms first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component within the technical concept of the present disclosure.

[0057] The various features of the various embodiments of the present invention may be partially or completely combined or combined with each other, and may be technically linked and driven in various ways. The various embodiments may be implemented separately or together in an associated relationship.

[0058] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0059] Figure 1 is a perspective view showing a head mounted display device according to an embodiment. Figure 2 It is shown Figure 1 An exploded perspective view of an example of a head-mounted display device.

[0060] Reference Figure 1 and Figure 2 According to one embodiment, a head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device storage portion 110, a storage cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted strap 140, an intermediate frame 160, a first optical component 151, a second optical component 152, a control circuit board 170 and a connector.

[0061] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is connected to the reference Figures 4 to 23 The display device 10 described above is substantially the same. Figures 4 to 23 The description of replaces the description of the first display device 10_1 and the second display device 10_2.

[0062] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0063] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170 and between the second display device 10_2 and the control circuit board 170. The middle frame 160 supports and fixes the first display device 10_1, the second display device 10_2 and the control circuit board 170.

[0064] The control circuit board 170 may be disposed between the middle frame 160 and the display device storage portion 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. Alternatively, the control circuit board 170 may convert an image source input from the outside into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0065] The control circuit board 170 may transmit the digital video data DATA of the left-eye image that is most suitable for the user's left eye to the first display device 10_1, and transmit the digital video data DATA of the right-eye image that is most suitable for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0066] The display device storage portion 110 serves to store the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical component 151, the second optical component 152, the control circuit board 170, and the connector. The storage cover 120 is configured to cover an open side of the display device storage portion 110. The storage cover 120 may include a first eyepiece 131 configured for the user's left eye and a second eyepiece 132 configured for the user's right eye. Figure 1 and Figure 2 In the embodiment, the first eyepiece 131 and the second eyepiece 132 are separately configured, but the embodiments of the present specification are not limited thereto. The first eyepiece 131 and the second eyepiece 132 may be integrated into one.

[0067] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical component 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical component 152. Therefore, the user may view the image of the first display device 10_1 magnified into a virtual image by the first optical component 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified into a virtual image by the second optical component 152 through the second eyepiece 132.

[0068] The head-mounted strap 140 serves to fix the display device storage unit 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the storage cover 120 can be respectively arranged at the user's left eye and right eye. When the display device storage unit 120 is implemented to be lightweight and small, the head-mounted display device 1 can be equipped with a head-mounted strap 140 instead of the head-mounted strap 140. Figure 3 That kind of glasses frame.

[0069] In addition, the head mounted display device 1 may further include a battery for supplying power, an external storage slot for storing an external memory, an external connection port for receiving an image source, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a WIFI module, or a Bluetooth module.

[0070] Figure 3 is a perspective view showing a head mounted display device according to an embodiment.

[0071] Reference Figure 3 According to an embodiment, the head mounted display device 1_1 may be a display device in which the display device storage portion 120_1 is implemented as a lightweight and compact glasses form. According to an embodiment, the head mounted display device 1_1 may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses frame legs 341, 342, an optical component 320, an optical path conversion component 330, and a display device storage portion 120_1.

[0072] Figure 3 The display device 10_3 shown is similar to the reference Figures 4 to 23 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to as Figures 4 to 23 Description instead.

[0073] The display device storage portion 120_1 may include a display device 10_3, an optical component 320, and an optical path conversion component 330. The image displayed on the display device 10_3 may be magnified by the optical component 320, and the optical path is converted by the optical path conversion component 330 to be provided to the right eye of the user through the right eye lens 312. Thus, the user may view an augmented reality image that is a combination of a virtual image displayed on the display device 10_3 through the right eye and a real image viewed through the right eye lens 312.

[0074] exist Figure 3 The example in the figure is that the display device storage portion 120_1 is configured at the right end of the support frame 350, but the embodiments of this specification are not limited to this. For example, the display device storage portion 120_1 can be configured at the left end of the support frame 350, in which case the image of the display device 10_3 can be provided to the left eye of the user. Alternatively, the display device storage portion 120_1 can be configured entirely at the left end and the right end of the support frame 350, in which case the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0075] Figure 4 is an exploded perspective view showing a display device according to an embodiment. Figure 5 It is shown Figure 4 A layout diagram of an example of a display panel shown. Figure 6 is a block diagram showing a display device according to an embodiment.

[0076] Reference Figure 4 and Figure 5 According to one embodiment, the display device 10 is a device for displaying dynamic images or static images. According to one embodiment, the display device 10 can be applicable to portable electronic devices such as mobile phones (Mobile Phone), smart phones (SmartPhone), tablet PCs (Tablet Personal Computers), mobile communication terminals, electronic manuals, electronic books, portable multimedia players (Portable Multimedia Player, PMP), navigators, ultra-portable mobile personal computers (UltraMobile PC, UMPC). For example, the display device 10 can be applicable to the display part of a television, a notebook, a monitor, an advertising board or the Internet of Things (Internet Of Things, IOT). Alternatively, the display device 10 can be applicable to a head mounted display (Head Mounted Display, HMD) for realizing a smart watch (Smart Watch), a watch phone (Watch Phone), virtual reality and augmented reality.

[0077] The display device 10 according to an embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 and a driving circuit 440 .

[0078] The display panel 410 may be composed of a plane form similar to a quadrilateral. For example, the display panel 410 may have a plane form similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 410, the corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be formed circularly or at right angles in a manner having a predetermined curvature. The plane form of the display panel 410 is not limited to a quadrilateral, and may be formed similarly to other polygons, circles, or ellipses. The plane form of the display device 10 may follow the plane form of the display panel 410, but the embodiments of the present specification are not limited thereto.

[0079] The display panel 410 includes Figure 6 There is a display area DAA where an image is displayed and a non-display area NDA where no image is displayed.

[0080] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of light emission control lines EL, and a plurality of data lines DL.

[0081] The plurality of pixels PX include a light emitting element LE (see Figure 7 ). A plurality of pixels PX may be arranged in a matrix form in the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of light emitting control lines EL may extend in the first direction DR1 and be arranged in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be arranged in the first direction DR1.

[0082] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of light emission control lines EL include a plurality of first light emission control lines EL1 and a plurality of second light emission control lines EL2.

[0083] Each of the plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, SP3 (see Fig. 9 ). The plurality of sub-pixels SP1, SP2, SP3 may include: Figure 7 Such a plurality of pixel transistors are formed by a semiconductor process and are arranged on a semiconductor substrate ( Fig. 9 For example, a plurality of pixel transistors may be formed by CMOS (Complementary Metal Oxide Semiconductor).

[0084] Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines EBL, any one of the plurality of first light-emitting control lines EL1, any one of the plurality of second light-emitting control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0085] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0086] The scanning driving area SDA may be an area where the scanning driving unit 510 and the light emitting driving unit 520 are arranged. Figure 5In the example, the scanning driving unit 510 is configured on the left side of the display area DAA, and the light emitting driving unit 520 is configured on the right side of the display area DAA, but the embodiments of this specification are not limited thereto. For example, the scanning driving unit 510 and the light emitting driving unit 520 can all be configured on the left and right sides of the display area DAA.

[0087] The scanning driving unit 510 includes a plurality of scanning transistors, and the light emitting driving unit 520 includes a plurality of light emitting transistors. The plurality of scanning transistors and the plurality of light emitting transistors are formed by a semiconductor process and formed on a semiconductor substrate ( Fig. 9 For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0088] The scan driving unit 510 may include a write scan signal output unit 511, a control scan signal output unit 512, and a bias scan signal output unit 513. Each of the write scan signal output unit 511, the control scan signal output unit 512, and the bias scan signal output unit 513 may receive a scan timing control signal SCS from the timing control circuit 610. The write scan signal output unit 511 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 610 and sequentially output it to the write scan line GWL. The control scan signal output unit 512 may generate a control scan signal according to the scan timing control signal SCS and sequentially output it to the control scan line GCL. The bias scan signal output unit 513 may generate a bias scan signal according to the scan timing control signal SCS and sequentially output it to the bias scan line EBL.

[0089] The light-emitting driving unit 520 includes a first light-emitting control driving unit 521 and a second light-emitting control driving unit 522. Each of the first light-emitting control driving unit 521 and the second light-emitting control driving unit 522 can receive a light-emitting timing control signal ECS from the timing control circuit 610. The first light-emitting control driving unit 521 can generate a first light-emitting control signal according to the light-emitting timing control signal ECS and output it to the first light-emitting control line EL1 in sequence. The second light-emitting control driving unit 522 can generate a second light-emitting control signal according to the light-emitting timing control signal ECS and output it to the second light-emitting control line EL2 in sequence.

[0090] The data driving area DDA may be an area where the data driving unit 530 is configured. The data driving unit 530 includes a plurality of data transistors, which may be formed by a semiconductor process and formed on a semiconductor substrate ( Fig. 9 For example, a plurality of data transistors may be formed of CMOS.

[0091] The data driving unit 530 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 610. The data driving unit 530 may convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driving unit 510, and the data voltage is supplied to the selected sub-pixels SP1, SP2, and SP3.

[0092] The pad area PDA includes a plurality of pads PD arranged in the first direction DR1. Each of the plurality of pads PD may not be covered by a cover layer ( Fig. 9 CVL) and polarizer cover and are exposed.

[0093] The heat dissipation layer 420 may overlap the display panel 410 in the thickness direction of the display panel 410, that is, in the third direction DR3. The heat dissipation layer 420 may be disposed on one side of the display panel 410, for example, on the back side. The heat dissipation layer 420 serves to dissipate heat generated in the display panel 410. The heat dissipation layer 420 may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

[0094] The circuit board 430 can be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 410 using a conductive adhesive component such as anisotropic conductive film. The circuit board 430 can be a flexible printed circuit board or a flexible film having a soft material. Figure 4 The example in FIG. 4 is that the circuit board 430 is unfolded, but the circuit board 430 may be bent. In this case, one end of the circuit board 430 may be disposed on the back of the display panel 410. One end of the circuit board 430 may be the opposite end of the other end of the circuit board 430 connected to the plurality of pads PD of the pad area PDA of the display panel 410 using a conductive adhesive component.

[0095] The timing control circuit 610 may receive digital video data and timing signals from the outside. The timing control circuit 610 may generate a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 410 according to the timing signals. The timing control circuit 610 may output the scan timing control signal SCS to the scan driving section 510 and the light emission timing control signal ECS to the light emission driving section 520. The timing control circuit 610 may output the digital video data and the data timing control signal DCS to the data driving section 530.

[0096] The power supply circuit 450 can generate a plurality of panel driving voltages according to the power supply voltage from the outside. For example, the power supply circuit 450 generates a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT to supply to the display panel 410. The description of the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be combined with Figure 7 And will be described later.

[0097] The timing control circuit 610 and the power supply circuit 450 can be formed by integrated circuits IC (integrated circuit) and attached to one side of the circuit board 430. The scanning timing control signal SCS, the light emitting timing control signal ECS, the digital video data DATA and the data timing control signal DCS of the timing control circuit 610 can be supplied to the display panel 410 through the circuit board 430. The first driving voltage VSS, the second driving voltage VDD and the third driving voltage VINT of the power supply circuit 450 can be supplied to the display panel 410 through the circuit board 430.

[0098] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0099] Reference Figure 7 , the first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first light-emitting control line EL1, the second light-emitting control line EL2 and the data line DL. In addition, the first sub-pixel SP1 can be connected to the first drive voltage line VSL that applies the first drive voltage VSS equivalent to the low potential voltage, the second drive voltage line VDL that applies the second drive voltage VDD equivalent to the high potential voltage, and the third drive voltage line VIL that applies the third drive voltage VINT equivalent to the initialization voltage. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. At this time, the first drive voltage VSS can be a voltage lower than the third drive voltage VINT. The second drive voltage VDD can be a voltage higher than the third drive voltage VINT.

[0100] The first sub-pixel SP1 includes a light emitting element LE (Light Emitting Element) and a pixel driving circuit PC connected to the light emitting element LE. The pixel driving circuit PC includes a plurality of transistors T1 to T6, a first capacitor C1, and a second capacitor C2.

[0101] The light emitting element LE emits light according to the driving current Ids flowing into the channel of the first transistor T1. The light emission of the light emitting element LE may be proportional to the driving current Ids. The light emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. It may be that the first electrode of the light emitting element LE is connected to the drain electrode of the fourth transistor T4, and the second electrode is connected to the first driving voltage line VSL. It may be that the first electrode of the light emitting element LE is an anode electrode (or a pixel electrode), and the second electrode of the light emitting element LE is a cathode electrode (or a common electrode). The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode, but the embodiments of the present specification are not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0102] The first transistor T1 may be a driving transistor that controls a source-drain current Ids (hereinafter referred to as a "driving current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0103] The second transistor T2 can be configured between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Thus, the data voltage of the data line DL can be applied to one electrode of the first capacitor C1. The second transistor ST2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0104] The third transistor T3 may be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by the write control signal of the control scan line GCL to connect the first node N1 to the second node N2. Thus, the gate electrode of the first transistor T1 is connected to the source electrode, and therefore, the first transistor T1 may work as a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0105] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light emission control signal of the first light emission control line EL1 to connect the second node N2 to the third node N3. Thus, the driving current of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first light emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0106] The fifth transistor T5 can be configured between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL and the third node N3 is connected to the third driving voltage line VIL. Thus, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0107] The sixth transistor T6 can be configured between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second light emitting control signal of the second light emitting control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Thus, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second light emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0108] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0109] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0110] The first node N1 is a connection point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a connection point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a connection point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0111] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiments of the present specification are not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, each of a portion of the transistors in the first to sixth transistors T1 to T6 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0112] exist Figure 7 In the example, the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors C1 and C2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 7 For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 7 As shown.

[0113] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be combined with Figure 7 The equivalent circuit diagram of the first sub-pixel SP1 described above is substantially the same, and therefore, descriptions of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 are omitted in this specification.

[0114] Figure 8 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0115] Reference Figure 8 Each of the plurality of pixels PX includes a first emission area EA1 of a first sub-pixel SP1, a second emission area EA2 of a second sub-pixel SP2, and a third emission area EA3 of a third sub-pixel SP3.

[0116] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a rectangular, square, or rhombus-like quadrilateral plane form. For example, the first light emitting area EA1 may have a rectangular plane form having a short side in the first direction DR1 and a long side in the second direction DR2. In addition, each of the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane form having a long side in the first direction DR1 and a short side in the second direction DR2.

[0117] The length of the first direction DR1 of the first emission area EA1 may be smaller than that of the second emission area EA2 and the third emission area EA3. The length of the first direction DR1 of the second emission area EA2 and the first direction DR1 of the third emission area EA3 may be substantially the same.

[0118] The length of the first light emitting area EA1 in the second direction DR2 may be greater than the sum of the second light emitting area EA2 and the third light emitting area EA3. The length of the second light emitting area EA2 in the second direction DR2 may be less than the length of the third light emitting area EA3 in the second direction DR2.

[0119] exist Figure 8 In the example, each of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 has a quadrilateral plane form, but the embodiments of the present specification are not limited thereto. For example, each of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 may have a plane form other than a quadrilateral, a circle or an ellipse.

[0120] In each of the plurality of pixels PX, the first light emitting region EA1 and the second light emitting region EA2 may be adjacent in the first direction DR1. In addition, the first light emitting region EA1 and the third light emitting region EA3 may be adjacent in the first direction DR1. In addition, the second light emitting region EA2 and the third light emitting region EA3 may be adjacent in the second direction DR2. The area of ​​the first light emitting region EA1, the area of ​​the second light emitting region EA2, and the area of ​​the third light emitting region EA3 may be different.

[0121] The first light emitting area EA1 may emit light of a first color, the second light emitting area EA2 may emit light of a second color, and the third sub-pixel BP may emit light of a third color. Here, the light of the first color may be light of a cyan wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a red wavelength band. For example, the cyan wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 370nm to 460nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 480nm to 560nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is approximately 600nm to 750nm.

[0122] exist Figure 8 In the example, each of the plurality of pixels PX includes three light emitting areas EA1, EA2, and EA3, but the embodiments of the present specification are not limited thereto. That is, each of the plurality of pixels PX may also include four light emitting areas.

[0123] In addition, the arrangement of the light emitting regions of the plurality of pixels PX is not limited to Figure 8 For example, the light emitting regions of the plurality of pixels PX may be configured as a stripe structure in which the light emitting regions are arranged in the first direction DR1, or a diamond structure in which the light emitting regions are arranged. A hexagonal structure or a hexagonal structure in which light-emitting areas are arranged in a hexagonal planar form.

[0124] Fig. 9 It is shown that the Figure 8 A cross-sectional view of an example of a display device.

[0125] Reference Fig. 9 The display panel 410 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0126] Below, in reference Fig. 9 The display panel 410 includes a semiconductor substrate SSUB such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. However, the display panel 410 of the present invention is not limited to a substrate that must be a semiconductor substrate SSUB. For example, the display panel 410 can be formed to be rigid or flexible. The display panel 410 can be formed of glass or plastic.

[0127] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Figure 4 The first to sixth transistors T1 to T6 are described.

[0128] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first-type dopant. A plurality of well areas WA may be configured on the semiconductor substrate SSUB. The plurality of well areas WA may be regions doped with a second-type dopant. The second-type dopant may be different from the aforementioned first-type dopant. For example, in the case where the first-type dopant is a p-type dopant, the second-type dopant may be an n-type dopant. Alternatively, in the case where the first-type dopant is an n-type dopant, the second-type dopant may be a p-type dopant.

[0129] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0130] Each of the source region SA and the drain region DA may be a region doped with a first type dopant. The gate electrode GE of the pixel transistor PTR may overlap with the well region WA in the third direction DR3. The channel region CH may overlap with the gate electrode GE in the third direction DR3. The source region SA may be arranged on one side of the gate electrode GE, and the drain region DA may be arranged on the other side of the gate electrode GE.

[0131] Each of the plurality of well regions WA further includes a first low-concentration dopant region disposed between the channel region CH and the source region SA and a second low-concentration dopant region disposed between the channel region CH and the drain region DA. The first low-concentration dopant region may be a region having a lower dopant concentration than the source region SA. The second low-concentration dopant region may be a region having a lower dopant concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration dopant region and the second low-concentration dopant region. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, and thus punch-through and hot carrier phenomena may be prevented by a short channel.

[0132] The first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0133] The second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0134] A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0135] A third semiconductor insulating film SINS3 may be disposed on the side of each of the plurality of contact terminals CTE. The top of each of the plurality of contact terminals CTE may not be covered by the third semiconductor insulating film SINS3 but may be exposed. The third semiconductor insulating film SINS3 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0136] A glass substrate or a polymer resin substrate such as polyimide can replace the semiconductor substrate SSUB. In this case, thin film transistors can be arranged on the glass substrate or the polymer resin substrate. The glass substrate is a rigid substrate that does not bend, and the polymer resin substrate is a flexible substrate that can be bent or curled.

[0137] The light emitting element back plate EBP includes first to eighth metal layers ML1-ML8, reflective metal layers RL1-RL4, a plurality of vias VA1-VA10 and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating films INS1-INS10 disposed between the first to sixth metal layers ML1-ML6.

[0138] The first to eighth metal layers ML1-ML8 are connected to a plurality of contact terminals CTE exposed in the semiconductor backplane SBP to realize Figure 4The circuit of the first sub-pixel SP1 shown in the figure. That is, only the first to sixth transistors T1 to T6 are formed on the semiconductor backplane SBP, and the connection between the first to sixth transistors T1 to T6 and the first capacitor C1 and the second capacitor C2 is formed by the first to eighth metal layers ML1 to ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4 and the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element LE is also formed by the first to eighth metal layers ML1 to ML8.

[0139] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating film INS1 and be connected to the contact terminal CTE exposed in the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and connected to the first vias VA1.

[0140] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may penetrate the second interlayer insulating film INS2 and be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and be connected to the second vias VA2.

[0141] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may penetrate the third interlayer insulating film INS3 and be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and connected to the third vias VA3.

[0142] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may penetrate the fourth interlayer insulating film INS4 and be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and connected to the fourth vias VA4.

[0143] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may penetrate the fifth interlayer insulating film INS5 and be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and connected to the fifth vias VA5.

[0144] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may penetrate the sixth interlayer insulating film INS6 and be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and be connected to the sixth vias VA6.

[0145] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may penetrate the seventh interlayer insulating film INS7 and be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and connected to the seventh vias VA7.

[0146] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may penetrate the eighth interlayer insulating film INS8 and be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and be connected to the eighth vias VA8.

[0147] The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be composed of substantially the same material. The first to eighth metal layers ML1 to ML8 and the first to eighth vias VA1 to VA8 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first to eighth vias VA1 to VA8 may be composed of substantially the same material. The first to eighth interlayer insulating films INS1 to ILD8 may be composed of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0148] Each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be approximately (Angstrom), the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 are each approximately The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 is approximately

[0149] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be approximately Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 may be approximately

[0150] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0151] Each of the ninth vias VA9 may pass through the ninth interlayer insulating film INS9 and be connected to the exposed eighth metal layer ML8. The ninth via VA9 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via VA9 may be approximately

[0152] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and connected to the ninth via VA9. The first reflective electrode RL1 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0153] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective electrode RL2 may be titanium nitride TiN.

[0154] In the first sub-pixel SP1, a step layer STPL may be configured on the second reflective electrode RL2. The step layer STPL may not be configured in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the first light-emitting layer EML1 to the fourth reflective electrode RL4 so as to facilitate reflection of the light of the first color emitted from the first light-emitting layer EML1 of the first sub-pixel SP1. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the step layer STPL can be approximately

[0155] In the first sub-pixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0156] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0157] Each of the fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first to third intermediate layers EML1, EML2, and EML3. The fourth reflective electrode RL4 may include a metal with high reflectivity so as to facilitate reflection of light. The fourth reflective electrode RL4 may be formed of aluminum (Al), a laminated structure of aluminum and titanium (Ti / Al / Ti), a laminated structure of aluminum and ITO (ITO / Al / ITO), an alloy of silver (Ag), palladium (Pd), and copper (Cu), i.e., an APC alloy, and a laminated structure of an APC alloy and ITO (ITO / APC / ITO), but the embodiments of the present specification are not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be approximately 1000 Å.

[0158] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of this specification are not limited to this.

[0159] Each of the tenth vias VA10 may penetrate the tenth interlayer insulating film INS10 and be connected to the exposed ninth metal layer ML9. The tenth via VA10 may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Due to the step layer STPL, the thickness of the tenth via VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via VA10 in the first sub-pixel SP1 may be approximately The thickness of the tenth via VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 is approximately

[0160] The light emitting element layer EML may be disposed on the light emitting element backplane EBP. The light emitting element layer EML may include a light emitting element LE and a pixel defining layer PDL including a first electrode AND, an intermediate layer IL, and a second electrode CAT, respectively.

[0161] The first electrode AND of each of the light emitting elements LE may be disposed on the tenth interlayer insulating film INS10 and connected to the tenth path VA1. The first electrode AND of each of the light emitting elements LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth path VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth paths VA1 to VA9, the first to eighth metal layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride TiN.

[0162] The pixel defining film PDL may be disposed on a portion of the first electrode AND of each light emitting element LE. The pixel defining film PDL may cover the edge of the first electrode AND of each light emitting element LE. The pixel defining film PDL may play a role in dividing the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0163] The first light emitting region EA1 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second light emitting region EA2 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third light emitting region EA3 may be defined as a region where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0164] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 may be disposed on the edge of the first electrode AND of each light emitting element LE, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be made of silicon oxide (SiO x) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0165] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0166] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, IL3 that emit light different from each other. For example, the intermediate layer IL may include a first intermediate layer IL1 that emits light of a first color, a second intermediate layer IL2 that emits light of a third color, and a third intermediate layer IL3 that emits light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0167] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0168] The intermediate layer IL may be formed in the opening OP of the pixel defining film PDL (see Fig.11 ) covers the first electrode AND, and covers the pixel defining film PDL between adjacently arranged sub-pixels SP1, SP2, and SP3, and a part of it can be disconnected.

[0169] In one embodiment, the intermediate layer IL is disconnected between adjacent sub-pixels SP1, SP2, and SP3, thereby preventing leakage current between adjacent sub-pixels SP1, SP2, and SP3, and preventing color crosstalk. The color crosstalk phenomenon refers to, for example, a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is unexpectedly lit during the period in which the blue sub-pixel emits blue light. The color crosstalk phenomenon is caused by leakage current, and may occur when a blue sub-pixel and a red sub-pixel with a large voltage difference in driving the pixels are adjacent. For example, in order to light up the blue sub-pixel, a portion of the driving current is transferred to the red sub-pixel through at least a portion of the conductive layer of the intermediate layer IL during the period in which the light-emitting element LE of the blue sub-pixel supplies the driving current. If leakage current is generated, the red sub-pixel may be unexpectedly lit during the period in which the blue sub-pixel is lit.

[0170] The number of intermediate layers IL1, IL2, IL3 that emit light different from each other is not limited to Fig. 9 As shown. For example, the intermediate layer IL may include two intermediate layers. In this case, it may be that either of the two intermediate layers is substantially the same as the first intermediate layer IL1, and the other includes a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to either intermediate layer and supplying charges to the other intermediate layer may be configured between the two intermediate layers.

[0171] In addition, Fig. 9 The example is that the first to third intermediate layers IL1, IL2, and IL3 are all configured in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the embodiments of this specification are not limited to this. For example, the first intermediate layer IL1 can be configured in the first light-emitting area EA1, and not configured in the second light-emitting area EA2 and the third light-emitting area EA3. In addition, the second intermediate layer IL2 can be configured in the second light-emitting area EA2, and not configured in the first light-emitting area EA1 and the third light-emitting area EA3. In addition, the third intermediate layer IL3 can be configured in the third light-emitting area EA3, and not configured in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the first to third color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0172] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of grooves. The second electrode CAT may be formed of a transparent conductive material TCO (Transparent Conductive Material) such as ITO, IZO, or a semi-transmissive metal material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag) that can transmit light. In the case where the second electrode CAT is formed of a semi-transmissive metal material, the light extraction efficiency in each of the first to third sub-pixels SP1, SP2, SP3 may be improved through a micro cavity.

[0173] The encapsulation layer TFE may be disposed on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic film TFE1, TFE2 to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the light emitting element layer EML from impurities such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0174] The first encapsulating inorganic film TFE1 may be disposed on the second electrode CAT, the encapsulating organic film TFE2 may be disposed on the first encapsulating inorganic film TFE1, and the second encapsulating inorganic film TFE3 may be disposed on the encapsulating organic film TFE2. The first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 may be formed by alternately stacking silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ) and aluminum oxide layer (AlO x ) is formed by a multilayer film of one or more inorganic films. The encapsulating organic film TFE2 may be a monomer. Alternatively, the encapsulating organic film TFE2 may be an organic film of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0175] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0176] The optical layer OPL includes a plurality of color filters CF1, CF2, CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, CF3 may include first to third color filters CF1, CF2, CF3. The first to third color filters CF1, CF2, CF3 may be disposed on the adhesive layer ADL.

[0177] The first color filter CF1 may overlap with the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color, that is, light of the cyan wavelength band. The cyan wavelength band may be approximately 370 nm to 460 nm. Therefore, the first color filter CF1 may transmit light of the first color in the light emitted from the first emission area EA1.

[0178] The second color filter CF2 may overlap with the second light emitting area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of the second color, i.e., light of a green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm. Therefore, the second color filter CF2 may transmit light of the second color in the light emitted from the second light emitting area EA2.

[0179] The third color filter CF3 may overlap with the third light emitting area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, i.e., light of a red wavelength band. The cyan wavelength band may be approximately 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color in the light emitted from the third light emitting area EA3.

[0180] Each of the plurality of lenses LNS may be disposed on each of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be a structure for increasing the ratio of light toward the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0181] The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL has a predetermined refractive index in order to allow light to travel in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film of acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0182] The covering layer CVL can be arranged on the filling layer FIL. The covering layer CVL can be a glass substrate or a polymer resin such as a resin. When the covering layer CVL is a glass substrate, it can be attached to the filling layer FIL. In this case, the filling layer FIL can play a role in bonding the covering layer CVL. When the covering layer CVL is a glass substrate, it can play a role as a packaging substrate. When the covering layer CVL is a polymer resin such as a resin, it can be directly coated on the filling layer FIL.

[0183] The polarizing plate may be disposed on one side of the cover layer CVL. The polarizing plate may be a structure for preventing visibility reduction due to external light reflection. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a quarter-wave plate, but the embodiments of the present specification are not limited thereto. However, in the case where visibility due to external light reflection is sufficiently improved by the first to third color filters CF1, CF2, CF3, the polarizing plate may also be omitted.

[0184] Fig.10 is a flow chart illustrating a method for manufacturing a display device according to an embodiment. Figures 11 to 16 1 is a cross-sectional view showing the process of manufacturing a display device according to an embodiment. Figures 11 to 16 The lower structure of the light emitting element layer EML is omitted. Fig. 9 The description instead of omitting the lower structure of the light emitting element layer EML.

[0185] Below, refer to Figures 10 to 16 , describing a method for manufacturing a display device according to an embodiment. The following description is only a part of the manufacturing process of the display panel 410, and a process for forming the constituent elements described with reference to this document may be additionally performed before or after each step described below. In addition, a manufacturing process for the display panel 410 known in the industry may be additionally performed before or after each step described below.

[0186] Reference Fig.10 In step 1010, a driving element layer SBP may be formed on a substrate SSUB. The substrate SSUB may be a semiconductor substrate SSUB. The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The driving element layer SBP may be a semiconductor backplane SBP including MOSFETs. The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively.

[0187] Reference Fig.10 In step 1020, a wiring layer EBP may be formed on the driving element layer SBP. The wiring layer EBP may be a semiconductor backplane SBP and a light emitting element backplane EBP electrically connected to the light emitting element layer EML. The light emitting element backplane EBP includes first to eighth metal layers ML1 to ML8, reflective metal layers RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element backplane EBP includes an interlayer insulating film INS disposed between the first to sixth metal layers ML1 to ML6. The interlayer insulating film INS includes a plurality of interlayer insulating films INS1 to INS10.

[0188] Reference Fig.10 as well as Fig.11 In step 1030 , a first electrode AND of each of the plurality of sub-pixels SP1 , SP2 , and SP3 and a pixel defining layer PDL that divides the plurality of sub-pixels SP1 , SP2 , and SP3 may be formed on the wiring layer EBP.

[0189] The first electrode AND may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride TiN.

[0190] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 may be disposed on the edge of the first electrode AND of each light emitting element LE, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0191] Reference Fig.10 as well as Fig.12 In step 1040, an intermediate layer IL may be evaporated.

[0192] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0193] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0194] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0195] Reference Fig.10 and Figures 13 to 15 In step 1050, the Joule heating device 1300 may be aligned on the substrate SSUB on which the intermediate layer IL is evaporated, and a portion of the intermediate layer IL corresponding to adjacent sub-pixels SP1, SP2, and SP3 may be removed by using the heating wiring 1330 of the Joule heating device 1300.

[0196] The Joule heating device 1300 may include a board 1310 having a power supply wiring 1311 for applying a heating voltage, an insulating layer 1320 disposed on the board 1310, and a heating wiring 1330 disposed on the insulating layer 1320. The heating wiring 1330 of the Joule heating device 1300 may be electrically connected to the power supply wiring 1311 through a through hole 1312 penetrating the insulating layer 1320. The insulating layer 1320 of the Joule heating device 1300 may be made of silicon oxide (SiO x ) series of inorganic films, but the embodiments of the present specification are not limited thereto. The material of the heat generating wiring 1330 may include at least one of Ti, Mo, W, TiN, and TiW.

[0197] The Joule heating device 1300 is a device for disconnecting a portion of the intermediate layer IL covering the pixel defining film PDL between adjacently arranged sub-pixels SP1, SP2, and SP3. Due to the high temperature of the heating wiring 1330 having the Joule heating device 1300, a portion of the intermediate layer IL can be removed. The heating wiring 1330 is configured to surround each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. Therefore, by the Joule heating device 1300, the removal area of ​​the intermediate layer IL ( Fig.15 1501) can be configured in the form of a periphery surrounding each of the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3.

[0198] The method of using the Joule heating device 1300 to disconnect a portion of the intermediate layer IL can be performed in the following order. First, Fig.13 As shown in FIG. 1 , the Joule heating device 1300 can be aligned on the substrate SSUB. Next, a heating voltage is applied to the power supply wiring 1311 of the Joule heating device 1300, so that the heating wiring 1330 can be heated. Next, as shown in FIG. Fig.14 As shown in FIG. 1 , when the heating wiring 1330 reaches a specified temperature, the heating wiring 1330 is brought into contact with the intermediate layer IL, thereby removing a portion of the intermediate layer IL. Here, the specified temperature may be a temperature greater than or equal to 400° C. Next, as shown in FIG. Fig.15 As shown, if the Joule heating device 1300 is separated from the substrate SSUB, an intermediate layer IL covering the pixel defining layer PDL between adjacently arranged sub-pixels SP1 , SP2 , and SP3 and having a portion thereof disconnected may be formed.

[0199] According to an embodiment, when the intermediate layer IL is disconnected by the Joule heating device 1300, a portion of the surface of the pixel defining film PDL directly contacting the Joule heating device 1300 or adjacently arranged within a specified distance from the Joule heating device 1300 may be patterned by the Joule heating device 1300. For example, a portion of the surface of the pixel defining film PDL may be patterned in a form corresponding to the shape of the heat generating wiring 1330 having the Joule heating device 1300.

[0200] In this document, the heating voltage may be named as “Joule heating voltage”, “heating voltage” or “driving voltage” or the like.

[0201] On the other hand, the method of using the Joule heating device 1300 to disconnect a portion of the intermediate layer IL can be performed in the following order. First, Fig.13 As shown, the Joule heating device 1300 can be aligned on the substrate SSUB. Fig.14 As shown, the heating wiring 1330 and the intermediate layer IL can be brought into contact. Next, a heating voltage is applied to the power wiring 1311 of the Joule heating device 1300, thereby heating the heating wiring 1330. The heating wiring 1330 is heated to a temperature specified by the heating voltage, thereby removing a portion of the intermediate layer IL that is in contact with the heating wiring 1330. Here, the specified temperature may be a temperature greater than or equal to 400°C. Next, as Fig.15 As shown, if the Joule heating device 1300 is separated from the substrate SSUB, an intermediate layer IL covering the pixel defining layer PDL between adjacently arranged sub-pixels SP1 , SP2 , and SP3 and having a portion thereof disconnected may be formed.

[0202] Reference Fig.10 as well as Fig.16 In step 1060, a second electrode may be evaporated. The second electrode may cover the intermediate layer IL and be commonly configured in a plurality of sub-pixels SP1, SP2, and SP3. The second electrode CAT may be formed of a transparent conductive material TCO (Transparent Conductive Material) such as ITO and IZO that can transmit light, or a semi-transmissive metal material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the second electrode CAT is formed of a semi-transmissive metal material, the light extraction efficiency in each of the first to third sub-pixels SP1, SP2, and SP3 may be improved through a micro cavity.

[0203] Fig.17is a flow chart illustrating a method for manufacturing a display device according to an embodiment. Figures 18 to 23 1 is a cross-sectional view showing the process of manufacturing a display device according to an embodiment. Figures 18 to 23 The lower structure of the light emitting element layer EML is omitted. Fig. 9 The description instead of omitting the lower structure of the light emitting element layer EML.

[0204] Below, refer to Figures 17 to 23 , describing a method for manufacturing a display device according to an embodiment. The following description is only a part of the manufacturing process of the display panel 410, and a process for forming the constituent elements described with reference to this document may be additionally performed before or after each step described below. In addition, a manufacturing process for the display panel 410 known in the industry may be additionally performed before or after each step described below.

[0205] Reference Fig.17 In step 1710, a driving element layer SBP may be formed on the substrate SSUB. The substrate SSUB may be a semiconductor substrate SSUB. The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The driving element layer SBP may be a semiconductor backplane SBP including MOSFET. The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Step 1710 may be performed with reference to Fig.10 The described step 1010 is substantially the same.

[0206] Reference Fig.17 In step 1720, a wiring layer EBP may be formed on the driving element layer SBP. The wiring layer EBP may include a light emitting element backplane EBP electrically connected to the semiconductor backplane SBP and the light emitting element layer EML. The light emitting element backplane EBP includes first to eighth metal layers ML1 to ML8, reflective metal layers RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating films INS1 to INS10 disposed between the first to sixth metal layers ML1 to ML6. Step 1710 may be the same as in reference Fig.10 The illustrated step 1020 is substantially the same.

[0207] Reference Fig.17 as well as Fig.18 In step 1730, a first electrode AND of each of the plurality of sub-pixels SP1, SP2, SP3 and a pixel defining layer PDL partitioning the plurality of sub-pixels SP1, SP2, SP3 may be formed on the wiring layer EBP.

[0208] The first electrode AND may be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride TiN.

[0209] The pixel defining film PDL may include first to third pixel defining films PDL1, PDL2, and PDL3. The first pixel defining film PDL1 may be disposed on the edge of the first electrode AND of each light emitting element LE, the second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and the third pixel defining film PDL3 may be disposed on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be made of silicon oxide (SiO x ) series of inorganic films are formed, but the embodiments of the present specification are not limited thereto. The thickness of the first pixel defining film PDL1, the thickness of the second pixel defining film PDL2, and the thickness of the third pixel defining film PDL3 may be approximately

[0210] Step 1730 can be compared with reference Fig.10 Step 1030 of the description is substantially the same.

[0211] Reference Fig.17 as well as Fig.19 In step 1740, an intermediate layer IL may be evaporated.

[0212] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0213] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, IL3 emitting different lights. For example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked in sequence.

[0214] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0215] Step 1740 can be combined with reference to Fig.10 Step 1040 of the description is substantially the same.

[0216] Reference Fig.17 and Figure 20 to Figure 22 In step 1750, the imprinting device 2000 is aligned on the substrate SSUB on which the intermediate layer IL is evaporated, and the imprinting component 2030 of the imprinting device 2000 can be used to imprint a portion of the intermediate layer IL corresponding to the adjacent sub-pixels SP1, SP2, and SP3.

[0217] The imprinting device 2000 may include a board 2010, an insulating layer 2020 disposed on the board 2010, and an imprinting member 2030 disposed on the insulating layer 2020. The insulating layer 2020 may be made of silicon oxide (SiO x ) series of inorganic films, but the embodiments of the present specification are not limited thereto. The stamping component 2030 may be composed of a Nano Structure having a precision of several nanometers. The material of the stamping component 2030 may include at least one of Silicon, Glass, Parylene, PI, Ni, Cr, and Invar. The end of the stamping component 2030 may have a pointed cone form, but the utility model is not necessarily limited thereto.

[0218] The imprinting device 2000 is a device for imprinting a portion of the intermediate layer IL that can cover the pixel definition film PDL between adjacently arranged sub-pixels SP1, SP2, and SP3. A portion of the intermediate layer IL can be changed into an imprinting region 2201 due to physical imprinting of the imprinting member 2030. The intermediate layer IL can be imprinted, so that the imprinting region 2201 of the intermediate layer IL formed by physical imprinting disconnects at least one conductive layer included in the intermediate layer IL. Here, the at least one conductive layer included in the intermediate layer IL may include at least one layer of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a P-doped layer.

[0219] The method of using the imprinting device 2000 to imprint a portion of the intermediate layer IL can be performed in the following order. First, Fig. 20As shown, the imprinting device 2000 may be aligned on the substrate SSUB. The imprinting member 2030 of the imprinting device 2000 is configured to surround each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. Fig.21 As shown, a portion of the intermediate layer IL is stamped by using a stamping member 2030, so that a portion of the intermediate layer IL can be changed into a stamping region 2201. The stamping region 2201 of the intermediate layer IL can disconnect at least one conductive layer included in the intermediate layer IL by physical stamping. The stamping region 2201 of the intermediate layer IL can be configured to surround each of the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3. Next, as shown in FIG. Fig. 22 As shown, if the imprinting device 2000 is separated from the substrate SSUB, an intermediate layer IL covering the pixel defining film PDL between adjacent sub-pixels SP1, SP2, and SP3 and having a portion thereof disconnected can be formed. In this document, the imprinting area 2201 can be named as a "pressing area" or "imprinting area" or the like.

[0220] Reference Fig.17 as well as Fig.23 In step 1760, a second electrode may be evaporated. The second electrode may cover the intermediate layer IL and be commonly configured in a plurality of sub-pixels SP1, SP2, and SP3. The second electrode CAT may be formed of a transparent conductive material TCO (Transparent Conductive Material) such as ITO and IZO that can transmit light, or a semi-transmissive metal material (Semi-transmissive Conductive Material) such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In the case where the second electrode CAT is formed of a semi-transmissive metal material, the light extraction efficiency in each of the first to third sub-pixels SP1, SP2, and SP3 may be improved through a micro cavity.

[0221] Step 1760 can be compared with reference Fig.10 Step 1060 of the description is substantially the same.

[0222] The embodiments of the present invention are described above with reference to the attached drawings, but a person with ordinary knowledge in the technical field to which the present invention belongs will understand that the present invention can be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all aspects only, and not restrictive.

Claims

1. A display device, It is characterized in that include: A semiconductor backplane, comprising a semiconductor substrate; A light emitting element backplane, arranged on the semiconductor backplane; as well as The light emitting element layer is arranged on the light emitting element backplane, The light emitting element layer comprises: A pixel defining film is used to divide a plurality of sub-pixels; The first electrode of each sub-pixel is disposed in the opening of the pixel defining film; an intermediate layer covering the first electrode in the opening and covering the pixel defining film between adjacently arranged sub-pixels, wherein a portion of the intermediate layer is disconnected; and a second electrode covering the intermediate layer and being disposed on the plurality of sub-pixels; The intermediate layer includes an embossed region, a portion of which is embossed between the adjacent sub-pixels.

2. The display device according to claim 1, It is characterized in that In the embossed region of the intermediate layer, at least one conductive layer included in the intermediate layer is disconnected.

3. The display device according to claim 2, It is characterized in that The at least one conductive layer includes at least one layer of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a P-doped layer.

4. The display device according to claim 1, It is characterized in that The plurality of sub-pixels include: a first sub-pixel including a first light emitting region; a second sub-pixel including a second light emitting region; and a third sub-pixel including a third light emitting region.

5. The display device according to claim 4, It is characterized in that The embossed area is configured to surround each of the first light emitting area, the second light emitting area, and the third light emitting area.

6. A mobile electronic device, It is characterized in that include: The display panel includes a light emitting element layer disposed on a semiconductor substrate. The display panel comprises: A semiconductor backplane, comprising the semiconductor substrate; A light emitting element backplane, disposed on the semiconductor backplane; and The light emitting element layer is arranged on the light emitting element backplane. The light emitting element layer comprises: A pixel defining film is used to divide a plurality of sub-pixels; The first electrode of each sub-pixel is disposed in the opening of the pixel defining film; an intermediate layer covering the first electrode in the opening and covering the pixel defining film between adjacently arranged sub-pixels, wherein a portion of the intermediate layer is disconnected; and a second electrode covering the intermediate layer and being disposed on the plurality of sub-pixels; The intermediate layer includes an embossed region, a portion of which is embossed between the adjacent sub-pixels.

7. The mobile electronic device according to claim 6, It is characterized in that In the embossed region of the intermediate layer, at least one conductive layer included in the intermediate layer is disconnected.

8. The mobile electronic device according to claim 7, It is characterized in that The at least one conductive layer includes at least one layer of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a P-doped layer.

9. The mobile electronic device according to claim 6, It is characterized in that The plurality of sub-pixels include: a first sub-pixel including a first light emitting region; a second sub-pixel including a second light emitting region; and a third sub-pixel including a third light emitting region.

10. The mobile electronic device according to claim 9, It is characterized in that The embossed area is configured to surround each of the first light emitting area, the second light emitting area, and the third light emitting area.

Images