Display panel

Abstract

The utility model discloses a display panel which comprises a plurality of pixel electrodes, a plurality of scanning lines, a plurality of first data lines, a plurality of second data lines and a plurality of thin film transistors. One of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected with one of the two adjacent pixel electrodes located in the column direction of the display panel. The other one of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected with the other one of the two adjacent pixel electrodes located in the column direction of the display panel, and one of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected with the first data line. The other one of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected with the second data line, and the two adjacent thin film transistors located in the row direction of the display panel are electrically connected with the same scanning line; the first data line overlaps the pixel electrode, and the second data line overlaps the pixel electrode.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] In large-size, high-resolution LCD panels, as the driving load of the LCD panel becomes larger and larger, the requirements for charging time and charging rate of the LCD panel are also getting higher and higher. Figure 1 and Figure 2 In order to improve the charging rate of the LCD panel, the LCD panel adopts the HG2D (Half Gate, Two Data) pixel architecture. In order to improve the display effect of the LCD panel, the LCD panel adopts the variable refresh rate technology (Variable Refresh Rate, VRR) to cooperate with the graphics card for variable frequency display. Due to the low storage capacitance of the LCD panel, the display brightness of the LCD panel decreases within one frame time. When the LCD panel switches back to high-frequency display, the display screen of the LCD panel becomes brighter instantly, so that the display screen has a brightness jump, causing the display screen of the display panel to flicker. Utility Model Content

[0003] An embodiment of the present application provides a display panel to improve the problem of screen flickering occurring on a display screen of the display panel.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including:

[0005] a plurality of pixel electrodes;

[0006] Multiple scan lines;

[0007] a plurality of first data lines;

[0008] a plurality of second data lines, wherein the second data lines are parallel to the first data lines;

[0009] a plurality of thin film transistors, wherein one of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to one of two adjacent pixel electrodes located in a column direction of the display panel, the other of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the other of the two adjacent pixel electrodes located in the column direction of the display panel, one of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the first data line, the other of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the second data line, and the two adjacent thin film transistors located in the row direction of the display panel are electrically connected to the same scan line;

[0010] Wherein, in a top view of the display panel, the first data line overlaps with the pixel electrode, and the second data line overlaps with the pixel electrode.

[0011] Furthermore, in a top view of the display panel, the first data line is located on one side of two adjacent thin film transistors in a row direction of the display panel, and the second data line is located on the other side of two adjacent thin film transistors in the row direction of the display panel.

[0012] Furthermore, the display panel also includes a first drain line and a first common electrode line, one end of the first drain line is electrically connected to the drain of the thin film transistor, the other end of the first drain line is electrically connected to the pixel electrode, and the first drain line extends along the column direction of the display panel, the first common electrode line is located between two adjacent pixel electrodes in the row direction of the display panel, and the first common electrode line extends along the row direction of the display panel; wherein, in a top view of the display panel, a portion of the first drain line overlaps with a portion of the first common electrode line.

[0013] Furthermore, the first drain line includes a first line segment and a second line segment, one end of the first line segment is electrically connected to the drain of the thin film transistor, the other end of the first line segment is electrically connected to one end of the second line segment, the other end of the second line segment is electrically connected to the pixel electrode, and the ratio of the length of the second line segment in the row direction of the display panel to the length of the first line segment in the row direction of the display panel is not less than 2; wherein, in a top view of the display panel, the second line segment overlaps with a portion of the first common electrode line.

[0014] Furthermore, the first common electrode line includes a third line segment and a fourth line segment, the fourth line segment is connected to the third line segment, and the ratio of the length of the third line segment in the column direction of the display panel to the length of the second line segment in the column direction of the display panel is not greater than 0.5; wherein, in a top view of the display panel, the second line segment overlaps with the fourth line segment.

[0015] Furthermore, in the top view of the display panel, the first data line and the second data line are located between two adjacent thin film transistors in the row direction.

[0016] Furthermore, the display panel also includes a second drain line and a second common electrode line, one end of the second drain line is electrically connected to the drain of the thin film transistor, the other end of the second drain line is electrically connected to the pixel electrode, and the second drain line extends along the column direction of the display panel, the second common electrode line is located between two adjacent pixel electrodes in the row direction of the display panel, and the second common electrode line extends along the row direction of the display panel; wherein, in a top view of the display panel, the second drain line overlaps with a portion of the second common electrode line.

[0017] Furthermore, the second drain line includes a fifth line segment and a sixth line segment, one end of the fifth line segment is electrically connected to the drain of the thin film transistor, the other end of the fifth line segment is electrically connected to one end of the sixth line segment, the other end of the sixth line segment is electrically connected to the pixel electrode, and the ratio of the length of the sixth line segment in the row direction of the display panel to the length of the fifth line segment in the row direction of the display panel is not less than 2; wherein, in a top view of the display panel, the sixth line segment overlaps with a portion of the second common electrode line.

[0018] Furthermore, the second common electrode line includes a seventh line segment and an eighth line segment, the eighth line segment is connected to the seventh line segment, and the ratio of the length of the seventh line segment in the column direction of the display panel to the length of the sixth line segment in the column direction of the display panel is not greater than 0.5; wherein, in a top view of the display panel, the sixth line segment overlaps with the eighth line segment.

[0019] Furthermore, the display panel also includes a third common electrode line, which is located between two adjacent pixel electrodes in the column direction of the display panel, and the third common electrode line extends along the column direction of the display panel; wherein, in the top view of the display panel, the fifth line segment overlaps with the third common electrode line.

[0020] Beneficial effects of this application:

[0021] The present application provides a display panel, wherein one of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to one of two adjacent pixel electrodes located in a column direction of the display panel, the other of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to the other of two adjacent pixel electrodes located in a column direction of the display panel, one of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to a first data line, and the other of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to a second data line. , and two adjacent thin film transistors located in the row direction of the display panel are electrically connected to the same scan line; so that two thin film transistors located in the same row and used to control two adjacent rows of pixel electrodes in the column direction of the display panel are electrically connected to the same scan line, thereby reducing the number of scan lines by half. Compared with the traditional solution, without reducing the aperture ratio of the pixel, the area for laying out the common electrode line on the pixel of the display panel can be increased, thereby increasing the facing area of ​​the common electrode line and the drain line or the pixel electrode, and improving the storage capacitance formed between the pixel electrode and the common electrode of the display panel, thereby improving the problem of screen flickering on the display screen of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic diagram of a display panel of a conventional solution;

[0023] Figure 2 yes Figure 1 A schematic diagram of a driving structure of a display panel shown;

[0024] Figure 3 is a schematic diagram of a first structure of a display panel in the present application;

[0025] Figure 4 yes Figure 3 A schematic diagram of position A of the display panel shown;

[0026] Figure 5 is a schematic diagram of a second structure of a display panel in the present application;

[0027] Figure 6 yes Figure 5 A schematic diagram of position B of the display panel shown;

[0028] Figure 7 yes Figure 3 or Figure 5 A schematic diagram of a driving structure of a display panel is shown.

[0029] 100-scan line; 200-first data line; 300-second data line; 400-thin film transistor; 500-first drain line, 510-first line segment, 520-second line segment; 600-first common electrode line, 610-third line segment, 620-fourth line segment; 700-second drain line, 710-fifth line segment, 720-sixth line segment; 800-second common electrode line, 810-seventh line segment, 820-eighth line segment; 900-third common electrode line; 1000-fourth common electrode line.

[0030] 01-pixel electrode; 02-thin film transistor; 03-scanning line; 04-metal line. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The technical solutions described below are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0032] In addition, the terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

[0033] refer to Figure 1 and Figure 2 In order to improve the charging rate of the liquid crystal display panel, the liquid crystal display panel adopts the HG2D (HalfGate, Two Data) pixel architecture. In the traditional display panel adopting the HG2D pixel architecture, a thin film transistor for controlling the operation of the pixel electrode is set between the two pixel electrodes in the column direction of the display panel. The thin film transistor 02 for controlling the two adjacent pixel electrodes 01 in the column direction of the display panel needs to be driven by two scanning lines 03 respectively, and an additional metal line 04 needs to be set to electrically connect the two thin film transistors 02; further, in order to improve the display effect of the liquid crystal display panel, the liquid crystal display panel adopts the variable refresh rate technology (Variable Refresh Rate, VRR) to cooperate with the graphics card for variable frequency display. Due to the low storage capacitance of the liquid crystal display panel, the display brightness of the liquid crystal display panel decreases within one frame time. When the liquid crystal display panel switches back to high-frequency display, the display screen of the liquid crystal display panel becomes brighter instantly, so that the display screen has a brightness jump, causing the display screen of the display panel to have a screen flickering problem.

[0034] It should be noted that the driving mode of the HG2D pixel architecture is a pixel architecture in which one gate line is connected to two rows of pixels, and two data lines are connected to one column of pixels.

[0035] Therefore, an embodiment of the present application provides a display panel, referring to Figure 3 , Figure 5 or Figure 7 The display panel includes a plurality of pixel electrodes, a plurality of scan lines 100 , a plurality of first data lines 200 , a plurality of second data lines 300 , and a plurality of thin film transistors 400 .

[0036] Specifically, the second data line 300 is parallel to the first data line 200; one of the two adjacent thin film transistors 400 located in the row direction of the display panel is electrically connected to one of the two adjacent pixel electrodes located in the column direction of the display panel, the other of the two adjacent thin film transistors 400 located in the row direction of the display panel is electrically connected to the other of the two adjacent pixel electrodes located in the column direction of the display panel, one of the two adjacent thin film transistors 400 located in the row direction of the display panel is electrically connected to the first data line 200, the other of the two adjacent thin film transistors 400 located in the row direction of the display panel is electrically connected to the second data line 300, and the two adjacent thin film transistors 400 located in the row direction of the display panel are electrically connected to the same scan line 100; wherein, in a top view of the display panel, the first data line 200 overlaps with the pixel electrode, and the second data line 300 overlaps with the pixel electrode.

[0037] By setting one of the two adjacent thin film transistors 400 located in the row direction of the display panel to be electrically connected to one of the two adjacent pixel electrodes located in the column direction of the display panel, the other of the two adjacent thin film transistors 400 located in the row direction of the display panel to be electrically connected to the other of the two adjacent pixel electrodes located in the column direction of the display panel, one of the two adjacent thin film transistors 400 located in the row direction of the display panel to be electrically connected to the first data line 200, the other of the two adjacent thin film transistors 400 located in the row direction of the display panel to be electrically connected to the second data line 300, and the adjacent Two thin film transistors 400 are electrically connected to the same scan line 100; so that the two thin film transistors 400 located in the same row and used to control two adjacent rows of pixel electrodes in the column direction of the display panel are electrically connected to the same scan line 100, thereby reducing the number of scan lines 100 by half. Compared with the traditional scheme, without reducing the aperture ratio of the pixel, the area for laying out the common electrode line on the pixel of the display panel can be increased, thereby increasing the facing area of ​​the common electrode line and the drain line or the pixel electrode, improving the storage capacitance formed between the pixel electrode and the common electrode of the display panel, and then improving the problem of screen flickering on the display screen of the display panel.

[0038] It should be noted that the display panel includes a plurality of pixel units, any two pixel units in the same column have the same color, the colors of the pixel units in three columns arranged consecutively in the row direction of the display panel are different from each other, the pixel unit includes a pixel electrode and a thin film transistor 400, the odd-numbered pixel units in a column of the pixel units are electrically connected to a first data line 200, and the even-numbered pixel units in a column of the pixel units are electrically connected to a second data line 300.

[0039] In this embodiment, the first data line 200 is electrically connected to the source of the thin film transistor 400 , and the second data line 300 is electrically connected to the source of the thin film transistor 400 .

[0040] In this embodiment, the scan line 100 is electrically connected to the gate of the thin film transistor 400 .

[0041] In this embodiment, in a top view of the display panel, the first data line 200 is located on one side of two adjacent thin film transistors 400 in the row direction of the display panel, and the second data line 300 is located on the other side of two adjacent thin film transistors 400 in the row direction of the display panel.

[0042] refer to Figure 3 In this embodiment, the display panel further includes a first drain line 500 and a first common electrode line 600, one end of the first drain line 500 is electrically connected to the drain of the thin film transistor 400, the other end of the first drain line 500 is electrically connected to the pixel electrode, and the first drain line 500 extends along the column direction of the display panel, the first common electrode line 600 is located between two adjacent pixel electrodes in the row direction of the display panel, and the first common electrode line 600 extends along the row direction of the display panel; wherein, in the top view of the display panel, a portion of the first drain line 500 overlaps with a portion of the first common electrode line 600. By arranging that a portion of the first drain line 500 overlaps with a portion of the first common electrode line 600, that is, a portion of the first drain line 500 is directly opposite to a portion of the first common electrode line 600, a storage capacitor can be formed between the first drain line 500 and the first common electrode line 600, thereby improving the problem of screen flickering in the display screen of the display panel.

[0043] refer to Figure 3 and Figure 4In the present embodiment, the first drain line 500 includes a first line segment 510 and a second line segment 520, one end of the first line segment 510 is electrically connected to the drain of the thin film transistor 400, the other end of the first line segment 510 is electrically connected to one end of the second line segment 520, the other end of the second line segment 520 is electrically connected to the pixel electrode, and the ratio of the length a of the second line segment 520 in the row direction of the display panel to the length b of the first line segment 510 in the row direction of the display panel is not less than 2; wherein, in a top view of the display panel, the second line segment 520 overlaps with a portion of the first common electrode line 600. By setting the ratio of the length a of the second line segment 520 in the row direction of the display panel to the length b of the first line segment 510 in the row direction of the display panel to be not less than 2, the second line segment 520 overlaps with a portion of the first common electrode line 600. Compared with the traditional scheme, the overlapping area of ​​the second line segment 520 and the first common electrode line 600 is increased, that is, the facing area of ​​the second line segment 520 and the first common electrode line 600 is increased, thereby improving the storage capacitance formed between the first drain line 500 and the first common electrode line 600 of the display panel, thereby improving the problem of screen flickering in the display screen of the display panel.

[0044] Referring to the figure, in this embodiment, the display panel further includes two fourth common electrode lines 1000 , which are connected to two ends of the first common electrode line 600 , wherein the fourth common electrode lines 1000 extend along the column direction of the display panel.

[0045] refer to Figure 3 and Figure 4 In this embodiment, the first common electrode line 600 includes a third line segment 610 and a fourth line segment 620, the fourth line segment 620 is connected to the third line segment 610, and the ratio of the length c of the third line segment 610 in the column direction of the display panel to the length d of the second line segment 520 in the column direction of the display panel is not greater than 0.5; wherein, in the top view of the display panel, the second line segment 520 overlaps with the fourth line segment 620. By setting the ratio of the length c of the third line segment 610 in the column direction of the display panel to the length d of the second line segment 520 in the column direction of the display panel to be not greater than 0.5, the second line segment 520 overlaps with the fourth line segment 620, and compared with the traditional solution, the overlapping area of ​​the second line segment 520 and the first common electrode line 600 is increased, that is, the area directly facing the second line segment 520 and the fourth line segment 620 is increased, thereby increasing the storage capacitor formed between the first drain line 500 and the first common electrode line 600 of the display panel, thereby improving the problem of screen flickering in the display screen of the display panel.

[0046] In this embodiment, the third line segment 610 is divided into two segments, and the fourth line segment 620 is located between the two third line segments 610 .

[0047] In this embodiment, in the top view of the display panel, the first data line 200 and the second data line 300 are located between two adjacent thin film transistors 400 in the row direction.

[0048] refer to Figure 5 In this embodiment, the display panel further includes a second drain line 700 and a second common electrode line 800, one end of the second drain line 700 is electrically connected to the drain of the thin film transistor 400, the other end of the second drain line 700 is electrically connected to the pixel electrode, and the second drain line 700 extends along the column direction of the display panel, the second common electrode line 800 is located between two adjacent pixel electrodes in the row direction of the display panel, and the second common electrode line 800 extends along the row direction of the display panel; wherein, in the top view of the display panel, the second drain line 700 overlaps with a portion of the second common electrode line 800. By arranging that the second drain line 700 overlaps with a portion of the second common electrode line 800, that is, the second drain line 700 and a portion of the second common electrode line 800 are directly opposite, a storage capacitor can be formed between the second drain line 700 and the second common electrode line 800, thereby improving the problem of screen flickering in the display screen of the display panel.

[0049] refer to Figure 5 and Figure 6 In this embodiment, the second drain line 700 includes a fifth line segment 710 and a sixth line segment 720, one end of the fifth line segment 710 is electrically connected to the drain of the thin film transistor 400, the other end of the fifth line segment 710 is electrically connected to one end of the sixth line segment 720, the other end of the sixth line segment 720 is electrically connected to the pixel electrode, and the ratio of the length e of the sixth line segment 720 in the row direction of the display panel to the length f of the fifth line segment 710 in the row direction of the display panel is not less than 2; wherein, in the top view of the display panel, the sixth line segment 720 overlaps with a portion of the second common electrode line 800. By setting the ratio of the length e of the sixth line segment 720 in the row direction of the display panel to the length f of the fifth line segment 710 in the row direction of the display panel to be not less than 2, the sixth line segment 720 overlaps with a portion of the second common electrode line 800. Compared with the traditional scheme, the overlapping area between the sixth line segment 720 and the second common electrode line 800 is increased, that is, the facing area between the sixth line segment 720 and the second common electrode line 800 is increased, thereby improving the storage capacitance formed between the second drain line 700 of the display panel and the second common electrode, thereby improving the problem of screen flickering in the display screen of the display panel.

[0050] refer to Figure 5 and Figure 6In this embodiment, the second common electrode line 800 includes a seventh line segment 810 and an eighth line segment 820, the eighth line segment 820 is connected to the seventh line segment 810, and the ratio of the length g of the seventh line segment 810 in the column direction of the display panel to the length h of the sixth line segment 720 in the column direction of the display panel is not greater than 0.5; wherein, in the top view of the display panel, the sixth line segment 720 overlaps with the eighth line segment 820. By setting the ratio of the length g of the seventh line segment 810 in the column direction of the display panel to the length h of the sixth line segment 720 in the column direction of the display panel to be not greater than 0.5, the sixth line segment 720 overlaps with the eighth line segment 820, and compared with the traditional solution, the overlapping area of ​​the sixth line segment 720 and the eighth line segment 820 is increased, that is, the area directly facing the sixth line segment 720 and the eighth line segment 820 is increased, thereby increasing the storage capacitor formed between the second drain line 700 of the display panel and the second common electrode line 800, thereby improving the problem of screen flickering in the display screen of the display panel.

[0051] In this embodiment, the eighth line segment 820 is divided into two segments, the seventh line segment 810 is divided into one segment, and the seventh line segment 810 is located between the two eighth line segments 820 .

[0052] refer to Figure 5 In this embodiment, the display panel further includes a third common electrode line 900, which is located between two adjacent pixel electrodes in the column direction of the display panel, and the third common electrode line 900 extends along the column direction of the display panel; wherein, in the top view of the display panel, the fifth line segment 710 overlaps with the third common electrode line 900. By setting the fifth line segment 710 to overlap with the third common electrode line 900, compared with the traditional solution, the overlapping area of ​​the second drain line 700 and the third common electrode line 900 is increased, that is, the facing area of ​​the second drain line 700 and the third common electrode line 900 is increased, thereby increasing the storage capacitor formed between the second drain line 700 and the third common electrode line 900 of the display panel, thereby improving the problem of screen flickering in the display screen of the display panel.

[0053] In this embodiment, two third common electrode lines 900 are provided, one of which is connected to one end of the second common electrode line 800 , and the other is connected to the other end of the second common electrode line 800 .

[0054] The technical solution of this application is specifically as follows:

[0055] The pixel structure of existing large-size, high-resolution LCD panels, such as 8K resolution and 75-inch display panels, often adopts HG2D pixel architecture to meet the charging rate requirements. However, the storage capacitance of LCD panels is low, and the risk of screen flickering is prone to occur when the variable refresh rate technology is applied to LCD panels. The traditional solution uses HG2D (Half Gate, Two Data) pixel architecture display panels such as Figure 1 As shown, the storage capacitor of the pixel of the pixel architecture is composed of two parts: one part is formed between the pixel electrode and the common electrode, and the other part is formed between the drain line and the common electrode. According to the capacitance formula, the storage capacitor is proportional to the area facing the pixel electrode and the common electrode or the area facing the drain line and the common electrode. Therefore, if you want to increase the storage capacitor under the pixel architecture of the traditional solution, you need to sacrifice a certain aperture ratio; its driving architecture is as follows Figure 2 As shown, when driving, two rows of scanning lines are connected to the same signal.

[0056] Therefore, the solution of the present application places the thin-film transistors that respectively control two rows of pixel switches adjacent to each other, thereby reducing the number of scan lines by half. The space of the reduced scan lines is used to layout the common electrode lines. Compared with the traditional solution, the facing area of ​​the common electrode line and the drain line or the pixel electrode is increased. Without sacrificing the pixel aperture ratio, the storage capacitance formed between the pixel electrode and the common electrode of the display panel is improved, thereby improving the problem of screen flickering on the display screen of the display panel.

[0057] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. A display panel, characterized in that: include: a plurality of pixel electrodes; Multiple scan lines; a plurality of first data lines; a plurality of second data lines, wherein the second data lines are parallel to the first data lines; a plurality of thin film transistors, wherein one of two adjacent thin film transistors located in a row direction of the display panel is electrically connected to one of two adjacent pixel electrodes located in a column direction of the display panel, the other of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the other of the two adjacent pixel electrodes located in the column direction of the display panel, one of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the first data line, the other of the two adjacent thin film transistors located in the row direction of the display panel is electrically connected to the second data line, and the two adjacent thin film transistors located in the row direction of the display panel are electrically connected to the same scan line; Wherein, in a top view of the display panel, the first data line overlaps with the pixel electrode, and the second data line overlaps with the pixel electrode.

2. The display panel according to claim 1, characterized in that: In a top view of the display panel, the first data line is located on one side of two adjacent thin film transistors in a row direction of the display panel, and the second data line is located on the other side of two adjacent thin film transistors in the row direction of the display panel.

3. The display panel according to claim 2, characterized in that: The display panel also includes a first drain line and a first common electrode line, one end of the first drain line is electrically connected to the drain of the thin film transistor, the other end of the first drain line is electrically connected to the pixel electrode, and the first drain line extends along the column direction of the display panel, the first common electrode line is located between two adjacent pixel electrodes in the row direction of the display panel, and the first common electrode line extends along the row direction of the display panel; wherein, in a top view of the display panel, a portion of the first drain line overlaps with a portion of the first common electrode line.

4. The display panel according to claim 3, characterized in that: The first drain line includes a first line segment and a second line segment, one end of the first line segment is electrically connected to the drain of the thin film transistor, the other end of the first line segment is electrically connected to one end of the second line segment, the other end of the second line segment is electrically connected to the pixel electrode, and the ratio of the length of the second line segment in the row direction of the display panel to the length of the first line segment in the row direction of the display panel is not less than 2; wherein, in a top view of the display panel, the second line segment overlaps with a portion of the first common electrode line.

5. The display panel according to claim 4, characterized in that: The first common electrode line includes a third line segment and a fourth line segment, the fourth line segment is connected to the third line segment, and the ratio of the length of the third line segment in the column direction of the display panel to the length of the second line segment in the column direction of the display panel is not greater than 0.5; wherein, in a top view of the display panel, the second line segment overlaps with the fourth line segment.

6. The display panel according to claim 1, characterized in that: In a top view of the display panel, the first data line and the second data line are located between two adjacent thin film transistors in the row direction.

7. The display panel according to claim 6, characterized in that: The display panel also includes a second drain line and a second common electrode line, one end of the second drain line is electrically connected to the drain of the thin film transistor, the other end of the second drain line is electrically connected to the pixel electrode, and the second drain line extends along the column direction of the display panel, the second common electrode line is located between two adjacent pixel electrodes in the row direction of the display panel, and the second common electrode line extends along the row direction of the display panel; wherein, in a top view of the display panel, the second drain line overlaps with a portion of the second common electrode line.

8. The display panel according to claim 7, characterized in that: The second drain line includes a fifth line segment and a sixth line segment, one end of the fifth line segment is electrically connected to the drain of the thin film transistor, the other end of the fifth line segment is electrically connected to one end of the sixth line segment, the other end of the sixth line segment is electrically connected to the pixel electrode, and the ratio of the length of the sixth line segment in the row direction of the display panel to the length of the fifth line segment in the row direction of the display panel is not less than 2; wherein, in a top view of the display panel, the sixth line segment overlaps with a portion of the second common electrode line.

9. The display panel according to claim 8, characterized in that: The second common electrode line includes a seventh line segment and an eighth line segment, the eighth line segment is connected to the seventh line segment, and the ratio of the length of the seventh line segment in the column direction of the display panel to the length of the sixth line segment in the column direction of the display panel is not greater than 0.5; wherein, in a top view of the display panel, the sixth line segment overlaps with the eighth line segment.

10. The display panel according to claim 8, characterized in that: The display panel also includes a third common electrode line, which is located between two adjacent pixel electrodes in the column direction of the display panel, and the third common electrode line extends along the column direction of the display panel; wherein, in a top view of the display panel, the fifth line segment overlaps with the third common electrode line.

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