Silicon carbide groove double-gate MOSFET

Abstract

The utility model provides a silicon carbide trench double-gate MOSFET. The lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate; the well region lower side is connected to the drift layer upper side; a source region is arranged on the well region; the gate dielectric layer sequentially penetrates through the well region and the drift layer, the lower side surface of the gate dielectric layer is connected to the upper side surface of the silicon carbide substrate, the side surfaces of the gate dielectric layer are respectively connected to the side surfaces of the well region and the drift layer, and a first gate and a second gate are arranged in the gate dielectric layer; the distance from the left side of the second gate to the right side of the drift layer is n times of the distance from the left side of the first gate to the right side of the well region, and n is 5-10; the source electrode metal layer is connected to the source region; and the upper side surface of the drain metal layer is connected to the lower side surface of the silicon carbide substrate, so that the drift layer resistance of the device can be effectively reduced, and the on-resistance of the device is further reduced.

Description

Technical Field

[0001] The utility model relates to a silicon carbide trench double-gate MOSFET. Background Art

[0002] As a wide bandgap semiconductor, silicon carbide (SiC) material has received increasing attention and research in the design of integrated circuit devices. Power MOSFET made of it has the advantages of high input impedance, good temperature characteristics, strong voltage resistance, excellent frequency characteristics, and fast switching speed. It is widely used in various fields. Reducing the on-resistance of the device and improving the high-frequency performance of the device without affecting other characteristics of the device is an important support for promoting the development of the electrical industry towards high frequency, miniaturization, and high efficiency, and is also the key to my country's realization of the dual carbon goals. Reducing the on-resistance and improving the high-frequency characteristics of the device are the constant pursuit of device design and manufacturing. Therefore, the existing silicon carbide devices still need to further reduce the on-resistance and continue to increase the operating frequency. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a silicon carbide trench dual-gate MOSFET, which can effectively reduce the resistance of the device drift layer and thus reduce the on-resistance of the device.

[0004] The utility model is implemented as follows: a silicon carbide trench dual-gate MOSFET, comprising:

[0005] Silicon carbide substrate,

[0006] a drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate;

[0007] A well region, wherein the lower side of the well region is connected to the upper side of the drift layer; a source region is disposed on the well region;

[0008] A gate dielectric layer, wherein the gate dielectric layer sequentially penetrates the well region and the drift layer, and the lower side of the gate dielectric layer is connected to the upper side of the silicon carbide substrate, and the side of the gate dielectric layer is respectively connected to the side of the well region and the side of the drift layer, and a first gate and a second gate are arranged in the gate dielectric layer; the distance from the left side of the second gate to the right side of the drift layer is n times the distance from the left side of the first gate to the right side of the well region, and n is 5 to 10;

[0009] a source metal layer connected to the source region;

[0010] and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

[0011] The advantages of the utility model are: the utility model is a silicon carbide trench dual-gate MOSFET, which adopts a trench dual-gate MOSFET structure, can effectively reduce the drift layer resistance of the device, and then reduce the on-resistance of the device; and through the design of device parameters, the introduction of the trench dual-gate structure has no effect on the drain-source withstand voltage capability of the device, and only improves the on-resistance; and when the device is turned on, the well region resistance is consistent with the drift region resistance, thereby achieving device impedance consistency and improving high-frequency characteristics; the gate charge of the device is consistent with the existing gate charge, and does not affect the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0013] Figure 1 The utility model is a schematic diagram of a silicon carbide trench dual-gate MOSFET.

[0014] Figure 2 The utility model is a flow chart of a method for manufacturing a silicon carbide trench dual-gate MOSFET.

[0015] Figure 3 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 1 .

[0016] Figure 4 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 2 .

[0017] Figure 5 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 3 .

[0018] Figure 6 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 4 .

[0019] Figure 7 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 5 .

[0020] Figure 8 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 6 .

[0021] Fig. 9 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 7 .

[0022] Fig.10This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 8 .

[0023] Fig.11 This is a cross-sectional view of the process of a silicon carbide trench dual-gate MOSFET of the utility model. Figure 9 . DETAILED DESCRIPTION

[0024] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0026] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0027] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0028] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0029] like Figure 1 As shown, the embodiment of the present application provides a silicon carbide trench dual-gate MOSFET, including:

[0030] Silicon carbide substrate 1,

[0031] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1;

[0032] A well region 3, wherein the lower side of the well region 3 is connected to the upper side of the drift layer 2; a source region 31 is disposed on the well region 3;

[0033] A gate dielectric layer 4, wherein the gate dielectric layer 4 sequentially penetrates the well region 3 and the drift layer 2, and the lower side of the gate dielectric layer 4 is connected to the upper side of the silicon carbide substrate 1, and the side of the gate dielectric layer 4 is respectively connected to the side of the well region 3 and the side of the drift layer 2, and a first gate 41 and a second gate 42 are provided in the gate dielectric layer 4; the distance from the left side of the second gate 42 to the right side of the drift layer 2 is n times the distance from the left side of the first gate 41 to the right side of the well region 3, and n is 5 to 10, and the connection line between the first gate 41 and the second gate 42 is parallel to the connection line between the well region 3 and the drift layer 2, and the length of the second gate 42 is equal to n times the width of the gate dielectric layer 4;

[0034] A source metal layer 5, wherein the source metal layer 5 is connected to the source region 31;

[0035] and a drain metal layer 6 , the upper side of the drain metal layer 6 being connected to the lower side of the silicon carbide substrate 1 .

[0036] The doping concentration of the silicon carbide substrate 1 is set to 2e18cm -3 , is N-type; the doping concentration of drift layer 2 is 1e16 cm -3 , is N-type; the doping concentration of well region 3 is 1e17 cm -3 , is P type; the doping concentration of the source region 31 is 2e18cm -3 , which is N-type. The doping of the silicon carbide substrate 1 is to reduce the contact resistance with the drain metal layer 6. The doping concentration of the drift layer 2 and the structure of the second gate 42 are matched so that the device inversion concentration is close to the substrate doping concentration to achieve resistance consistency. P-type doping is boron doping, and N-type doping is phosphorus doping.

[0037] The length of the second gate 42 is equal to n times the width of the gate dielectric layer 4; that is, the relationship between the bottom width W of the gate dielectric layer 4 and the length L of the second gate 42 from top to bottom can be expressed as, L=nW, so that the well region 3 inverts to form a conductive channel region and the second gate 42 below controls the increase of the impedance of the conductive channel region to maintain consistency.

[0038] A trench dual-gate MOSFET structure is adopted. The first gate 41 realizes the inversion of the well region 3 near the gate area, controls the formation of the conductive channel, and controls the on and off of the device. The second gate 42 increases the electron concentration near the drift layer 3 near the gate dielectric layer, effectively reduces the drift layer resistance of the device, and then reduces the on-resistance of the device.

[0039] like Figures 1 to 11 As shown, the method for manufacturing the above-mentioned silicon carbide trench dual-gate MOSFET includes:

[0040] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 6, and epitaxially growing on the side of the silicon carbide substrate 1 to form a drift layer 2;

[0041] Step 2: depositing a barrier layer a on the drift layer 2, etching the barrier layer a to form a through hole, and etching the drift layer 2 through the through hole to form a gate dielectric etching region b;

[0042] Step 3: performing dry oxygen oxidation on the gate dielectric etched region b to form a gate dielectric layer 4;

[0043] Step 4: removing the barrier layer a, re-forming the barrier layer a, etching to form a through hole, performing metal deposition, and forming a second gate 42;

[0044] Step 5: removing the barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing ion implantation on the drift layer 2 to form a well region 3;

[0045] Step 6: removing the barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing ion implantation on the well region 3 to form a source region 31;

[0046] Step 7: removing the barrier layer a, re-forming the barrier layer a, etching to form a through hole, performing metal deposition, and forming a source metal layer 5;

[0047] Step 8: remove the barrier layer a, redeposit the barrier layer a, etch the barrier layer a to form a through hole, etch the gate dielectric layer 4 and the second gate 42 through the through hole to form a gate region c, perform metal deposition to form a first gate 41, and remove the barrier layer a; the distance d2 from the left side of the second gate 42 to the right side of the drift layer 2 is n times the distance d1 from the left side of the first gate 41 to the right side of the well region 3, and n is 5 to 10, so as to achieve impedance consistency; the connection line between the first gate 41 and the second gate 42 is level with the connection line between the well region 3 and the drift layer 2, ensuring the control of the well region 3 by the first gate 41 and the control of the drift layer 2 by the second gate 42.

[0048] The introduction of the trench dual-gate structure has no effect on the drain-source withstand voltage capability of the device, only an improvement in the on-resistance; since the breakdown field strength of silicon dioxide is 5MV / cm and the breakdown field strength of silicon carbide is 2.5MV / cm, it is necessary to ensure during device design that the distance from the bottom of the second gate 42 to the silicon carbide substrate 1 is greater than or equal to half the thickness of the drift layer, which can ensure the withstand voltage characteristics of the second gate 42 and prevent breakdown.

[0049] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A silicon carbide trench dual-gate MOSFET, It is characterized in that include: Silicon carbide substrate, a drift layer, the lower side of the drift layer being connected to the upper side of the silicon carbide substrate; A well region, wherein the lower side of the well region is connected to the upper side of the drift layer; a source region is disposed on the well region; A gate dielectric layer, wherein the gate dielectric layer sequentially penetrates the well region and the drift layer, and the lower side of the gate dielectric layer is connected to the upper side of the silicon carbide substrate, and the side of the gate dielectric layer is respectively connected to the side of the well region and the side of the drift layer, and a first gate and a second gate are arranged in the gate dielectric layer; the distance from the left side of the second gate to the right side of the drift layer is n times the distance from the left side of the first gate to the right side of the well region, and n is 5 to 10; a source metal layer connected to the source region; and a drain metal layer, wherein the upper side of the drain metal layer is connected to the lower side of the silicon carbide substrate.

2. A silicon carbide trench dual-gate MOSFET as claimed in claim 1, It is characterized in that A connection line between the first gate and the second gate is flush with a connection line between the well region and the drift layer.

3. A silicon carbide trench dual-gate MOSFET as claimed in claim 1, It is characterized in that The length of the second gate is equal to n times the width of the gate dielectric layer.

4. A silicon carbide trench dual-gate MOSFET as claimed in claim 1, It is characterized in that The distance from the bottom of the second gate to the upper side of the silicon carbide substrate is greater than or equal to half the thickness of the drift layer.

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