TOPCon battery

Abstract

The utility model relates to the technical field of solar cells, and discloses a TOPCon cell, comprising a silicon substrate; the P + doping layer is arranged on the front surface of the silicon substrate; the tunneling oxide layer is arranged on the back surface of the silicon substrate; the N + doping layer is arranged on one side, far away from the silicon substrate, of the tunneling oxide layer; the N + + heavily doped layer is arranged in the N + doped layer; the electrode assembly comprises a first electrode and a second electrode, one end of the first electrode is arranged on the side, away from the tunneling oxide layer, of the silicon substrate, and one end of the second electrode is arranged on the N + + heavily doped layer; wherein the N + doped layer is one of an N + doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer; and the N + + heavily doped layer is one of an N + + heavily doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer. The internal contact resistance of the cell is low, and the conversion efficiency of the cell is high.

Description

Technical Field

[0001] The utility model relates to the technical field of solar cells, in particular to a TOPCon cell. Background Art

[0002] Solar cells are devices that directly convert light energy into electrical energy through the photoelectric effect or photochemical effect. Crystalline silicon solar cells that work with the photovoltaic effect are the mainstream. TOPCon cells are a type of photovoltaic crystalline silicon cell, which is a tunneling oxide layer passivation contact solar cell based on the principle of selective carriers. The current TOPCon cells do not use the N++ heavily doped structure, so the contact resistance inside the cell is relatively high, and there is a need to further reduce it. Utility Model Content

[0003] The utility model aims to provide a TOPCon battery, which has low contact resistance inside the battery and high conversion efficiency.

[0004] In order to achieve the above object, the utility model provides a TOPCon battery, comprising:

[0005] Silicon substrate;

[0006] A P+ doped layer, disposed on the front side of the silicon substrate;

[0007] A tunneling oxide layer, disposed on the back side of the silicon substrate;

[0008] An N+ doped layer is disposed on a side of the tunnel oxide layer away from the silicon substrate;

[0009] An N++ heavily doped layer, disposed in the N+ doped layer; and

[0010] An electrode assembly, comprising a first electrode and a second electrode, wherein one end of the first electrode is disposed on a side of the silicon substrate away from the tunneling oxide layer, and one end of the second electrode is disposed on the N++ heavily doped layer;

[0011] The N+ doped layer is one of an N+ doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer; the N++ heavily doped layer is one of an N++ heavily doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer.

[0012] In some embodiments, a first passivation layer and a second passivation layer are further included, wherein the first passivation layer is disposed on a side of the P+ doped layer away from the silicon substrate, and the second passivation layer is disposed on a side of the N+ doped layer away from the tunneling oxide layer.

[0013] In some embodiments, an anti-reflection layer is further included, and the anti-reflection layer is disposed on a side of the first passivation layer away from the P+ doped layer.

[0014] In some embodiments, the N+ doped layer has a thickness of 40-120 nm and a square resistance of 100-200 Ω / □.

[0015] In some embodiments, the silicon substrate is an N-type silicon substrate.

[0016] In some embodiments, the N++ heavily doped layer and the tunneling oxide layer are spaced apart, and a bottom surface of the N++ heavily doped layer is flush with a bottom surface of the N+ doped layer.

[0017] The utility model provides a TOPCon battery, which has the following beneficial effects compared with the prior art:

[0018] The N+ doped layer is arranged on the side of the tunneling oxide layer away from the silicon substrate, the N++ heavily doped layer is arranged in the N+ doped layer, and one end of the second electrode is arranged on the N++ heavily doped layer. By setting the doping concentration of the N++ heavily doped layer to be higher, the contact resistance between the second electrode and the silicon substrate is reduced, thereby improving the conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a TOPCon battery provided in an embodiment of the utility model.

[0020] In the figure: 1. Silicon substrate; 2. P+ doped layer; 3. Tunneling oxide layer; 4. N+ doped layer; 5. N++ heavily doped layer; 6. First electrode; 7. Second electrode; 8. First passivation layer; 9. Second passivation layer; 10. Anti-reflection layer. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0022] It should be understood that, in the description of the present application, the terms "upper", "lower", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated, that is, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In addition, unless otherwise specified, "multiple" means two or more.

[0023] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0024] like Figure 1 As shown, the TOPCon battery provided by the embodiment of the utility model includes a silicon substrate 1, a P+ doped layer 2, a tunneling oxide layer 3, an N+ doped layer 4, an N++ heavily doped layer 5 and an electrode assembly. The P+ doped layer 2 is arranged on the front side of the silicon substrate 1; the tunneling oxide layer 3 is arranged on the back side of the silicon substrate 1; the N+ doped layer 4 is arranged on the side of the tunneling oxide layer 3 away from the silicon substrate 1; the N++ heavily doped layer 5 is arranged in the N+ doped layer 4; the electrode assembly includes a first electrode 6 and a second electrode 7, one end of the first electrode 6 is arranged on the side of the silicon substrate 1 away from the tunneling oxide layer 3, and one end of the second electrode 7 is arranged on the N++ heavily doped layer 5, wherein the N+ doped layer 4 is one of an N+ doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer; the N++ heavily doped layer 5 is one of an N++ heavily doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer. The other end of the first electrode 6 and the other end of the second electrode 7 are connected to external components.

[0025] Based on the above configuration, the N+ doped layer 4 is arranged on the side of the tunneling oxide layer 3 away from the silicon substrate 1, the N++ heavily doped layer 5 is arranged in the N+ doped layer 4, and one end of the second electrode 7 is arranged on the N++ heavily doped layer 5. The internal doping concentration of the arranged N++ heavily doped layer 5 is higher, thereby reducing the contact resistance between the second electrode and the silicon substrate and improving the conversion efficiency of the battery.

[0026] And when the N+ doped layer 4 and the N++ heavily doped layer 5 are made of microcrystalline silicon layer or nanocrystalline silicon layer, the N+ doped layer 4 and the N++ heavily doped layer 5 have a wider band gap, which can reduce the parasitic absorption of the long-wave band on the back side of the battery, increase the passivation effect, and thus improve the short-circuit current; and because the longitudinal conductivity of the microcrystalline silicon layer or nanocrystalline silicon layer is stronger, the contact resistivity on the back side of the battery can be reduced and the fill factor can be improved.

[0027] In one embodiment, the TOPCon battery further includes a first passivation layer 8 and a second passivation layer 9, wherein the first passivation layer 8 is disposed on a side of the P+ doped layer 2 away from the silicon substrate 1, and the second passivation layer 9 is disposed on a side of the N+ doped layer 4 away from the tunneling oxide layer 3. When in use, the first passivation layer 8 and the second passivation layer 9 can protect the silicon substrate 1 from the external environment, thereby improving the efficiency and life of the battery.

[0028] In one embodiment, the TOPCon cell further includes an anti-reflection layer 10, which is disposed on a side of the first passivation layer 8 away from the P+ doped layer 2. When in use, the anti-reflection layer 10 can reduce the reflection of light and absorb light as much as possible, thereby improving the light absorption rate of the cell and improving the efficiency of the cell.

[0029] In one embodiment, the thickness of the N+ doped layer 4 is 40-120 nm, and the square resistance is 100-200 Ω / □. The size and parameters of the N+ doped layer 4 are determined according to actual needs. By increasing the doping concentration of the N+ doped layer 4 and the N++ heavily doped layer 5, the thickness can be set lower, thereby reducing the manufacturing cost.

[0030] In one embodiment, the silicon substrate 1 is an N-type silicon substrate. The N-type silicon substrate has the advantages of high minority carrier lifetime and low light-induced attenuation, and has greater room for efficiency improvement. At the same time, the battery prepared by the N-type silicon substrate has the advantages of good weak light response and low temperature coefficient. Therefore, the N-type silicon substrate has the dual advantages of high power generation and high reliability.

[0031] In one embodiment, the N++ heavily doped layer 5 is spaced apart from the tunnel oxide layer 3, and the bottom surface of the N++ heavily doped layer 5 is flush with the bottom surface of the N+ doped layer 4. This makes the processing of the N++ heavily doped layer simpler, and there is one more selective heavily doping process than the preparation of the N+ doped layer 4.

[0032] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principle of the present invention. These improvements and substitutions should also be regarded as the protection scope of the present invention.

Claims

1. A TOPCon battery, characterized in that: include: Silicon substrate; A P+ doped layer, disposed on the front side of the silicon substrate; A tunneling oxide layer, disposed on the back side of the silicon substrate; An N+ doped layer is disposed on a side of the tunnel oxide layer away from the silicon substrate; An N++ heavily doped layer is disposed in the N+ doped layer; as well as An electrode assembly, comprising a first electrode and a second electrode, wherein one end of the first electrode is disposed on a side of the silicon substrate away from the tunneling oxide layer, and one end of the second electrode is disposed on the N++ heavily doped layer; The N+ doped layer is one of an N+ doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer; the N++ heavily doped layer is one of an N++ heavily doped microcrystalline silicon layer, a nanocrystalline silicon layer and a polycrystalline silicon layer.

2. The TOPCon battery according to claim 1, characterized in that It also includes a first passivation layer and a second passivation layer. The first passivation layer is arranged on a side of the P+ doped layer away from the silicon substrate, and the second passivation layer is arranged on a side of the N+ doped layer away from the tunneling oxide layer.

3. The TOPCon battery according to claim 2, characterized in that It also includes an anti-reflection layer, which is arranged on a side of the first passivation layer away from the P+ doped layer.

4. The TOPCon battery according to claim 1, characterized in that The thickness of the N+ doped layer is 40-120 nm, and the sheet resistance is 100-200Ω / □.

5. The TOPCon battery according to claim 1, characterized in that The silicon substrate is an N-type silicon substrate.

6. The TOPCon battery according to claim 1, characterized in that The N++ heavily doped layer and the tunneling oxide layer are spaced apart, and the bottom surface of the N++ heavily doped layer is flush with the bottom surface of the N+ doped layer.

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