RFFE control interface identification circuit

Abstract

The utility model relates to the technical field of radio frequency control interfaces, and discloses an RFFE control interface identification circuit, which comprises a first current mirror, a second current mirror, a resistor R1 and a resistor R2, in actual use, when the signal input end inputs high and low level signals or is in a suspended state, the two control state output ends can generate three signal states, so that when three control state output ends are provided, nine signal states can be generated in total, and the control state output ends can be connected with the control state output ends. And therefore, the circuit area required for realizing the same function can be reduced, and practical application is facilitated.

Description

Technical Field

[0001] The utility model relates to the technical field of radio frequency control interfaces, and in particular to an RFFE control interface identification circuit. Background Art

[0002] As RF technology continues to develop, the demand for RF front-end devices (such as power amplifiers, active antenna tuners, low noise amplifiers, and antenna switches) continues to increase. Similarly, for equipment manufacturers, it is becoming increasingly difficult to control all RF front-end devices.

[0003] At present, most RF front-end chips use MIPI bus control for control, but some RF front-end chips use GPIO control routing. Figure 1 As shown in the figure, a single RFFE bus can be connected to one master device and a maximum of 15 slave devices ( Figure 1 Only slave device 1 and slave device 2 are used for illustration); in addition, the RFFE bus uses two signal lines, one is a clock signal line (SCLK) controlled by the host, and the other is a unidirectional / bidirectional data line (SDATA); each RFFE slave device coupled to the RFFE bus can be identified by an identification signal such as USID (Unique Slave ID, slave device identifier), PID (PRODUCT ID, product identifier) ​​or MID (MANUFACTURER_ID, manufacturer identifier).

[0004] In actual use, when the USID, PID and MID of two slave devices are the same, the MIPI RFFE master device cannot distinguish between the two slave devices. In order to avoid the above problems, the two control lines SCLK / SDATA are swapped and connected to the chip PIN pin SCLK / SDATA, and then the chip sets different USID values ​​for the chip by identifying different connection methods, so as to achieve the address expansion of two USIDs of the same chip; or by setting one more pin pin USID, and then the existing external device controls the high and low levels of the USID pin to distinguish the two USID values ​​of the same chip, and then the identification circuit inside the chip identifies the high and low levels of the externally controlled USID pin and the floating three situations to distinguish the three USID values ​​of the same chip.

[0005] In the existing identification circuit, such as Figure 2 As shown, taking the switch logic of the general-purpose RF switch SP8T as an example: it can be seen that the V1 / V2 / V3 control states are used to control the switches of the corresponding 8 RF channels respectively, and V1 / V2 / V3 cannot be used to form redundant control states to control enable / disable of the entire chip. Utility Model Content

[0006] In view of the shortcomings of the background technology, the utility model provides an RFFE control interface identification circuit. The technical problem to be solved is that the three control pins of the identification circuit of the existing radio frequency chip can only form eight control devices, and the applicability is poor.

[0007] To solve the above technical problems, in a first aspect, the utility model provides an RFFE control interface identification circuit of a first structure, including a first current mirror, a second current mirror, a resistor R1 and a resistor R2;

[0008] The first current mirror comprises a first main branch, a first slave branch and a second slave branch, wherein the first slave branch and the second slave branch replicate the current flowing through the first main branch in proportion;

[0009] The second current mirror comprises a second main branch, a third slave branch and a fourth slave branch, wherein the third slave branch and the fourth slave branch replicate the current flowing through the second main branch in proportion;

[0010] The output end of the first main branch is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to one end of the resistor R2, which is the signal input end of the identification circuit, and the other end of the resistor R2 is electrically connected to the input end of the second main branch; the output end of the first slave branch is electrically connected to the input end of the third slave branch, which is the first control state output end, and the output end of the second slave branch is electrically connected to the input end of the fourth slave branch, which is the second control state output end.

[0011] In a certain implementation manner of the first aspect, the first master branch includes a PMOS transistor P1, the first slave branch includes a PMOS transistor P2, and the second slave branch includes a PMOS transistor P3;

[0012] The source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2 and the source of the PMOS tube P3 respectively, and is used to access the power supply voltage VDD;

[0013] The drain of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P1, one end of the resistor R1, the gate of the PMOS tube P2 and the gate of the PMOS tube P3, respectively, and is the output end of the first main branch; the drain of the PMOS tube P2 is the output end of the first slave branch, and the drain of the PMOS tube P3 is the output end of the second slave branch.

[0014] In certain implementations of the first aspect, the ratio of the width-to-length ratio of the PMOS tube P2 to the width-to-length ratio of the PMOS tube P1 is 1:1, and the ratio of the width-to-length ratio of the PMOS tube P3 to the width-to-length ratio of the PMOS tube P1 is greater than 4:1.

[0015] In a certain implementation manner of the first aspect, the second master branch includes an NMOS transistor N1, the third slave branch includes an NMOS transistor N2, and the fourth slave branch includes an NMOS transistor N3;

[0016] The drain of the NMOS tube N1 is electrically connected to the gate of the NMOS tube N1, the other end of the resistor R2, the gate of the NMOS tube N2 and the gate of the NMOS tube N3 respectively, and is the input end of the second main branch. The drain of the NMOS tube N2 is the input end of the third slave branch. The drain of the NMOS tube N3 is the input end of the fourth slave branch. The source of the NMOS tube N1, the source of the NMOS tube N2 and the source of the NMOS tube N3 are all grounded.

[0017] In certain implementations of the first aspect, the ratio of the width-to-length ratio of the NMOS tube N2 to the width-to-length ratio of the NMOS tube N1 is greater than 4:1, and the ratio of the width-to-length ratio of the NMOS tube N3 to the width-to-length ratio of the NMOS tube N1 is 1:1.

[0018] In a certain implementation of the first aspect, the other end of the resistor R1 is also electrically connected to the output end of the first slave branch through the resistor R3, and the other end of the resistor R1 is also electrically connected to the output end of the second slave branch through the resistor R4.

[0019] In a second aspect, the utility model further provides another structure of an RFFE control interface identification circuit, including a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a resistor R1, a resistor R2, a resistor R3, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4;

[0020] The source of the PMOS tube P4 is electrically connected to the source of the PMOS tube P1, the source of the PMOS tube P2, and the source of the PMOS tube P3, respectively, for accessing the power supply voltage VDD, and the PMOS tube P4, the PMOS tube P1, and the PMOS tube P3 form a current mirror structure, the gate of the PMOS tube P4 is electrically connected to the gate of the PMOS tube P1, the gate of the PMOS tube P3, and one end of the resistor R2, respectively, and is a signal input terminal of the identification circuit, the other end of the resistor R2 is electrically connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, one end of the resistor R3, and the gate of the NMOS tube N3, respectively, the other end of the resistor R3 is electrically connected to the drain of the PMOS tube P4, and the NMOS tube N4 and the NMOS tube N3 form a current mirror structure;

[0021] The drain of the PMOS tube P1 is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to the drain of the NMOS tube N1, the gate of the NMOS tube N1, and the gate of the NMOS tube N2 respectively. The NMOS tubes N1 and NMOS tubes N2 form a current mirror structure, and the source of the NMOS tube N1, the source of the NMOS tube N2, the source of the NMOS tube N3, and the source of the NMOS tube N4 are all grounded;

[0022] The drain of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2 , and the drain of the PMOS tube P3 is electrically connected to the drain of the NMOS tube N3 .

[0023] In certain implementations of the second aspect, the ratios of the width to length of the PMOS tube P1 , the width to length of the PMOS tube P2 , the width to length of the PMOS tube P3 , and the width to length of the PMOS tube P4 are 1:1:1:1.

[0024] In some implementation of the second aspect, the ratio of the width to length of the NMOS tube N1, the width to length of the NMOS tube N2, the width to length of the NMOS tube N3, and the width to length of the NMOS tube N4 is 1:1:1:1.

[0025] In a certain implementation of the second aspect, the resistance value of the resistor R2 and the resistor R3 is the same, which is twice that of the resistor R1.

[0026] Compared with the prior art, the utility model has the following beneficial effects: in actual use, when the signal input end of the utility model inputs high or low level signals or is in a suspended state, the two control state output ends can generate three signal states, so when there are three utility models, a total of nine signal states can be generated, and the enable control can be performed from the extra signal states, thereby reducing the circuit area required to realize the same function, which is beneficial to practical application. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the structure of the existing MIPI RFFE system;

[0028] Figure 2 It is a schematic diagram of the switch logic of the existing RF switch SP8T;

[0029] Figure 3 This is a first circuit diagram of the RFFE control interface identification circuit in Embodiment 1;

[0030] Figure 4 This is a second circuit diagram of the RFFE control interface identification circuit in Embodiment 1;

[0031] Figure 5 This is a circuit diagram of the RFFE control interface identification circuit in Example 2. DETAILED DESCRIPTION

[0032] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0033] Embodiment 1

[0034] like Figure 3 As shown, an RFFE control interface identification circuit includes a first current mirror 1, a second current mirror 2, a resistor R1 and a resistor R2;

[0035] The first current mirror 1 comprises a first main branch 10, a first slave branch 11 and a second slave branch 12, wherein the first slave branch 11 and the second slave branch 12 replicate the current flowing through the first main branch 10 in proportion;

[0036] The second current mirror 2 comprises a second main branch 20, a third slave branch 21 and a fourth slave branch 22, wherein the third slave branch 21 and the fourth slave branch 22 replicate the current flowing through the second main branch 20 in proportion;

[0037] The output end of the first main branch 10 is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to one end of the resistor R2, which is the signal input end of the identification circuit, and the other end of the resistor R2 is electrically connected to the input end of the second main branch 20; the output end of the first slave branch 11 is electrically connected to the input end of the third slave branch 21, which is the first control state output end A, and the output end of the second slave branch 12 is electrically connected to the input end of the fourth slave branch 22, which is the second control state output end B.

[0038] Specifically, in this embodiment, the first main branch 10 includes a PMOS transistor P1, the first slave branch 11 includes a PMOS transistor P2, and the second slave branch 12 includes a PMOS transistor P3;

[0039] The source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2 and the source of the PMOS tube P3 respectively, and is used to access the power supply voltage VDD;

[0040] The drain of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P1, one end of the resistor R1, the gate of the PMOS tube P2 and the gate of the PMOS tube P3, respectively, and is the output end of the first main branch 10; the drain of the PMOS tube P2 is the output end of the first slave branch 11, and the drain of the PMOS tube P3 is the output end of the second slave branch 12.

[0041] In this embodiment, the ratio of the width-to-length ratio of the PMOS tube P2 to the width-to-length ratio of the PMOS tube P1 is 1:1, and the ratio of the width-to-length ratio of the PMOS tube P3 to the width-to-length ratio of the PMOS tube P1 is greater than 4:1. In actual use, the current replication ratio of the first slave branch 11 and the second slave branch 12 can be adjusted by adjusting the ratio of the width-to-length ratio of the PMOS tube P2 to the width-to-length ratio of the PMOS tube P1 and by adjusting the ratio of the width-to-length ratio of the PMOS tube P3 to the width-to-length ratio of the PMOS tube P1.

[0042] Specifically, in this embodiment, the second main branch 20 includes an NMOS transistor N1, the third slave branch 21 includes an NMOS transistor N2, and the fourth slave branch 22 includes an NMOS transistor N3;

[0043] The drain of the NMOS tube N1 is electrically connected to the gate of the NMOS tube N1, the other end of the resistor R2, the gate of the NMOS tube N2 and the gate of the NMOS tube N3 respectively, and is the input end of the second main branch 20. The drain of the NMOS tube N2 is the input end of the third slave branch 21. The drain of the NMOS tube N3 is the input end of the fourth slave branch 22. The source of the NMOS tube N1, the source of the NMOS tube N2 and the source of the NMOS tube N3 are all grounded.

[0044] In this embodiment, the ratio of the width-to-length ratio of the NMOS tube N2 to the width-to-length ratio of the NMOS tube N1 is greater than 4:1, and the ratio of the width-to-length ratio of the NMOS tube N3 to the width-to-length ratio of the NMOS tube N1 is 1:1. In actual use, the current replication ratio of the third slave branch 21 and the fourth slave branch 22 can be adjusted by adjusting the ratio of the width-to-length ratio of the NMOS tube N2 to the width-to-length ratio of the NMOS tube N1 and by adjusting the ratio of the width-to-length ratio of the NMOS tube N3 to the width-to-length ratio of the NMOS tube N1.

[0045] for Figure 3 In the circuit shown, when the input signal IN is at a high level, i.e., the same as the power supply voltage VDD, since the PMOS tubes P1, PMOS tubes P2 and PMOS tubes P3 are turned off, the NMOS tubes N1, NMOS tubes N2 and NMOS tubes are turned on. At this time, the signal states of the first control state output terminal A and the second control state output terminal B are at a low level state, i.e., 00;

[0046] When the input signal IN is in a level state, i.e., GND, since the PMOS tubes P1, PMOS tubes P2, and PMOS tubes P3 are turned on, and the NMOS tubes N1, NMOS tubes N2, and NMOS tubes are turned off, at this time, the signal state of the first control state output terminal A and the second control state output terminal B is in a high level state, i.e., 11;

[0047] When there is no input signal IN, that is, the other end of the resistor R1 is left floating, Figure 1All MOS tubes in the circuit are turned on. Since the width-to-length ratio of the MOS tubes is different, the signal states of the first control state output terminal A and the second control state output terminal B are respectively in a low level state and a high level state, that is, 01.

[0048] Through the above principle description, the circuit of the utility model realizes three signal state outputs through one pin. When there are three utility models, nine signal state outputs can be realized. The extra signal states can be enabled and controlled, thereby reducing the circuit area required to realize the same function, which is beneficial to practical application.

[0049] In addition, Figure 4 As shown, this embodiment also provides another RFFE control interface identification circuit. Figure 3 The difference is that in Figure 4 In the embodiment, the other end of the resistor R1 is also electrically connected to the output end of the first slave branch 11 through the resistor R3, and the other end of the resistor R1 is also electrically connected to the output end of the second slave branch 12 through the resistor R4.

[0050] In actual use, if the sum of the threshold voltage of the PMOS tube P1 and the threshold voltage of the NMOS tube N1 is greater than the power supply voltage VDD, the detection bias current will be small, thereby affecting the speed of the detection flipping or even losing the recognition function. By setting the resistors R3 and R4, the detection can be accelerated to realize the recognition function of the input signal IN under the low power supply voltage VDD.

[0051] Embodiment 2

[0052] like Figure 5 As shown, this embodiment also provides another structure of an RFFE control interface identification circuit, including a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a PMOS transistor P4, a resistor R1, a resistor R2, a resistor R3, an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, and an NMOS transistor N4;

[0053] The source of the PMOS tube P4 is electrically connected to the source of the PMOS tube P1, the source of the PMOS tube P2 and the source of the PMOS tube P3, respectively, for accessing the power supply voltage VDD, and the PMOS tube P4, the PMOS tube P1 and the PMOS tube P3 form a current mirror structure, the gate of the PMOS tube P4 is electrically connected to the gate of the PMOS tube P1, the gate of the PMOS tube P3 and one end of the resistor R2, respectively, and is a signal input terminal of the identification circuit, the other end of the resistor R2 is electrically connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, one end of the resistor R3 and the gate of the NMOS tube N3, the other end of the resistor R3 is electrically connected to the drain of the PMOS tube P4, and the NMOS tube N4 and the NMOS tube N3 form a current mirror structure;

[0054] The drain of the PMOS tube P1 is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to the drain of the NMOS tube N1, the gate of the NMOS tube N1, and the gate of the NMOS tube N2 respectively. The NMOS tubes N1 and NMOS tubes N2 form a current mirror structure, and the source of the NMOS tube N1, the source of the NMOS tube N2, the source of the NMOS tube N3, and the source of the NMOS tube N4 are all grounded;

[0055] The drain of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2 , and the drain of the PMOS tube P3 is electrically connected to the drain of the NMOS tube N3 .

[0056] In this embodiment, the ratio of the width to length of the PMOS transistor P1 , the width to length of the PMOS transistor P2 , the width to length of the PMOS transistor P3 , and the width to length of the PMOS transistor P4 is 1:1:1:1.

[0057] In this embodiment, the ratio of the width to length of the NMOS transistor N1 , the width to length of the NMOS transistor N2 , the width to length of the NMOS transistor N3 , and the width to length of the NMOS transistor N4 is 1:1:1:1.

[0058] In this embodiment, the resistance of the resistor R2 and the resistor R3 are the same, which is twice that of the resistor R1.

[0059] for Figure 5 In the circuit shown, when the signal VCTRL is at a high level, the voltage across the resistor R2 increases, the conduction of the PMOS tube P1 weakens, and the conduction of the PMOS tube P2 strengthens. At this time, the output of node A is in a high level state; the multi-resistor R2 passes the current, the NMOS tube N4 conducts more fully, the NMOS tube N3 pulls down more strongly, and the output of node B is low.

[0060] When the signal VCTRL is at a low level, the PMOS tube P1 is more fully turned on than the PMOS tube P2, and the NMOS tube N2 pulls down to make the node A output low; the gate voltage of the PMOS tube P3 is grounded, and it is fully turned on, and the node B is pulled up and output high;

[0061] When there is no signal VCTRL input, that is, the gate of the PMOS tube P4 is suspended from the outside, the gate voltages of the PMOS tubes P2 and P3 are equal, and consistent with the gate voltage of the NMOS tube N4. At this time, the NMOS tubes N4 and N1 are respectively limited by the resistors R3 and R1, resulting in low gate voltages of the NMOS tubes N4 and N1, which means that the VGS turn-on voltages of the PMOS tubes P2, P3 and P4 are large at the same time, and the PMOS tubes P2 and P3 as the mirror pull-up current capabilities of the PMOS tube P4 are stronger than the NMOS tubes N2 and N3 as the mirror pull-down current capabilities of the NMOS tube N4, resulting in nodes A and B being pulled up to a high level state at the same time.

[0062] In summary, there are three Figure 5 In the circuit shown, nine signal states can be generated through three state bits, which can save one state bit compared to the existing circuit, and the extra signal state can be used for enabling control, saving circuit power consumption.

[0063] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A RFFE control interface identification circuit, It is characterized in that It includes a first current mirror, a second current mirror, a resistor R1 and a resistor R2; The first current mirror comprises a first main branch, a first slave branch and a second slave branch, wherein the first slave branch and the second slave branch replicate the current flowing through the first main branch in proportion; The second current mirror comprises a second main branch, a third slave branch and a fourth slave branch, wherein the third slave branch and the fourth slave branch replicate the current flowing through the second main branch in proportion; The output end of the first main branch is electrically connected to one end of the resistor R1, the other end of the resistor R1 is electrically connected to one end of the resistor R2, and is the signal input end of the identification circuit, and the other end of the resistor R2 is electrically connected to the input end of the second main branch; the output end of the first slave branch is electrically connected to the input end of the third slave branch, and is the first control state output end, and the output end of the second slave branch is electrically connected to the input end of the fourth slave branch, and is the second control state output end.

2. The RFFE control interface identification circuit according to claim 1, It is characterized in that The first main branch includes a PMOS transistor P1, the first slave branch includes a PMOS transistor P2, and the second slave branch includes a PMOS transistor P3; The source of the PMOS tube P1 is electrically connected to the source of the PMOS tube P2 and the source of the PMOS tube P3 respectively, and is used to access the power supply voltage VDD; The drain of the PMOS tube P1 is electrically connected to the gate of the PMOS tube P1, one end of the resistor R1, the gate of the PMOS tube P2 and the gate of the PMOS tube P3, respectively, and is the output end of the first main branch; the drain of the PMOS tube P2 is the output end of the first slave branch, and the drain of the PMOS tube P3 is the output end of the second slave branch.

3. The RFFE control interface identification circuit according to claim 2, It is characterized in that The ratio of the width to length ratio of the PMOS tube P2 to that of the PMOS tube P1 is 1:1, and the ratio of the width to length ratio of the PMOS tube P3 to that of the PMOS tube P1 is greater than 4:

1.

4. The RFFE control interface identification circuit according to any one of claims 1 to 3, It is characterized in that The second main branch includes an NMOS transistor N1, the third slave branch includes an NMOS transistor N2, and the fourth slave branch includes an NMOS transistor N3; The drain of the NMOS tube N1 is electrically connected to the gate of the NMOS tube N1, the other end of the resistor R2, the gate of the NMOS tube N2 and the gate of the NMOS tube N3 respectively, and is the input end of the second main branch. The drain of the NMOS tube N2 is the input end of the third slave branch. The drain of the NMOS tube N3 is the input end of the fourth slave branch. The source of the NMOS tube N1, the source of the NMOS tube N2 and the source of the NMOS tube N3 are all grounded.

5. The RFFE control interface identification circuit according to claim 4, It is characterized in that The ratio of the width to length ratio of the NMOS tube N2 to that of the NMOS tube N1 is greater than 4:1, and the ratio of the width to length ratio of the NMOS tube N3 to that of the NMOS tube N1 is 1:

1.

6. The RFFE control interface identification circuit according to claim 4, It is characterized in that The other end of the resistor R1 is also electrically connected to the output end of the first slave branch through the resistor R3, and the other end of the resistor R1 is also electrically connected to the output end of the second slave branch through the resistor R4.

7. A RFFE control interface identification circuit, It is characterized in that It includes a PMOS tube P1, a PMOS tube P2, a PMOS tube P3, a PMOS tube P4, a resistor R1, a resistor R2, a resistor R3, an NMOS tube N1, an NMOS tube N2, an NMOS tube N3 and an NMOS tube N4; The source of the PMOS tube P4 is electrically connected to the source of the PMOS tube P1, the source of the PMOS tube P2, and the source of the PMOS tube P3, respectively, for accessing the power supply voltage VDD, and the PMOS tube P4, the PMOS tube P1, and the PMOS tube P3 form a current mirror structure, the gate of the PMOS tube P4 is electrically connected to the gate of the PMOS tube P1, the gate of the PMOS tube P3, and one end of the resistor R2, respectively, and is the signal input end of the identification circuit, the other end of the resistor R2 is electrically connected to the drain of the NMOS tube N4, the gate of the NMOS tube N4, one end of the resistor R3, and the gate of the NMOS tube N3, respectively, the other end of the resistor R3 is electrically connected to the drain of the PMOS tube P4, and the NMOS tube N4 and the NMOS tube N3 form a current mirror structure; The drain of the PMOS tube P1 is electrically connected to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to the drain of the NMOS tube N1, the gate of the NMOS tube N1, and the gate of the NMOS tube N2 respectively. The NMOS tubes N1 and NMOS tubes N2 form a current mirror structure, and the source of the NMOS tube N1, the source of the NMOS tube N2, the source of the NMOS tube N3, and the source of the NMOS tube N4 are all grounded; The drain of the PMOS tube P2 is electrically connected to the drain of the NMOS tube N2 , and the drain of the PMOS tube P3 is electrically connected to the drain of the NMOS tube N3 .

8. The RFFE control interface identification circuit according to claim 7, It is characterized in that The ratio of the width to length of the PMOS tube P1 , the width to length of the PMOS tube P2 , the width to length of the PMOS tube P3 , and the width to length of the PMOS tube P4 is 1:1:1:

1.

9. The RFFE control interface identification circuit according to claim 7, It is characterized in that The ratio of the width to length of the NMOS tube N1 , the width to length of the NMOS tube N2 , the width to length of the NMOS tube N3 , and the width to length of the NMOS tube N4 is 1:1:1:

1.

10. The RFFE control interface identification circuit according to claim 7, It is characterized in that The resistance value of the resistor R2 and the resistor R3 is the same, which is twice that of the resistor R1.

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