Power module, electric driving device and vehicle

Abstract

The utility model relates to the technical field of vehicles, in particular to a power module, an electric driving device and a vehicle. The power module comprises an upper bridge chip group, a lower bridge chip group, an upper bridge metal layer, a lower bridge metal layer, a positive electrode copper bar, a negative electrode copper bar and a phase copper bar; the chips in the upper bridge chip group and the lower bridge chip group comprise IGBT chips, SIC chips and FRD chips, the chips in the upper bridge chip group are connected in parallel, and the chips in the lower bridge chip group are connected in parallel; chips in the upper bridge chip group are welded on an upper bridge metal layer electrically connected with the positive electrode copper bar, and one surface, far away from the upper bridge metal layer, of each chip in the upper bridge chip group is electrically connected with the phase copper bar; and each chip in the lower bridge chip group is welded on the lower bridge metal layer, and one surface, far away from the lower bridge metal layer, of each chip in the lower bridge chip group is electrically connected with the negative electrode copper bar. According to the invention, the total occupied area of the chip in the power module is reduced while the power module is improved to meet the current ever-increasing large current and large power requirements.

Description

Technical Field

[0001] The present disclosure relates to the field of vehicle technology, and in particular to a power module, an electric drive device and a vehicle. Background Art

[0002] With the increasing development of new energy vehicles, power modules are widely used in the field of new energy vehicle technology. At present, power modules have become important components in motor controllers, inverters and new energy charging piles in new energy vehicles. At present, the more mature power module products on the market mainly include IGBT power modules (IGBT chips) or SIC power modules (SIC chips).

[0003] Under high current, the switching loss of IGBT chip is large; the on-state voltage drop of SIC chip is lower, which makes the switching loss of SIC chip smaller, but because the area of ​​SIC chip is smaller than that of IGBT chip, the thermal resistance on SIC chip is large. Therefore, the current power module cannot meet the growing demand for high current and high power. In addition, the IGBT chip in IGBT power module is usually used in parallel with FRD chip to ensure the normal shutdown of IGBT chip, which increases the total occupied area of ​​the chip in IGBT power module. Utility Model Content

[0004] In order to solve the above technical problems, the present disclosure provides a power module, an electric drive device and a vehicle, which can improve the power module to meet the current growing demand for high current and high power, and at the same time help reduce the total occupied area of ​​the chip in the power module.

[0005] In a first aspect, the present disclosure provides a power module, comprising:

[0006] A substrate and an electrical structure located on the substrate, wherein the electrical structure includes an upper bridge chipset, a lower bridge chipset, an upper bridge metal layer, a lower bridge metal layer, a positive copper busbar, a negative copper busbar, and a phase copper busbar;

[0007] The chips in the upper bridge chipset and the lower bridge chipset include IGBT chips, SIC chips and FRD chips, the chips in the upper bridge chipset are connected in parallel, and the chips in the lower bridge chipset are connected in parallel; the chips in the upper bridge chipset are welded on the upper bridge metal layer, the upper bridge metal layer is electrically connected to the positive copper busbar, and the side of each chip in the upper bridge chipset away from the upper bridge metal layer is electrically connected to the phase copper busbar;

[0008] Each chip in the lower bridge chipset is welded on the lower bridge metal layer, and a side of each chip in the lower bridge chipset away from the lower bridge metal layer is electrically connected to the negative copper busbar, and the lower bridge metal layer is also electrically connected to the phase copper busbar.

[0009] In some embodiments, the power module further comprises:

[0010] a first bonding wire and a second bonding wire;

[0011] A side of each chip in the upper bridge chipset away from the upper bridge metal layer is electrically connected to the phase copper busbar through the first bonding wire, and the first bonding wire is also electrically connected to the lower bridge metal layer;

[0012] A surface of each chip in the lower bridge chipset away from the lower bridge metal layer is electrically connected to the negative electrode copper busbar through the second bonding wire.

[0013] In some embodiments, the IGBT chip and the FRD chip in the upper bridge chipset are arranged in a one-to-one correspondence; the IGBT chip and the FRD chip in the lower bridge chipset are arranged in a one-to-one correspondence.

[0014] In some embodiments, the upper bridge chipset includes a first chipset, a second chipset and a third chipset, the first chipset includes an IGBT chip and an FRD chip, the second chipset includes an IGBT chip and an FRD chip, and the third chipset includes two SIC chips;

[0015] The lower bridge chipset includes a fourth chipset, a fifth chipset and a sixth chipset, the fourth chipset includes an IGBT chip and an FRD chip, the fifth chipset includes an IGBT chip and an FRD chip, and the sixth chipset includes two SIC chips.

[0016] In some embodiments, the upper bridge metal layer includes a first area, a second area, and a third area arranged side by side along a first direction, the third area is located in the middle between the first area and the second area, the first chipset is located in the first area, the second chipset is located in the second area, and the third chipset is located in the third area;

[0017] The lower bridge metal layer includes a fourth area, a fifth area and a sixth area arranged side by side along a first direction, the sixth area is located in the middle position between the fourth area and the fifth area, the fourth chipset is located in the fourth area, the fifth chipset is located in the fifth area, and the sixth chipset is located in the sixth area.

[0018] In some embodiments, the first area and the fourth area are located side by side in the second direction, the second area and the fifth area are located side by side in the second direction, and the third area and the sixth area are located side by side in the second direction; the first direction is perpendicular to the second direction.

[0019] In some embodiments, a distance between two SIC chips in the third chipset is greater than the first distance.

[0020] In some embodiments, the distance between two SIC chips in the sixth chipset is greater than the second distance.

[0021] In a second aspect, the present disclosure further provides an electric drive device, comprising the power module as described in the first aspect.

[0022] In a third aspect, the present disclosure further provides a vehicle, comprising the electric drive device as described in the second aspect.

[0023] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0024] The power module provided by the embodiment of the present disclosure includes: a substrate and an electrical structure located on the substrate, the electrical structure includes an upper bridge chipset, a lower bridge chipset, an upper bridge metal layer, a lower bridge metal layer, a positive copper bus, a negative copper bus and a phase copper bus; the chips in the upper bridge chipset and the lower bridge chipset include IGBT chips, SIC chips and FRD chips, the chips in the upper bridge chipset are connected in parallel, and the chips in the lower bridge chipset are connected in parallel; the chips in the upper bridge chipset are welded on the upper bridge metal layer, the upper bridge metal layer is electrically connected to the positive copper bus, and the side of the chips in the upper bridge chipset away from the upper bridge metal layer is electrically connected to the phase copper bus; the chips in the lower bridge chipset are welded on the lower bridge metal layer, the side of the chips in the lower bridge chipset away from the lower bridge metal layer is electrically connected to the negative copper bus, and the lower bridge metal layer is also electrically connected to the phase copper bus. Thus, by arranging parallel IGBT chips, SIC chips and FRD chips in the upper bridge chipset, and arranging parallel IGBT chips, SIC chips and FRD chips in the lower bridge chipset. The mixed application of IGBT chips and SIC chips can play the advantages of low loss when turning on and off the SIC chips and low conduction loss of small current when the power module is working normally. At the same time, under high current conditions, the advantages of small conduction loss voltage drop of large current SIC chips can be played, and the use of IGBT chips can bear more current. At the same time, the area of ​​IGBT chips is larger than that of SIC chips, which is conducive to reducing heat resistance and further reducing the temperature of the power module when working with high current, which is conducive to improving the power module's demand for the current growing high current and high power. In addition, while improving the power module's demand for the current growing high current and high power, it is conducive to reducing the total occupied area of ​​the chip in the power module. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0027] Figure 1 A schematic diagram of the structure of a power module provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] The power module provided by the embodiment of the present disclosure is provided by setting parallel IGBT chips, SIC chips and FRD chips in the upper bridge chipset, and setting parallel IGBT chips, SIC chips and FRD chips in the lower bridge chipset. The mixed application of IGBT chips and SIC chips can play the advantages of small losses when turning on and off the SIC chips and low conduction losses of small currents when the power module is working normally. At the same time, under high current conditions, the advantages of small conduction loss voltage drop of large current SIC chips can be played, and the use of IGBT chips can bear more current. At the same time, the area of ​​IGBT chips is relatively large relative to the area of ​​SIC chips, which is conducive to reducing heat resistance and further reducing the temperature of the power module when working with large currents, which is conducive to improving the power module for the current growing demand for large currents and high powers. In addition, while improving the power module for the current growing demand for large currents and high powers, it is conducive to reducing the total occupied area of ​​chips in the power module.

[0031] The power module provided in the embodiments of the present disclosure is exemplarily described below with reference to the accompanying drawings.

[0032] Figure 1 Schematic diagram of a power module provided by an embodiment of the present disclosure. Figure 1As shown, the power module includes: a substrate 10 and an electrical structure located on the substrate 10, the electrical structure includes an upper bridge chipset, a lower bridge chipset, an upper bridge metal layer 16, a lower bridge metal layer 17, a positive copper busbar 14, a negative copper busbar 15 and a phase copper busbar 18; the chips in the upper bridge chipset and the lower bridge chipset include an IGBT chip 11, a SIC chip 13 and an FRD chip 12, the chips in the upper bridge chipset are connected in parallel, and the chips in the lower bridge chipset are connected in parallel; the chips in the upper bridge chipset are welded on the upper bridge metal layer 16, the upper bridge metal layer 16 is electrically connected to the positive copper busbar 14, and the side of the chips in the upper bridge chipset away from the upper bridge metal layer 16, that is, the upper surface, is electrically connected to the phase copper busbar 18; the chips in the lower bridge chipset are welded on the lower bridge metal layer 17, the side of the chips in the lower bridge chipset away from the lower bridge metal layer 17, that is, the upper surface, is electrically connected to the negative copper busbar 15, and the lower bridge metal layer 17 is also electrically connected to the phase copper busbar 18.

[0033] Specifically, the copper layer on the substrate 10 is etched to form Figure 1 The metal regions shown are respectively an upper bridge metal layer 16, a lower bridge metal layer 17, a positive copper busbar 14, a negative copper busbar 15 and a phase copper busbar 18. A plurality of chips are arranged on the upper bridge metal layer 16 to form an upper bridge chip group, and a plurality of chips are arranged on the lower bridge metal layer 17 to form a lower bridge chip group. The upper bridge metal layer 16 is electrically connected to the positive copper busbar 14, and the upper bridge metal layer 16 is electrically connected to the phase copper busbar 18 through the chip arranged on the upper bridge metal layer 16; the lower bridge metal layer 17 is electrically connected to the negative copper busbar 15, and the lower bridge metal layer 17 is electrically connected to the phase copper busbar 18 through the chip arranged on the lower bridge metal layer 17.

[0034] The chips in the upper bridge chipset include an IGBT chip 11, a SIC chip 13 and a FRD chip 12, and the IGBT chip 11, the SIC chip 13 and the FRD chip 12 are arranged in parallel. The IGBT chip 11, the SIC chip 13 and the FRD chip 12 in the upper bridge chipset are all welded on the upper bridge metal layer 16. Specifically, the welding surface (including the collector) of the IGBT chip 11 in the upper bridge chipset is welded on the upper bridge metal layer 16, the welding surface (including the drain) of the SIC chip 13 in the upper bridge chipset is welded on the upper bridge metal layer 16, and the welding surface (including the cathode) of the FRD chip 12 in the upper bridge chipset is welded on the upper bridge metal layer 16. The emitter on the upper surface of the IGBT chip 11 in the upper bridge chipset, the anode on the upper surface of the FRD chip 12, and the source on the upper surface of the SIC chip 13 are all electrically connected to the phase copper bus 18.

[0035] The chips in the lower bridge chipset include an IGBT chip 11, a SIC chip 13 and an FRD chip 12, and the IGBT chip 11, the SIC chip 13 and the FRD chip 12 are arranged in parallel. The IGBT chip 11, the SIC chip 13 and the FRD chip 12 in the lower bridge chipset are all welded on the lower bridge metal layer 17. Specifically, the welding surface (including the collector) of the IGBT chip 11 in the lower bridge chipset is welded on the lower bridge metal layer 17, the welding surface (including the drain) of the SIC chip 13 in the lower bridge chipset is welded on the lower bridge metal layer 17, and the welding surface (including the cathode) of the FRD chip 12 in the lower bridge chipset is welded on the lower bridge metal layer 17. The emitter on the upper surface of the IGBT chip 11 in the bridge chipset, the anode on the upper surface of the FRD chip 12, and the source on the upper surface of the SIC chip 13 are all electrically connected to the negative copper bus 15.

[0036] When the power module is working, the specific working process of the upper bridge chipset is as follows. Specifically, the positive electrode of the power supply flows into the current through the positive copper busbar 14, and the current flows into the upper bridge metal layer 16 electrically connected to the positive copper busbar 14. The current in the upper bridge metal layer 16 flows in from the collector on the lower surface of the IGBT chip 11 and flows out from the emitter on the upper surface of the IGBT chip 11 to the phase copper busbar 18. The current in the upper bridge metal layer 16 flows in from the drain on the lower surface of the SIC chip 13 and flows out from the source on the upper surface of the SIC chip 13 to the phase copper busbar 18, and the current in the upper bridge metal layer 16 flows in from the cathode on the lower surface of the FRD chip 12 and flows out from the anode on the upper surface of the FRD chip 12 to the phase copper busbar 18. As a result, the current in the upper bridge metal layer 16 flows in through the welding surface of each chip in the upper bridge chipset, that is, the lower surface, and then flows out through the side of each chip in the upper bridge chipset that is away from the welding surface, that is, the upper surface. Therefore, when the upper bridge chipset is working, the current flowing into the upper bridge metal layer 16 through the positive copper bus 14 flows in from the lower surface of each chip welded in the upper bridge metal layer 16 in the vertical direction, flows out through the upper surface of each chip to the phase copper bus 18, and then flows out through the phase copper bus 18.

[0037] For example, a first bonding wire 19 may be provided in the power module, and the first bonding wire 19 may be a bonding wire. The upper surface of each chip in the upper bridge chipset is electrically connected to the phase copper bus 18 through the first bonding wire 19, so that the upper surface of each chip in the upper bridge chipset can be electrically connected to the phase copper bus 18 by providing the first bonding wire 19. At the same time, the first bonding wire 19 is provided to be electrically connected to the lower bridge metal layer 17.

[0038] When the power module is working, the specific working process of the lower bridge chipset is as follows. Specifically, the current in the phase copper busbar 18 flows into the lower bridge metal layer 17 through the first bonding wire 19, the current in the lower bridge metal layer 17 flows in from the collector on the lower surface of the IGBT chip 11 and flows out from the emitter on the upper surface of the IGBT chip 11 to the negative copper busbar 15, the current in the upper bridge metal layer 16 flows in from the drain on the lower surface of the SIC chip 13 and flows out from the source on the upper surface of the SIC chip 13 to the negative copper busbar 15, and the current in the upper bridge metal layer 16 flows in from the cathode on the lower surface of the FRD chip 12 and flows out from the anode on the upper surface of the FRD chip 12 to the negative copper busbar 15. Thus, the current flowing into the lower bridge metal layer 17 flows in through the welding surface of each chip in the lower bridge chipset, that is, the lower surface, and then flows out through the side of each chip in the lower bridge chipset away from the welding surface, that is, the upper surface. Therefore, when the lower bridge chipset is working, the current flowing into the lower bridge metal layer 17 through the phase copper bus 18 flows in from the lower surface of each chip welded in the lower bridge metal layer 17 in the vertical direction, flows out from the upper surface of each chip to the negative copper bus 15 electrically connected to each chip, and then flows into the negative electrode of the power supply through the negative copper bus 15.

[0039] For example, a second bonding wire 20 may be provided in the power module, and the second bonding wire 20 may be a bonding wire, and the upper surface of each chip in the lower bridge chipset is electrically connected to the negative copper bus 15 through the second bonding wire 20. Thus, by providing the second bonding wire 20, the upper surface of each chip in the lower bridge chipset can be electrically connected to the negative copper bus 15.

[0040] The beneficial effects of the power module provided by the embodiment of the present disclosure are exemplarily described below with respect to setting the same number of IGBT chips and / or SIC chips, in combination with an IGBT power module or a SIC power module in the prior art.

[0041] For example, the IGBT power module in the prior art has four parallel IGBT chips in the upper bridge chipset and four parallel IGBT chips in the lower bridge chipset, and the upper bridge chipset needs to be equipped with four FRD chips, and the lower bridge chipset needs to be equipped with four FRD chips. For example, the SIC power module in the prior art has four parallel SIC chips in the upper bridge chipset and four parallel SIC chips in the lower bridge chipset.

[0042] Exemplarily, in an embodiment of the present application, an upper bridge chipset may be configured to include two IGBT chips and two SIC chips, and a lower bridge chipset may be configured to include two IGBT chips and two SIC chips. Meanwhile, the upper bridge chipset needs to be equipped with two FRD chips, and the lower bridge chipset needs to be equipped with two FRD chips.

[0043] Therefore, compared with the prior art IGBT power module which respectively sets four IGBT chips in the upper and lower bridge chipsets, the power module provided by the embodiment of the present disclosure respectively sets two IGBT chips and two SIC chips in the upper and lower bridge chipsets. Since the area of ​​the SIC chip is smaller than the area of ​​the IGBT chip, and the number of FRD chips used in the embodiment of the present disclosure is less than the number of FRD chips in the IGBT power module, it is beneficial to reduce the total occupied area of ​​the chip. In addition, since the switching loss of the SIC chip is small, compared with the prior art IGBT power module which respectively sets four IGBT chips in the upper and lower bridge chipsets, the disclosed embodiment respectively sets two IGBT chips and two SIC chips in the upper and lower bridge chipsets, which is beneficial to reduce the switching loss.

[0044] Compared with the SIC power module in the prior art, which respectively sets four SIC chips in the upper and lower bridge chipsets, the power module provided by the disclosed embodiment respectively sets two IGBT chips and two SIC chips in the upper and lower bridge chipsets, which can take advantage of the IGBT chip to bear more current, which is conducive to improving the current capacity, and at the same time, it is conducive to reducing the thermal resistance caused by the small area of ​​the SIC chip. In addition, since the price of the SIC chip is relatively expensive, the power module provided by the disclosed embodiment is conducive to reducing costs compared with the SIC power module in the prior art.

[0045] Therefore, the power module provided by the embodiment of the present disclosure is provided by setting the IGBT chip, SIC chip and FRD chip in parallel in the upper bridge chipset, and setting the IGBT chip, SIC chip and FRD chip in parallel in the upper bridge chipset. The mixed application of the IGBT chip and the SIC chip can play the advantages of small loss and low conduction loss of small current when the SIC chip is turned on and off when the power module is working normally. At the same time, under high current working conditions, the advantages of small conduction loss voltage drop of the large current SIC chip can be played, and the use of the IGBT chip can bear more current. At the same time, the area of ​​the IGBT chip is relatively large relative to the area of ​​the SIC chip, which is conducive to reducing heat resistance, further reducing the temperature of the power module when working with large current, and helping to improve the power module for the current growing demand for large current and high power. In addition, while improving the power module for the current growing demand for large current and high power, it is conducive to reducing the total occupied area of ​​the chip in the power module.

[0046] In some embodiments, Figure 1 The IGBT chip 11 and the FRD chip 12 in the upper bridge chipset are arranged in a one-to-one correspondence, and the IGBT chip 11 and the FRD chip 12 in the lower bridge chipset are arranged in a one-to-one correspondence.

[0047] Specifically, the IGBT chip 11 and the FRD chip 12 are arranged in a one-to-one correspondence to ensure that the IGBT chip 11 is normally turned off. Figure 1 exemplarily shows that the upper bridge chipset is configured to include two IGBT chips 11, and the corresponding upper bridge chipset is configured to include two FRD chips 12. And, Figure 1 exemplarily shows that the lower bridge chipset includes two IGBT chips 11, and the corresponding lower bridge chipset includes two FRD chips 12. The FRD chip 12 is used as a current discharge circuit when the power module is turned off, and is used in conjunction with the IGBT chip 11 to play the role of freewheeling protection of the IGBT chip 11.

[0048] In some embodiments, continue to refer to Figure 1 The upper bridge chipset includes a first chipset 01, a second chipset 02 and a third chipset 03, the first chipset 01 includes an IGBT chip 11 and an FRD chip 12, the second chipset 02 includes an IGBT chip 11 and an FRD chip 12, and the third chipset 03 includes two SIC chips 13; the lower bridge chipset includes a fourth chipset 04, a fifth chipset 05 and a sixth chipset 06, the fourth chipset 04 includes an IGBT chip 11 and an FRD chip 12, the fifth chipset 05 includes an IGBT chip 11 and an FRD chip 12, and the sixth chipset 06 includes two SIC chips 13.

[0049] Specifically, Figure 1 01, the upper bridge chipset includes two IGBT chips 11, two SIC chips 13 and two FRD chips 12. One IGBT chip 11 and one FRD chip 12 in the upper bridge chipset may constitute a first chipset 01, another IGBT chip 11 and another FRD chip 12 may constitute a second chipset 02, and two SIC chips 13 may constitute a third chipset 03.

[0050] Specifically, Figure 1 04, another IGBT chip 11 and another FRD chip 12 may form a fifth chipset 05, and two SIC chips 13 may form a sixth chipset 06.

[0051] It should be noted that the embodiment of the present disclosure does not specifically limit the specific number of IGBT chips 11 and SIC chips 13 in the upper bridge chipset, and does not specifically limit the specific number of IGBT chips 11 and SIC chips 13 in the upper bridge chipset.

[0052] In some embodiments, continue to refer to Figure 1The upper bridge metal layer 16 includes a first region 011 , a second region 012 and a third region 013 arranged side by side along a first direction (shown as an X direction in the figure), and the third region 013 is located in the middle position between the first region 011 and the second region 012 .

[0053] Specifically, in combination with the above, the first chipset 01 is set in the first area 011, the second chipset 02 is set in the second area 012, and the third chipset 03 is set in the third area 013. The third area 013 is located in the middle between the first area 011 and the second area 012.

[0054] Therefore, by placing the two SIC chips 13 in the upper bridge chipset in the middle of the two IGBT chips 11, the two IGBT chips 11 can be located on both sides of the SIC chip 13 to ensure that the two IGBT chips 11 in the upper bridge chipset are kept at a greater distance, which is beneficial to reducing the thermal coupling between the two IGBT chips 11 and further reducing the maximum junction temperature of the IGBT chip 11 under high current conditions.

[0055] In some embodiments, continue to refer to Figure 1 The lower bridge metal layer 17 includes a fourth region 014, a fifth region 015 and a sixth region 016 arranged side by side along a first direction (shown as the X direction in the figure), the fourth region 014 and the fifth region 015 are located on opposite sides of the lower bridge metal layer 17, and the sixth region 016 is located in the middle position between the fourth region 014 and the fifth region 015.

[0056] Specifically, in combination with the above, the fourth chipset 04 is set in the fourth area 014, the fifth chipset 05 is set in the fifth area 015, and the sixth chipset 06 is set in the sixth area 016. The sixth area 016 is located in the middle between the fourth area 014 and the fifth area 015.

[0057] Thus, the two SIC chips 13 in the lower bridge chipset can be placed in the middle of the two IGBT chips 11, and the two IGBT chips 11 can be located on both sides of the SIC chip 13 to ensure that the two IGBT chips 11 in the upper bridge chipset are kept at a greater distance, which is beneficial to reduce the thermal coupling between the two IGBT chips 11 and further reduce the maximum junction temperature of the IGBT chip 11 under high current conditions.

[0058] In some embodiments, continue to refer to Figure 1 , the first area 011 and the fourth area 014 are arranged side by side along the second direction (shown in the Y direction in the figure), the second area 012 and the fifth area 015 are arranged side by side along the second direction (shown in the Y direction in the figure), and the third area 013 and the sixth area 016 are arranged side by side along the second direction (shown in the Y direction in the figure). The first direction is perpendicular to the second direction.

[0059] Specifically, the chips in the first area 011 and the chips in the fourth area 014 are arranged in the same direction, the chips in the second area 012 and the chips in the fifth area 015 are arranged in the same direction, and the chips in the third area 013 and the chips in the sixth area 016 are arranged in the same direction. Setting the positions of the chips in the upper bridge chipset and the lower bridge chipset in this way is conducive to optimizing the layout space and optimizing the layout and routing of the power module.

[0060] In addition, the chips of the same type in the first area 011 and the fourth area 014 are symmetrically arranged along the second direction, and the chips of the same type in the third area 013 and the sixth area 016 are symmetrically arranged along the second direction.

[0061] For example, Figure 1 As shown, an IGBT chip 11 in the first zone 011 and an IGBT chip 11 in the fourth zone 014 are symmetrically arranged, and an FRD chip 12 in the first zone 011 and an FRD chip 12 in the fourth zone 014 are symmetrically arranged; an IGBT chip 11 in the second zone 012 and an IGBT chip 11 in the fifth zone 015 are symmetrically arranged, and an FRD chip 12 in the second zone 012 and an FRD chip 12 in the fifth zone 015 are symmetrically arranged.

[0062] The distance between the two SIC chips 13 in the third chip group 03 is greater than the first distance, and the distance between the two SIC chips 13 in the sixth chip group 06 is greater than the second distance.

[0063] Specifically, the distance between the two SIC chips 13 in the third chipset 03 is set to be greater than the first distance, so that the distance between the two SIC chips 13 in the third chipset 03 is kept as far as possible, which can reduce the thermal coupling between the two SIC chips 13 in the third chipset 03.

[0064] Specifically, the distance between the two SIC chips 13 in the sixth chipset 06 is set to be greater than the second distance, so that the distance between the two SIC chips 13 in the sixth chipset 06 is kept as far as possible, which can reduce the thermal coupling between the two SIC chips 13 in the sixth chipset 06.

[0065] The first distance and the second distance may be equal or unequal, and specific setting data of the first distance and the second distance may be set according to the layout of the power module provided in the embodiment of the present disclosure, which is not limited here.

[0066] It should be noted that the power module provided in the embodiment of the present disclosure mainly relies on the FRD chip 12 and the SIC chip 13 for freewheeling when encountering reverse freewheeling conditions, power generation conditions, and stalled rotor conditions. Among them, the FRD chip 12 and the SIC chip 13 are connected in parallel in the reverse freewheeling condition, which can further reduce the voltage drop in the power generation and freewheeling stages, while improving the current capacity in the stalled rotor.

[0067] On the basis of the above embodiments, the present disclosure further provides an electric drive device, including a power module as described in the above embodiments, and thus has the same or similar beneficial effects, which will not be described in detail herein.

[0068] On the basis of the above embodiments, the present disclosure further provides a vehicle, including the electric drive device as described in the above embodiments, and thus has the same or similar beneficial effects, which will not be described in detail herein.

[0069] In other embodiments, the vehicle may also include a cockpit system, a drive system, and other structural or functional systems or components, which are not elaborated or limited here.

[0070] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0071] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power module, characterized in that: include: A substrate and an electrical structure located on the substrate, wherein the electrical structure includes an upper bridge chipset, a lower bridge chipset, an upper bridge metal layer, a lower bridge metal layer, a positive copper bus, a negative copper bus and a phase copper bus; The chips in the upper bridge chipset and the lower bridge chipset include IGBT chips, SIC chips and FRD chips, the chips in the upper bridge chipset are connected in parallel, and the chips in the lower bridge chipset are connected in parallel; the chips in the upper bridge chipset are welded on the upper bridge metal layer, the upper bridge metal layer is electrically connected to the positive copper busbar, and the side of each chip in the upper bridge chipset away from the upper bridge metal layer is electrically connected to the phase copper busbar; Each chip in the lower bridge chipset is welded on the lower bridge metal layer, and a side of each chip in the lower bridge chipset away from the lower bridge metal layer is electrically connected to the negative copper busbar, and the lower bridge metal layer is also electrically connected to the phase copper busbar.

2. The power module according to claim 1, characterized in that: Also includes: a first bonding wire and a second bonding wire; A side of each chip in the upper bridge chipset away from the upper bridge metal layer is electrically connected to the phase copper busbar through the first bonding wire, and the first bonding wire is also electrically connected to the lower bridge metal layer; A surface of each chip in the lower bridge chipset away from the lower bridge metal layer is electrically connected to the negative electrode copper busbar through the second bonding wire.

3. The power module according to claim 1, characterized in that: The IGBT chip and the FRD chip in the upper bridge chipset are arranged in a one-to-one correspondence; the IGBT chip and the FRD chip in the lower bridge chipset are arranged in a one-to-one correspondence.

4. The power module according to claim 1, characterized in that: The upper bridge chipset includes a first chipset, a second chipset and a third chipset, the first chipset includes an IGBT chip and an FRD chip, the second chipset includes an IGBT chip and an FRD chip, and the third chipset includes two SIC chips; The lower bridge chipset includes a fourth chipset, a fifth chipset and a sixth chipset, the fourth chipset includes an IGBT chip and an FRD chip, the fifth chipset includes an IGBT chip and an FRD chip, and the sixth chipset includes two SIC chips.

5. The power module according to claim 4, characterized in that: The upper bridge metal layer includes a first area, a second area and a third area arranged side by side along a first direction, the third area is located in the middle between the first area and the second area, the first chipset is located in the first area, the second chipset is located in the second area, and the third chipset is located in the third area; The lower bridge metal layer includes a fourth area, a fifth area and a sixth area arranged side by side along a first direction, the sixth area is located in the middle position between the fourth area and the fifth area, the fourth chipset is located in the fourth area, the fifth chipset is located in the fifth area, and the sixth chipset is located in the sixth area.

6. The power module according to claim 5, characterized in that: The first area and the fourth area are located side by side in the second direction, the second area and the fifth area are located side by side in the second direction, and the third area and the sixth area are located side by side in the second direction; the first direction is perpendicular to the second direction.

7. The power module according to claim 5, characterized in that: The distance between the two SIC chips in the third chipset is greater than the first distance.

8. The power module according to claim 5, characterized in that: The distance between the two SIC chips in the sixth chipset is greater than the second distance.

9. An electric drive device, characterized in that: Comprising a power module as described in any one of claims 1 to 8.

10. A vehicle, characterized in that: Comprising the electric drive device as claimed in claim 9.

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