Alternating current detection circuit and alternating current detection system

Abstract

The embodiment of the utility model discloses an alternating current detection circuit and an alternating current detection system. The AC detection circuit comprises an AC acquisition circuit, a negation circuit, an integrating circuit and a latch circuit. The negation circuit is connected with the integrating circuit, and the integrating circuit is used for generating a trigger signal according to the received reversal signal and outputting the trigger signal; the integrating circuit is connected with the latch circuit, and the latch circuit is used for controlling and / or maintaining the state of the output level according to the received trigger signal; the state of controlling and / or maintaining the output level according to the received trigger signal comprises the following steps: when the reversal signal is a high level, the trigger signal is a low level, and the output end of the latch circuit keeps low level output; and when the reversal signal is at a low level, the trigger signal is at a high level, and the output end of the latch circuit keeps high-level output. According to the utility model, by adding a secondary power-on self-locking function, secondary power-on is carried out after power failure, and equipment cannot be started, so that the safety of operators and the equipment is protected.

Description

Technical Field

[0001] The embodiments of the utility model relate to the technical field of alternating current detection, and in particular to an alternating current detection circuit and an alternating current detection system. Background Art

[0002] The AC detection circuit is a common circuit in electronic equipment, and is usually used in power grids, switching power supplies, photovoltaic inverters and other related equipment. During the use of these devices, on the one hand, after the power is disconnected, the residual power needs to be discharged before the operator can proceed to the next step of the equipment. If the operator operates the equipment during the discharge period, it may cause serious consequences such as equipment damage, electrical fires, and even life safety. On the other hand, if the equipment is powered off due to a fault, the operator may cause irreparable losses when the power is turned on again without eliminating the fault. The principle of the alternating current (AC) detection circuit is to input the alternating current (AC) signal into the alternating current (AC) detection circuit to convert direct current (DC), square waves, pulses and other signals. The principle block diagram is shown as follows. Figure 1 shown.

[0003] The AC detection circuit in the prior art can eliminate small noise interference in the circuit through isolation protection processing, and also suppress instantaneous high voltage, thereby improving circuit safety. However, the AC detection circuit lacks protection function. When the equipment has a low voltage power failure, the fault is not eliminated, and the second power-on is easily caused to damage the equipment and harm the operator. Utility Model Content

[0004] The utility model provides an AC detection circuit and an AC detection system, which increase a secondary power-on self-locking function, and perform secondary power-on after a fault power failure, so that the equipment cannot be started, thereby protecting the safety of operators and equipment.

[0005] According to one aspect of the utility model, an AC detection circuit is provided, the AC detection circuit comprising: an AC acquisition circuit, an inversion circuit, an integration circuit and a latch circuit;

[0006] The AC acquisition circuit is connected to the inversion circuit, the AC acquisition circuit is used to modulate the collected AC voltage signal into a square wave signal and output it, and the inversion circuit is used to convert the received square wave signal into an inversion signal and output it;

[0007] The inversion circuit is connected to the integration circuit, and the integration circuit is used to generate and output a trigger signal according to the received inversion signal;

[0008] The integration circuit is connected to the latch circuit, and the latch circuit is used to control and / or maintain the state of the output level according to the received trigger signal;

[0009] The state of controlling and / or maintaining the output level according to the received trigger signal comprises:

[0010] When the inversion signal is at a high level, the trigger signal is at a low level, and the output end of the latch circuit maintains a low level output;

[0011] When the inversion signal is at a low level, the trigger signal is at a high level, and the output end of the latch circuit maintains a high level output.

[0012] Optionally, the AC acquisition circuit includes: a power supply unit, a first current limiting unit, a second current limiting unit, a first pull-up unit and a protection unit;

[0013] The power supply unit is connected between the first end of the first current limiting unit and the first end of the protection unit, the second end of the first current limiting unit is connected to the first end of the second current limiting unit and the first end of the first pull-up unit, the second end of the protection unit is connected to the second end of the second current limiting unit and the inversion circuit, and the second end of the first pull-up unit is connected to the inversion circuit.

[0014] Optionally, the AC acquisition circuit further includes: an isolation unit;

[0015] The first end of the isolation unit is connected to the second end of the first current limiting unit and the first end of the second current limiting unit, the second end of the isolation unit is connected to the second end of the protection unit and the second end of the second current limiting unit, the third end of the isolation unit is connected to the first end of the first pull-up unit, and the fourth end of the isolation unit is connected to the inversion circuit.

[0016] Optionally, the power supply unit includes an AC voltage source, the first current limiting unit includes a first current limiting resistor, the second current limiting unit includes a second current limiting resistor, the first pull-up unit includes a first pull-up resistor, and the protection unit includes an anti-breakdown diode;

[0017] The AC voltage source is connected between the first end of the first current limiting resistor and the first end of the anti-breakdown diode, the second end of the first current limiting resistor is connected to the first end of the second current limiting resistor of the optocoupler and the first end of the first pull-up resistor, the second end of the anti-breakdown diode is connected to the second end of the second current limiting resistor of the optocoupler and the inversion circuit, the second current limiting resistor is connected between the first end of the optocoupler and the second end of the optocoupler, the third end of the optocoupler is connected to the first end of the first pull-up resistor, and the second end of the first pull-up resistor is connected to the inversion circuit.

[0018] Optionally, the isolation unit includes an optocoupler, a first end of the optocoupler connected to the second end of the first current limiting resistor and the first end of the second current limiting resistor, a second end of the optocoupler connected to the second end of the anti-breakdown diode and the second end of the second current limiting resistor, a third end of the optocoupler connected to the first end of the first pull-up resistor, and a fourth end of the optocoupler connected to the inversion circuit.

[0019] Optionally, the inversion circuit includes: a third current limiting unit, a second pull-up unit and a first switch unit;

[0020] A first end of the third current limiting unit is connected to the AC acquisition circuit, a first end of the second pull-up unit is connected to the power supply end, a second end of the third current limiting unit is connected to a first end of the first switch unit, a first end of the second pull-up unit is connected to a second end of the first switch unit, and a third end of the first switch unit is grounded.

[0021] Optionally, the third current limiting unit includes a third current limiting resistor, the second pull-up unit includes a second pull-up resistor, and the first switch unit includes a first transistor;

[0022] The first end of the third current limiting resistor is connected to the AC acquisition circuit, the first end of the second pull-up resistor is connected to the power supply end, the second end of the third current limiting resistor is connected to the first end of the first transistor, the first end of the second pull-up resistor is connected to the second end of the first transistor, and the third end of the first transistor is grounded.

[0023] Optionally, the integration circuit comprises: a fourth current limiting unit, a third pull-up unit, a second switch unit and an integration unit;

[0024] The first end of the fourth current limiting unit is connected to the inversion circuit and the latch circuit, the second end of the fourth current limiting unit is connected to the first end of the second switch unit, the first end of the third pull-up unit is connected to the power supply end, the second end of the third pull-up unit is connected to the second end of the second switch unit, the first end of the integration unit and the latch circuit, and the second end of the integration unit is connected to the third end of the second switch unit and then grounded.

[0025] Optionally, the fourth current limiting unit includes a fourth current limiting resistor, the third pull-up unit includes a third pull-up resistor, the second switch unit includes a second triode, and the integration unit includes an integration capacitor;

[0026] The first end of the fourth current limiting resistor is connected to the inversion circuit and the latch circuit, the second end of the fourth current limiting resistor is connected to the first end of the second transistor, the first end of the third pull-up resistor is connected to the power supply end, the second end of the third pull-up resistor is connected to the second end of the second transistor, the first end of the integration capacitor and the latch circuit, and the second end of the integration capacitor is connected to the third end of the second transistor and then grounded.

[0027] Optionally, the latch circuit includes: a trigger unit, a fifth current limiting unit and a third switch unit;

[0028] The first end of the trigger unit is connected to the integration circuit, the second end of the trigger unit is connected to the first end of the third switch unit, the inversion circuit and the integration circuit, the third end of the trigger unit is connected to the first end of the fifth current limiting unit, the second end of the fifth current limiting unit is connected to the second end of the third switch unit, and the third end of the third switch unit is grounded.

[0029] Optionally, the trigger unit includes a trigger, the fifth current limiting unit includes a fifth current limiting resistor, and the third switch unit includes a third triode;

[0030] The first end of the trigger is connected to the integration circuit, the second end of the trigger is connected to the first end of the third transistor, the inversion circuit and the integration circuit, the third end of the trigger is connected to the first end of the fifth current limiting resistor, the second end of the fifth current limiting resistor is connected to the second end of the third transistor, and the third end of the third transistor is grounded.

[0031] According to another aspect of the utility model, an AC detection system is provided. The AC detection system includes any one of the AC detection circuits described in the above aspect.

[0032] The technical solution of the embodiment of the utility model can realize the monitoring of complex working conditions such as low voltage ride-through fault and flashover of the power grid by accumulating fault signals through the integration circuit, and effectively avoid the false detection of power grid faults. The latch circuit adds a secondary power-on self-locking function. When the reversal signal is high, the integration circuit starts to work and discharges, and the signal at the S end of the latch circuit is low. When the reversal signal R is low, the integration circuit stops working and the output voltage exceeds the flip level of the S end of the latch circuit, the signal at the S end of the latch circuit is set to 1, otherwise it remains at 0; when the signal at the S end of the latch circuit is 1, the reversal signal R at the R end of the latch circuit is 0, and the latch circuit QThe terminal is set to 1, and the internal switch tube is in the on state; at this time, no matter what state the square wave signal T is in, the inversion signal at the R terminal of the latch circuit will remain at a low level, and the output terminal of the latch circuit will maintain a high level signal output, which is a fault signal. If the fault signal is not actively cleared, the output terminal of the latch circuit will output a high level each time it is powered on thereafter; since the fault information is saved, the equipment cannot be started until the fault is cleared, and the equipment will not operate, thereby protecting the safety of the operator and the equipment. The utility model solves the problem of the prior art that the power is lost due to a fault, the fault is not eliminated, and the second power-on is performed, causing damage to the equipment, and prevents such incidents from happening. The utility model adds a secondary power-on self-locking function, and the second power-on is performed after the power is lost due to a fault, and the equipment cannot be started, thereby protecting the safety of the operator and the equipment.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present utility model, nor are they intended to limit the scope of the present utility model. Other features of the present utility model will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 It is a principle block diagram of an AC detection circuit;

[0036] Figure 2 It is a structural schematic diagram of an AC detection circuit provided according to an embodiment of the utility model;

[0037] Figure 3 It is a control block diagram of an AC detection circuit provided according to an embodiment of the utility model;

[0038] Figure 4 It is a circuit principle diagram of an AC detection circuit provided according to an embodiment of the utility model;

[0039] Figure 5 It is a waveform diagram of an AC detection circuit provided according to an embodiment of the utility model;

[0040] Figure 6 It is a circuit principle diagram of another AC detection circuit provided according to an embodiment of the utility model;

[0041] Figure 7 It is a waveform diagram of another AC detection circuit provided according to an embodiment of the utility model;

[0042] Figure 8 It is a circuit principle diagram of another AC detection circuit provided according to an embodiment of the utility model;

[0043] Fig. 9 It is a control block diagram of another AC detection circuit provided according to an embodiment of the utility model;

[0044] Fig.10 This is a waveform diagram of another AC detection circuit provided according to an embodiment of the utility model. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 2 is a structural diagram of an AC detection circuit provided according to an embodiment of the utility model, Figure 3 It is a control block diagram of an AC detection circuit provided according to an embodiment of the utility model. Figure 2 and Figure 3 , the embodiment of the utility model provides an AC detection circuit, the AC detection circuit includes: an AC acquisition circuit 10, an inversion circuit 20, an integration circuit 30 and a latch circuit 40;

[0048] The AC acquisition circuit 10 is connected to the inversion circuit 20. The AC acquisition circuit 10 is used to modulate the collected AC voltage signal U into a square wave signal T and output it. The inversion circuit 20 is used to convert the received square wave signal T into an inversion signal R and output it.

[0049] The inversion circuit 20 is connected to the integration circuit 30, and the integration circuit 30 is used to generate and output a trigger signal S according to the received inversion signal R;

[0050] The integration circuit 30 is connected to the latch circuit 40, and the latch circuit 40 is used to control and / or maintain the state of the output level according to the received trigger signal S;

[0051] The state of controlling and / or maintaining the output level according to the received trigger signal S includes:

[0052] When the inversion signal R is at a high level, the trigger signal S is at a low level, and the output end of the latch circuit 40 maintains a low level output;

[0053] When the inversion signal R is at a low level, the trigger signal S is at a high level, and the output terminal of the latch circuit 40 maintains a high level output.

[0054] Specifically, U is the voltage signal of the AC voltage source collected by the AC acquisition circuit 10, and the voltage signal U is modulated by the AC acquisition circuit 10 to output a square wave signal T. The square wave signal T passes through the inversion circuit 20 to obtain the inversion signal R, and the inversion signal R controls the integration circuit 30 to generate a trigger signal S that triggers the latch circuit 40S end. When the inversion signal R is at a high level, the integration circuit 30 starts to work and discharge, and the signal at the latch circuit 40S end is at a low level. When the inversion signal R is at a low level, the integration circuit 30 stops working. When the output voltage of the integration circuit 30 exceeds the TTL flip level of the S end of the latch circuit 40, the signal at the S end of the latch circuit 40 is set to 1, otherwise it remains at 0. When the signal at the S end of the latch circuit 40 is 1, the inversion signal R at the R end of the latch circuit 40 is 0, and the latch circuit 40 Q The terminal is set to 1, and the internal switch tube is in the on state; at this time, no matter what state the square wave signal T is in, the inversion signal R at the latch circuit 40R terminal is affected by the internal switch tube and will remain at a low level. Q The output signal Q remains high until it is manually cleared.

[0055] In addition, when the above device is powered on for the first time and when the device is running, the latch circuit 40 Q The terminal always outputs a low level. After the device fails and loses power, when it is powered on again, the latch circuit 40 Q The high level output of the terminal is a fault signal. If the fault signal is not actively cleared, each subsequent power-on will cause the latch circuit 40 to Q The two ends will output a high level, save the fault information, and make the equipment unable to start, thereby protecting the safety of operators and equipment.

[0056] The AC detection circuit in the embodiment of the utility model has an isolation protection function. The circuit design is simple, which can improve the efficiency, accuracy and safety of AC detection, simplify the circuit, reduce the detection cost, have low production cost and high detection efficiency. It has a signal self-locking function. When a fault occurs, the circuit fault alarm is triggered; when the fault is not actively cleared, the fault state still exists after the power is turned on again. It has a certain fault tolerance capability. By accumulating the fault signal through the integration circuit, it can realize the monitoring of complex working conditions such as low voltage crossing fault of the power grid and flashover of the power grid, and effectively avoid the false detection of power grid faults.

[0057] The technical solution of the embodiment of the utility model can realize the monitoring of complex working conditions such as low voltage ride-through fault and flashover of the power grid by accumulating fault signals through the integration circuit, and effectively avoid the false detection of power grid faults. The latch circuit adds a secondary power-on self-locking function. When the reversal signal R is high, the integration circuit starts to work and discharge, and the signal at the S end of the latch circuit is low. When the reversal signal R is low, the integration circuit stops working and the output voltage exceeds the flip level of the S end of the latch circuit, the signal at the S end of the latch circuit is set to 1, otherwise it remains at 0; when the signal at the S end of the latch circuit is 1, the reversal signal R at the R end of the latch circuit is 0, and the latch circuit Q The terminal is set to 1, and the internal switch tube is in the on state; at this time, no matter what state the square wave signal T is in, the inversion signal at the R terminal of the latch circuit will remain at a low level, and the signal at the output terminal of the latch circuit will remain at a high level output, which is a fault signal. If the fault signal is not actively cleared, the output terminal of the latch circuit will output a high level each time it is powered on thereafter; since the fault information is saved, the equipment cannot be started until the fault is cleared, and the equipment will not operate, thereby protecting the safety of the operator and the equipment. The utility model solves the problem of the prior art that the power is lost due to a fault, the fault is not eliminated, and the secondary power-on is performed, causing damage to the equipment, and prevents such incidents from happening. The utility model can improve the efficiency, accuracy and safety of AC detection, simplify the circuit, reduce the detection cost, and also increase the secondary power-on self-locking function. After the fault power is lost, the secondary power-on is performed, and the equipment cannot be started, thereby protecting the safety of the operator and the equipment.

[0058] Figure 4 is a circuit schematic diagram of an AC detection circuit provided according to an embodiment of the utility model, referring to Figure 4 Optionally, the AC acquisition circuit 10 includes: a power supply unit 11, a first current limiting unit 12, a second current limiting unit 13, a first pull-up unit 14 and a protection unit 15;

[0059] The power supply unit 11 is connected between the first end of the first current limiting unit 12 and the first end of the protection unit 15, the second end of the first current limiting unit 12 is connected to the first end of the second current limiting unit 13 and the first end of the first pull-up unit 14, the second end of the protection unit 15 is connected to the second end of the second current limiting unit 13 and the inversion circuit 20, and the second end of the first pull-up unit 14 is connected to the inversion circuit 20.

[0060] Continue to refer Figure 4 Optionally, the AC acquisition circuit 10 further includes: an isolation unit 16; a first end of the isolation unit 16 is connected to the second end of the first current limiting unit 12 and the first end of the second current limiting unit 13, a second end of the isolation unit 16 is connected to the second end of the protection unit 15 and the second end of the second current limiting unit 13, a third end of the isolation unit 16 is connected to the first end of the first pull-up unit 14, and a fourth end of the isolation unit 16 is connected to the inversion circuit 20.

[0061] Continue to refer Figure 4 Optionally, the power supply unit 11 includes an alternating current voltage source AC, the first current limiting unit 12 includes a first current limiting resistor R1, the second current limiting unit 13 includes a second current limiting resistor R2, the first pull-up unit 14 includes a first pull-up resistor R3, and the protection unit 15 includes an anti-breakdown diode D1;

[0062] The alternating current voltage source AC is connected between the first end of the first current limiting resistor R1 and the first end of the anti-breakdown diode D1, the second end of the first current limiting resistor R1 is connected to the first end of the second current limiting resistor R2 and the first end of the first pull-up resistor R3, the second end of the anti-breakdown diode D1 is connected to the second end of the second current limiting resistor R2 and the inversion circuit 20, and the second end of the first pull-up resistor R3 is connected to the inversion circuit 20.

[0063] Continue to refer Figure 4 Optionally, the isolation unit 16 includes an optocoupler U1, a first end of the optocoupler U1 is connected to the second end of the first current limiting resistor R1 and the first end of the second current limiting resistor R2, a second end of the optocoupler U1 is connected to the second end of the anti-breakdown diode D1 and the second end of the second current limiting resistor R2, a third end of the optocoupler U1 is connected to the first end of the first pull-up resistor R3, and a fourth end of the optocoupler U1 is connected to the inversion circuit 20.

[0064] Specifically, the optocoupler U1 has an isolation protection function. The AC detection circuit has a simple design, low production cost and high detection efficiency.

[0065] Continue to refer Figure 4 Optionally, the inversion circuit 20 includes: a third current limiting unit 21, a second pull-up unit 22 and a first switch unit 23;

[0066] A first end of the third current limiting unit 21 is connected to the AC acquisition circuit 10, a first end of the second pull-up unit 22 is connected to the power supply end VCC, a second end of the third current limiting unit 21 is connected to a first end of the first switch unit 23, a first end of the second pull-up unit 22 is connected to a second end of the first switch unit 23, and a third end of the first switch unit 23 is grounded.

[0067] Continue to refer Figure 4 Optionally, the third current limiting unit 21 includes a third current limiting resistor R4, the second pull-up unit 22 includes a second pull-up resistor R5, and the first switch unit 23 includes a first transistor Q1;

[0068] A first end of the third current limiting resistor R4 is connected to the AC acquisition circuit 10, a first end of the second pull-up resistor R5 is connected to the power supply end VCC, a second end of the third current limiting resistor R4 is connected to a first end of the first transistor Q1, a first end of the second pull-up resistor R5 is connected to a second end of the first transistor Q1, and a third end of the first transistor Q1 is grounded.

[0069] Continue to refer Figure 4 Optionally, the integration circuit 30 includes: a fourth current limiting unit 31, a third pull-up unit 32, a second switch unit 33 and an integration unit 34;

[0070] The first end of the fourth current limiting unit 31 is connected to the inversion circuit 20 and the latch circuit 40, the second end of the fourth current limiting unit 31 is connected to the first end of the second switch unit 33, the first end of the third pull-up unit 32 is connected to the power supply end VCC, the second end of the third pull-up unit 32 is connected to the second end of the second switch unit 33, the first end of the integration unit 34 and the latch circuit 40, and the second end of the integration unit 34 is connected to the third end of the second switch unit 33 and then grounded.

[0071] Continue to refer Figure 4 Optionally, the fourth current limiting unit 31 includes a fourth current limiting resistor R6, the third pull-up unit 32 includes a third pull-up resistor R7, the second switch unit 33 includes a second transistor Q2, and the integration unit 34 includes an integration capacitor C1;

[0072] A first end of the fourth current limiting resistor R6 is connected to the inversion circuit 20 and the latch circuit 40, a second end of the fourth current limiting resistor R6 is connected to the first end of the second transistor Q2, a first end of the third pull-up resistor R7 is connected to the power supply end VCC, a second end of the third pull-up resistor R7 is connected to the second end of the second transistor Q2, a first end of the integration capacitor C1 and the latch circuit 40, and a second end of the integration capacitor C1 is connected to the third end of the second transistor Q2 and then grounded.

[0073] Continue to refer Figure 4, Optionally, the latch circuit 40 includes: a trigger unit 41, a fifth current limiting unit 42 and a third switch unit 43;

[0074] The first end of the trigger unit 41 is connected to the integration circuit 30, the second end of the trigger unit 41 is connected to the first end of the third switch unit 43, the inversion circuit 20 and the integration circuit 30, the third end of the trigger unit 41 is connected to the first end of the fifth current limiting unit 42, the second end of the fifth current limiting unit 42 is connected to the second end of the third switch unit 43, and the third end of the third switch unit 43 is grounded GND.

[0075] Continue to refer Figure 4 Optionally, the trigger unit 41 includes a trigger U2, the fifth current limiting unit 42 includes a fifth current limiting resistor R8, and the third switch unit 43 includes a third transistor Q3;

[0076] The first end of the trigger U2 is connected to the integration circuit 30, the second end of the trigger U2 is connected to the first end of the third transistor Q3, the inversion circuit 20 and the integration circuit 30, the third end of the trigger U2 is connected to the first end of the fifth current limiting resistor R8, the second end of the fifth current limiting resistor R8 is connected to the second end of the third transistor Q3, and the third end of the third transistor Q3 is grounded GND.

[0077] Specific, combined Figure 3 , U is the voltage signal of the AC voltage source AC collected by the AC acquisition circuit 10, and the voltage signal U is modulated by the AC acquisition circuit 10 to output a square wave signal T. The square wave signal T passes through the inversion circuit 20 to obtain the inversion signal R, and the inversion signal R controls the integration capacitor C1 in the integration circuit 30 to generate a trigger signal S that triggers the S end of the trigger U2 in the latch circuit 40. When the inversion signal R is at a high level, the second transistor Q2 in the integration circuit 30 is turned on, the integration capacitor C1 is discharged, and the signal at the S end of the trigger U2 is at a low level. When the inversion signal R is at a low level, the second transistor Q2 is turned off, and the power supply terminal VCC charges the integration capacitor C1 through the third pull-up resistor R7. When the voltage of the integration capacitor C1 exceeds the TTL flip level of the S end of the trigger U2, the signal at the S end is set to 1, otherwise it remains at 0. When the signal at the S end of the trigger U2 is 1, the inversion signal R at the R end of the trigger U2 is 0, and the output end of the trigger U2 Q Set to 1, the collector and emitter of the third transistor Q3 are turned on; at this time, no matter what state the square wave signal T is in, the inversion signal R at the R end of the trigger U2 will remain at a low level under the influence of the third transistor Q3, and the output end of the trigger U2 Q Remains high until manually cleared.

[0078] Figure 5 is a waveform diagram of an AC detection circuit provided according to an embodiment of the utility model, with reference to Figure 5 and Figure 4 Based on the above logic, draw the waveform diagram as follows Figure 5 As shown, when the device is powered on for the first time, the output of trigger U2 Q Set to 0. In this waveform, t0~t1 and t3~t4 are the time periods when the device is powered on, and the AC voltage source outputs stably; t1~t3 is the time period when the device is powered off, and the device is disconnected from the AC voltage source.

[0079] During the time period t0 to t1, in the time period T1, the voltage of the AC voltage signal U is higher than the threshold voltage Uref, the diode in the optocoupler U1 is turned on, the square wave signal T is at a low level, the first transistor Q1 is turned off, the inversion signal R is at a high level, the second transistor Q2 is turned on, the charge of the integral capacitor C1 is 0, and the S terminal of the trigger U2 is at a low level. Q The terminal outputs 0 and the third transistor Q3 is cut off.

[0080] During the T2 period, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is cut off, the square wave signal T is high, the first transistor Q1 is turned on, the inversion signal R is low, the second transistor Q2 is cut off, the integral capacitor C1 is charged, but it does not reach the TTL voltage at the S terminal of the trigger U2, and the output terminal of the trigger U2 is Q Output 0, the third transistor Q3 is cut off.

[0081] In the time period from t1 to t3, the device is powered off at t1, the diode in the optocoupler U1 is cut off, the square wave signal T is at a high level, the first transistor Q1 is turned on, the inversion signal R at the R end of the trigger U2 is at a low level, the second transistor Q2 is cut off, and the integral capacitor C1 is charged.

[0082] At t2, the voltage across the integrating capacitor C1 reaches the TTL level voltage of the trigger U2, the S terminal of the trigger U2 is high, and the trigger U2 Q The output of the terminal is 1, the third transistor Q3 is turned on, the R terminal of the trigger U2 is grounded, and the inversion signal R of the R terminal of the trigger U2 is set to 0.

[0083] During the time period t3 to t4, at t3, the device is powered on for the second time. During the time period T3, the voltage of the AC voltage signal U is higher than the threshold voltage Uref, the diode in the optocoupler U1 is turned on, the square wave signal T is at a low level, and the first transistor Q1 is turned off. At this time, the trigger U2 Q The output of the third transistor Q3 is 1, the R terminal of the trigger U2 is grounded, the inversion signal R of the R terminal of the trigger U2 is set to 0, the second transistor Q2 is turned off, the S terminal of the trigger U2 is high level, and the trigger U2 Q The output is kept at 1.

[0084] In the T4 time period, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is cut off, the square wave signal T is high level, the first transistor Q1 is turned on, the inversion signal R at the R end of the trigger U2 is low level, the S end of the trigger U2 is a high level signal, and the trigger U2 Q The output is kept at 1.

[0085] Different from the related art, the integration circuit in the embodiment of the utility model solves the problem of misjudgment of AC information caused by voltage low-break fault. The duration of the time period t1-t2 can be controlled by changing the capacitance value of the integration capacitor. If a voltage low-break fault occurs during this time period, after the fault ends, the integration capacitor C1 discharges, and the trigger signal S will not be at a high level, so there will be no circuit misjudgment problem. In addition, when the device is powered on for the first time and when the device is running, the trigger U2 Q The terminal always outputs a low level. After the device fails and loses power, when it is powered on again, the trigger U2 Q The high level output of the terminal is a fault signal. If the fault signal is not actively cleared, the trigger U2 will Q The two ends will output a high level, save the fault information, and make the equipment unable to start, thereby protecting the safety of operators and equipment.

[0086] Figure 6 is a circuit schematic diagram of another AC detection circuit provided according to an embodiment of the utility model. Figure 7 is a waveform diagram of another AC detection circuit provided according to an embodiment of the utility model, referring to Figure 6 and Figure 7 , the circuit diagram is as follows Figure 6 As shown: the signal Out2 is used for the frequency information of the AC power, and in combination with the signal Out1 fault signal, some functional combinations can be realized. In addition, the Int terminal is led out in the latch circuit 40 as a circuit reset signal, and the waveform is shown as follows: Figure 7 As shown:

[0087] t0~t1 is the power-off time period of the device, and t1~t2 is the power-on time period of the device. Q The Int terminal must be grounded after the second power-on until the trigger U2 Q The output of the terminal is low level, the Int terminal is left floating, and the reset action is completed.

[0088] During the time period from t0 to t1, before the second power-on, Int is grounded and the trigger U2 QThe end is grounded, Out1 is at a low level, the third transistor Q3 is turned off, the AC power is cut off, the diode in the optocoupler U1 is turned off, the square wave signal T outputs a high level, the first transistor Q1 is turned on, the inversion signal R at the R end of the trigger U2 is at a low level, the second transistor Q2 is turned off, and the S end of the trigger U2 is at a high level;

[0089] After the machine has eliminated the fault at t1, it is powered on again, Int is grounded, and the trigger U2 Q The end is grounded, Out1 is at a low level, the third transistor Q3 is turned off, and the inversion signal R at the R end of the trigger U2 is not grounded.

[0090] During the time period t1 to t2, during the time period T1, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is turned on, the square wave signal T is at a low level, the first transistor Q1 is turned off, the R terminal of the trigger U2 is a high level signal, the second transistor Q2 is turned on, the S terminal of the trigger U2 is at a low level, and the trigger U2 Q The output of the terminal is 0, that is, Out1 outputs 0.

[0091] In the T2 time period, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is cut off, the square wave signal T outputs a high level, the first transistor Q1 is turned on, the inversion signal R at the R end of the trigger U2 is a low level, the second transistor Q2 is cut off, the integral capacitor C1 is charged, but does not reach the TTL voltage of the trigger U2, and the trigger U2 Q The terminal outputs 0 and the third transistor Q3 is cut off.

[0092] At this point, the circuit has completed reset and only needs to leave Int floating.

[0093] Figure 8 is a circuit schematic diagram of another AC detection circuit provided according to an embodiment of the utility model. Fig. 9 is a control block diagram of another AC detection circuit provided according to an embodiment of the utility model. Fig.10 is a waveform diagram of another AC detection circuit provided according to an embodiment of the utility model, referring to Figure 8 , Fig. 9 and Fig.10 , the derivative circuit of AC detection circuit is as follows Figure 8 As shown, it is composed of an AC acquisition circuit 10, an inverting circuit 20, an integration circuit 30 and a latch circuit 40. On the basis of the original circuit, the integration circuit 30 is moved forward to connect the square wave signal T and the trigger signal S, the inverting circuit 20 is connected to the square wave signal T and the inversion signal R, and finally the latch circuit 40 outputs the signal Q. The control block diagram and waveform diagram of the AC detection circuit are shown in Fig. 9 , Fig.10 shown.

[0094] and Figure 4 The circuit is the same. Before the first power-on, the output of trigger U2 Q Set to 0. In the waveform diagram, t0~t1 and t3~t4 are the time periods when the device is powered on, and the AC voltage source outputs stably; t1~t3 is the time period when the device is powered off, and the device is disconnected from the AC voltage source.

[0095] During the time period t0 to t1, during the time period T1, the voltage of the AC voltage signal U is higher than the threshold voltage Uref, the diode in the optocoupler U1 is turned on, the charge of the integral capacitor C1 is 0, the square wave signal T and the trigger signal S are at a low level, the first transistor Q1 is turned off, the inversion signal R is at a high level, and the trigger U2 is Q The output of the terminal is 0, and the second transistor Q2 is cut off.

[0096] During the T2 period, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is cut off, the integral capacitor C1 is charged, but it does not reach the TTL voltage of the trigger U2, the square wave signal T and the trigger signal S are low level, the first transistor Q1 is cut off, the inversion signal R is high level, and the trigger U2 Q The output of the terminal is 0, and the second transistor Q2 is cut off.

[0097] During the time period from t1 to t3, the device is powered off at t1, the diode in the optocoupler U1 is cut off, the integral capacitor C1 is charged, and the TTL voltage of the trigger U2 is reached at t2. The square wave signal T and the trigger signal S are high level, the first transistor Q1 is turned on, the inversion signal R is low level, and the trigger U2 Q The terminal outputs 1 and the second transistor Q2 is turned on.

[0098] During the time period t3 to t4, the device is powered on for the second time at t3. During the time period T3, the voltage of the AC voltage signal U is higher than the threshold voltage Uref, the diode in the optocoupler U1 is turned on, the square wave signal T and the trigger signal S are at a low level, the first transistor Q1 is turned off, but the output signal Q is set to a high level signal, the second transistor Q2 is turned on, the R terminal of the trigger U2 is grounded, the inversion signal R is set to 0, and the output terminal of the trigger U2 is turned on. Q Keep output 0.

[0099] In the T4 period, the voltage of the AC voltage signal U is lower than the threshold voltage Uref, the diode in the optocoupler U1 is cut off, the integral capacitor C1 is charged, but it does not reach the TTL voltage of the trigger U2, the square wave signal T and the trigger signal S are low level, and the R end of the trigger U2 is always low level because the second transistor Q2 is turned on, then the trigger U2 Q The output is kept at 1.

[0100] An embodiment of the utility model further provides an AC detection system, which includes the AC detection circuit provided by any embodiment of the utility model.

[0101] Since the AC detection system includes the AC detection circuit provided by any embodiment of the utility model, the beneficial effects of the AC detection system and the AC detection circuit are the same, which will not be described in detail here.

[0102] The above specific implementations do not constitute a limitation on the protection scope of the present utility model. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An AC detection circuit, characterized in that: include: AC acquisition circuit, inversion circuit, integration circuit and latch circuit; The AC acquisition circuit is connected to the inversion circuit, the AC acquisition circuit is used to modulate the collected AC voltage signal into a square wave signal and output it, and the inversion circuit is used to convert the received square wave signal into an inversion signal and output it; The inversion circuit is connected to the integration circuit, and the integration circuit is used to generate and output a trigger signal according to the received inversion signal; The integration circuit is connected to the latch circuit, and the latch circuit is used to control and / or maintain the state of the output level according to the received trigger signal; The state of controlling and / or maintaining the output level according to the received trigger signal comprises: When the inversion signal is at a high level, the trigger signal is at a low level, and the output end of the latch circuit maintains a low level output; When the inversion signal is at a low level, the trigger signal is at a high level, and the output end of the latch circuit maintains a high level output.

2. The AC detection circuit according to claim 1, characterized in that: The AC collection circuit includes: a power supply unit, a first current limiting unit, a second current limiting unit, a first pull-up unit and a protection unit; The power supply unit is connected between the first end of the first current limiting unit and the first end of the protection unit, the second end of the first current limiting unit is connected to the first end of the second current limiting unit and the first end of the first pull-up unit, the second end of the protection unit is connected to the second end of the second current limiting unit and the inversion circuit, and the second end of the first pull-up unit is connected to the inversion circuit.

3. The AC detection circuit according to claim 2, characterized in that: The AC acquisition circuit further includes: an isolation unit; The first end of the isolation unit is connected to the second end of the first current limiting unit and the first end of the second current limiting unit, the second end of the isolation unit is connected to the second end of the protection unit and the second end of the second current limiting unit, the third end of the isolation unit is connected to the first end of the first pull-up unit, and the fourth end of the isolation unit is connected to the inversion circuit.

4. The AC detection circuit according to claim 3, characterized in that: The power supply unit includes an AC voltage source, the first current limiting unit includes a first current limiting resistor, the second current limiting unit includes a second current limiting resistor, the first pull-up unit includes a first pull-up resistor, and the protection unit includes an anti-breakdown diode; The AC voltage source is connected between the first end of the first current limiting resistor and the first end of the anti-breakdown diode, the second end of the first current limiting resistor is connected to the first end of the second current limiting resistor and the first end of the first pull-up resistor, the second end of the anti-breakdown diode is connected to the second end of the second current limiting resistor and the inversion circuit, and the second end of the first pull-up resistor is connected to the inversion circuit.

5. The AC detection circuit according to claim 4, characterized in that: The isolation unit includes an optocoupler, a first end of the optocoupler is connected to the second end of the first current limiting resistor and the first end of the second current limiting resistor, a second end of the optocoupler is connected to the second end of the anti-breakdown diode and the second end of the second current limiting resistor, a third end of the optocoupler is connected to the first end of the first pull-up resistor, and a fourth end of the optocoupler is connected to the inversion circuit.

6. The AC detection circuit according to claim 1, characterized in that: The inversion circuit comprises: a third current limiting unit, a second pull-up unit and a first switch unit; A first end of the third current limiting unit is connected to the AC acquisition circuit, a first end of the second pull-up unit is connected to the power supply end, a second end of the third current limiting unit is connected to a first end of the first switch unit, a first end of the second pull-up unit is connected to a second end of the first switch unit, and a third end of the first switch unit is grounded.

7. The AC detection circuit according to claim 6, characterized in that: The third current limiting unit includes a third current limiting resistor, the second pull-up unit includes a second pull-up resistor, and the first switch unit includes a first transistor; The first end of the third current limiting resistor is connected to the AC acquisition circuit, the first end of the second pull-up resistor is connected to the power supply end, the second end of the third current limiting resistor is connected to the first end of the first transistor, the first end of the second pull-up resistor is connected to the second end of the first transistor, and the third end of the first transistor is grounded.

8. The AC detection circuit according to claim 1, characterized in that: The integration circuit comprises: a fourth current limiting unit, a third pull-up unit, a second switch unit and an integration unit; The first end of the fourth current limiting unit is connected to the inversion circuit and the latch circuit, the second end of the fourth current limiting unit is connected to the first end of the second switch unit, the first end of the third pull-up unit is connected to the power supply end, the second end of the third pull-up unit is connected to the second end of the second switch unit, the first end of the integration unit and the latch circuit, and the second end of the integration unit is connected to the third end of the second switch unit and then grounded.

9. The AC detection circuit according to claim 8, characterized in that: The fourth current limiting unit includes a fourth current limiting resistor, the third pull-up unit includes a third pull-up resistor, the second switch unit includes a second triode, and the integration unit includes an integration capacitor; The first end of the fourth current limiting resistor is connected to the inversion circuit and the latch circuit, the second end of the fourth current limiting resistor is connected to the first end of the second transistor, the first end of the third pull-up resistor is connected to the power supply end, the second end of the third pull-up resistor is connected to the second end of the second transistor, the first end of the integration capacitor and the latch circuit, and the second end of the integration capacitor is connected to the third end of the second transistor and then grounded.

10. The AC detection circuit according to claim 1, characterized in that: The latch circuit comprises: a trigger unit, a fifth current limiting unit and a third switch unit; The first end of the trigger unit is connected to the integration circuit, the second end of the trigger unit is connected to the first end of the third switch unit, the inversion circuit and the integration circuit, the third end of the trigger unit is connected to the first end of the fifth current limiting unit, the second end of the fifth current limiting unit is connected to the second end of the third switch unit, and the third end of the third switch unit is grounded.

11. The AC detection circuit according to claim 10, characterized in that: The trigger unit includes a trigger, the fifth current limiting unit includes a fifth current limiting resistor, and the third switch unit includes a third triode; The first end of the trigger is connected to the integration circuit, the second end of the trigger is connected to the first end of the third transistor, the inversion circuit and the integration circuit, the third end of the trigger is connected to the first end of the fifth current limiting resistor, the second end of the fifth current limiting resistor is connected to the second end of the third transistor, and the third end of the third transistor is grounded.

12. An AC detection system, characterized in that: The AC detection circuit comprises the AC detection circuit described in any one of claims 1 to 11.

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