Semiconductor power device

Abstract

The utility model belongs to the technical field of semiconductor devices, and discloses a semiconductor power device which comprises a TEC substrate, the TEC substrate comprises a heat dissipation plate, a PN junction layer and a heat collection plate which are sequentially stacked from bottom to top, a chip and power pins are both attached to the upper surface of the heat collection plate, and the two TEC pins are connected with the positive current input end and the negative current input end of the PN junction layer respectively; by adopting the TEC substrate and utilizing the semiconductor refrigeration principle, heat can be actively conducted from the heat collection plate to the heat dissipation plate, so that the heat dissipation efficiency is improved, and the heat dissipation device has the advantages of being good in heat dissipation performance and capable of meeting the heat dissipation requirement of a high-power device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a semiconductor power device. Background Art

[0002] The structure of traditional power discrete devices is as follows Fig. 9 As shown, it includes a heat sink 1', a chip 2', a conductive sheet 3' or welding wires, pins 4' and a plastic package (not shown in the figure). The chip 2' is mounted on the heat sink 1' and is electrically connected to the pins 4' through the conductive sheet 3' or welding wires; wherein the heat sink 1' is usually a simple plate structure (such as a copper plate, a copper-clad ceramic plate, etc.).

[0003] When this type of power discrete device is working, heat is generated from the inside of the chip 2'. Relying on the characteristics of heat transmission from high temperature to low temperature, the heat is diffused to the heat sink 1', and then dissipated from the heat sink 1' to the external heat dissipation structure. This heat dissipation method is a passive heat dissipation that completely relies on contact heat conduction. It is limited by the specific heat capacity of the heat sink 1' in the device. When the heat fills the heat sink 1' in the device, the internal heat will form a thermal balance with the external heat, limiting the continuous dissipation of heat, so the heat dissipation performance is poor.

[0004] Therefore, the prior art needs to be improved and enhanced. Utility Model Content

[0005] The purpose of the present application is to provide a semiconductor power device with good heat dissipation performance.

[0006] The present application provides a semiconductor power device, comprising a substrate, a chip mounted on the upper surface of the substrate, a plurality of power pins mounted on the upper surface of the substrate and electrically connected to the chip, and a plastic package; the substrate is a TEC substrate, the TEC substrate comprises a heat sink, a PN junction layer and a heat collecting plate stacked in sequence from bottom to top, the substrate is connected to two TEC pins; the chip and the power pins are both mounted on the upper surface of the heat collecting plate, the two TEC pins are respectively connected to the positive and negative current input ends of the PN junction layer; the substrate, the chip, the connection end of the power pin connected to the substrate, and the connection end of the TEC pin connected to the substrate are all plastic-sealed by the plastic package, and the bottom surface of the heat sink is exposed.

[0007] By adopting the TEC substrate and utilizing the principle of semiconductor refrigeration, heat can be actively transferred from the heat collecting plate to the heat dissipating plate, thereby improving the heat dissipation efficiency. It has the advantages of good heat dissipation performance and can meet the heat dissipation requirements of high-power devices.

[0008] Preferably, the PN junction layer includes a plurality of N-type semiconductor components and a plurality of P-type semiconductor components, and the N-type semiconductor components and the P-type semiconductor components are alternately arranged and sequentially connected in series to form a plurality of PN junctions connected in series.

[0009] This structural design can significantly improve the efficiency of thermoelectric conversion. When current passes through the PN junction, a temperature difference is generated due to the Seebeck effect of the semiconductor material, thereby achieving thermoelectric conversion. The series connection of multiple PN junctions not only increases the total thermoelectric potential, but also maximizes the use of thermoelectric materials in a limited space. The alternating arrangement design can effectively increase the number and contact area of ​​PN junctions, further improving the efficiency of thermoelectric conversion.

[0010] Preferably, the chip accounts for more than 95% of the area of ​​the upper surface of the heat collecting plate.

[0011] By setting the chip area ratio on the surface of the heat collector to more than 95%, the area of ​​the heat collector is used to the maximum extent. This design helps to increase the contact area between the chip and the heat collector, thereby improving the heat conduction efficiency. The large contact area between the chip and the heat collector can more effectively transfer the heat generated by the chip to the heat collector, and then dissipate it through the PN junction layer and the heat sink. This high-ratio design makes full use of the limited substrate space, maximizes the heat dissipation area, and helps to improve the heat dissipation performance of the entire semiconductor power device.

[0012] Preferably, the chip has a drain, a gate, a Kelvin source and a source, the drain is arranged at the bottom of the chip, and the gate, the Kelvin source and the source are all arranged at the top of the chip; the power pin includes a drain pin, a gate pin, a Kelvin source pin and a source pin; the upper surface of the heat collector is provided with a first copper clad layer and three first pads, the bottom surface of the chip is conductively mounted on the first copper clad layer, and the drain pin is welded on the first copper clad layer; the gate pin, the Kelvin source pin and the source pin are respectively welded on the three first pads, and are respectively electrically connected to the gate, the Kelvin source and the source.

[0013] Preferably, the power pins are arranged in a straight line on the same side edge of the heat collecting plate; the two TEC pins are welded on the upper surface of the heat dissipation plate, and the power pins and the TEC pins are arranged on two sides of the substrate opposite to each other.

[0014] Preferably, the gate and the Kelvin source are both arranged on a side of the top of the chip close to the power pin, and the source is arranged on a side of the top of the chip away from the power pin; the gate and the Kelvin source are electrically connected to the corresponding power pin through leads, and the source is electrically connected to the corresponding power pin through a conductive sheet.

[0015] Preferably, the gate is provided with one, the Kelvin source is provided with two, the source is provided with two, the gate is provided on a symmetry line at the top of the chip, the two Kelvin source are symmetrically arranged about the symmetry line and are respectively located on both sides of the gate, the two source are symmetrically arranged about the symmetry line, and the two Kelvin source are respectively connected to the two source;

[0016] The gate is electrically connected to the gate pin via the lead, one of the Kelvin sources is electrically connected to the Kelvin source pin via the lead, and two sources are electrically connected to the source pin via the same conductive sheet.

[0017] Preferably, the conductive sheet includes an integrally formed first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion are perpendicular to each other to form an L-shaped structure; the two ends of the first connecting portion are respectively welded to the two source electrodes, and the middle portion of the first connecting portion is bent upward and convex to form an arch structure; the end of the second connecting portion away from the first connecting portion is bent downward from the edge of the chip and welded to the source pin.

[0018] Preferably, the inner angle at the connection between the first connection portion and the second connection portion is a right angle or an acute angle.

[0019] Preferably, the chip is a silicon carbide MOSFET chip.

[0020] Beneficial effects: The semiconductor power device provided in the present application includes a TEC substrate, which includes a heat sink, a PN junction layer and a heat collecting plate stacked in sequence from bottom to top, the chip and the power pins are mounted on the upper surface of the heat collecting plate, and the two TEC pins are respectively connected to the positive and negative current input ends of the PN junction layer; by adopting the TEC substrate and utilizing the principle of semiconductor refrigeration, heat can be actively conducted from the heat collecting plate to the heat sink, thereby improving the heat dissipation efficiency, and has the advantages of good heat dissipation performance and being able to meet the heat dissipation requirements of high-power devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 An exploded diagram of a semiconductor power device provided in an embodiment of the present application.

[0022] Figure 2 A three-dimensional diagram of a semiconductor power device provided in an embodiment of the present application.

[0023] Figure 3 This is a diagram of the internal structure of a semiconductor power device provided in an embodiment of the present application.

[0024] Figure 4 A three-dimensional diagram of a TEC substrate.

[0025] Figure 5 Schematic diagram of the structure of the PN junction layer.

[0026] Figure 6 A three-dimensional image of the chip.

[0027] Figure 7 It is a top view of the connection structure of the chip, TEC substrate and each pin.

[0028] Figure 8 It is a schematic diagram of the structure of the conductive sheet.

[0029] Fig. 9 It is a schematic diagram of the structure of an existing power discrete device.

[0030] Explanation of reference numerals: 1. substrate; 101. heat sink; 1011. second solder pad; 102. PN junction layer; 1021. N-type semiconductor component; 1022. P-type semiconductor component; 103. heat collector; 1031. first copper cladding layer; 1032. first solder pad; 2. chip; 201. gate; 202. Kelvin source; 203. source; 3. power pin; 301. drain pin; 302. gate pin; 303. Kelvin source pin; 304. source pin; 4. plastic package; 5. TEC pin; 6. conductive solder layer; 7. lead; 8. conductive sheet; 801. first connecting portion; 8011. arch structure; 802. second connecting portion. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0032] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0033] In the application of semiconductor power devices, heat dissipation has always been a key factor restricting device performance and reliability. Traditional power discrete devices use passive heat dissipation, relying on the property of heat conduction from high temperature to low temperature to diffuse heat from the chip to the heat sink, and then from the heat sink to the external heat dissipation structure. However, this heat dissipation method has obvious limitations. Due to the limited specific heat capacity of the heat sink, when the heat accumulates to a certain extent, a thermal equilibrium will be formed between the inside and outside of the device, making it difficult to continuously dissipate the heat. In this case, the chip temperature may rise rapidly, exceeding the safe operating range, seriously affecting the performance and life of the device.

[0034] In order to solve the problem of insufficient heat dissipation performance of semiconductor power devices, several possible solutions were first considered. One idea is to increase the area of ​​the heat sink or improve its material. However, this will lead to an increase in the size of the device, which is not in line with the development trend of miniaturization. Another method is to use a liquid cooling system, but this will increase system complexity and cost. The use of heat pipes or phase change materials to improve heat dissipation efficiency is also considered. Although these methods can improve heat dissipation performance to a certain extent, they still belong to the category of passive heat dissipation and cannot achieve active control of chip temperature.

[0035] This reminds us of thermoelectric cooling technology (TEC), which has the ability to actively cool and heat, and can precisely control the temperature. However, traditional TEC is usually used as part of an external heat dissipation system rather than being directly integrated into a power device. Based on this, this application proposes an innovative solution: integrating TEC directly into the substrate of a power device to form a new type of TEC substrate. This design not only enables active heat dissipation, but also maintains the compact structure of the power device.

[0036] Please refer to Figure 1-Figure 4 In some embodiments of the present application, a semiconductor power device comprises a substrate 1, a chip 2 mounted on the upper surface of the substrate 1, a plurality of power pins 3 mounted on the upper surface of the substrate 1 and electrically connected to the chip 2, and a plastic package 4; the substrate 1 is a TEC substrate, the TEC substrate comprises a heat sink 101, a PN junction layer 102 and a heat collecting plate 103 stacked in sequence from bottom to top, the substrate 1 is connected to two TEC pins 5; the chip 2 and the power pins 3 are both mounted on the upper surface of the heat collecting plate 103, and the two TEC pins 5 are respectively connected to the positive and negative current input ends of the PN junction layer 102 (such as Figure 5 In the figure, a is a positive current input terminal, and b is a negative current input terminal); the substrate 1, the chip 2, the connection terminal of the power pin 3 connected to the substrate 1, and the connection terminal of the TEC pin 5 connected to the substrate 1 are all sealed by the plastic sealing body 4, and the bottom surface of the heat sink 101 is exposed.

[0037] By adopting the TEC substrate and utilizing the principle of semiconductor refrigeration, heat can be actively transferred from the heat collecting plate 103 to the heat dissipating plate 101, thereby improving the heat dissipation efficiency. It has the advantages of good heat dissipation performance and can meet the heat dissipation requirements of high-power devices.

[0038] Specifically, this design utilizes the Peltier effect. When current passes through the PN junction layer 102, heat is absorbed on one side of the PN junction and released on the other side. By controlling the direction and magnitude of the current, the temperature of the chip 2 can be precisely controlled. The heat collecting plate 103 is located above the PN junction layer 102 and can quickly absorb the heat generated by the chip 2; the heat dissipating plate 101 is located below the PN junction layer 102 and is used to dissipate heat; wherein the bottom surface of the heat dissipating plate 101 is exposed, which is convenient for heat exchange with an external heat dissipation device, thereby dissipating heat to the external heat dissipation device.

[0039] Specifically, see Figure 5 The PN junction layer 102 includes a plurality of N-type semiconductor components 1021 and a plurality of P-type semiconductor components 1022 . The N-type semiconductor components 1021 and the P-type semiconductor components 1022 are alternately arranged and sequentially connected in series to form a plurality of PN junctions connected in series.

[0040] This structural design can significantly improve the efficiency of thermoelectric conversion. When current passes through the PN junction, a temperature difference is generated due to the Seebeck effect of the semiconductor material, thereby achieving thermoelectric conversion. The series connection of multiple PN junctions not only increases the total thermoelectric potential, but also maximizes the use of thermoelectric materials in a limited space. The alternating arrangement design can effectively increase the number and contact area of ​​PN junctions, further improving the efficiency of thermoelectric conversion.

[0041] The alternating arrangement of the N-type semiconductor elements 1021 and the P-type semiconductor elements 1022 may adopt different patterns. One possible arrangement is an "S"-shaped arrangement, that is, the N-type semiconductor elements 1021 and the P-type semiconductor elements 1022 are alternately arranged along an S-shaped path. Another possible arrangement is a "snake" arrangement, that is, the N-type semiconductor elements 1021 and the P-type semiconductor elements 1022 are alternately arranged along a back-and-forth path (such as Figure 5 These arrangements help to maximize the number of PN junctions within a limited space.

[0042] The number and size of the N-type semiconductor components 1021 and the P-type semiconductor components 1022 can be set according to the actual size restriction of the semiconductor power device; the larger the size of the PN junction in the PN junction layer 102 (i.e., the larger the size of the N-type semiconductor components 1021 and the P-type semiconductor components 1022), the greater the current load capacity, and the greater the load current, the stronger the heat dissipation capacity. Generally, the length and width of the semiconductor power device are relatively limited, and it is difficult to increase the size of the PN junction in the length and width directions, but the limitation in the thickness direction is relatively small. Therefore, the thickness of the PN junction can be increased as much as possible within the allowable range (i.e., the height of the N-type semiconductor components 1021 and the P-type semiconductor components 1022 can be increased as much as possible), thereby improving the heat dissipation capacity. For example, the thickness of the PN junction can be set to 100μm-200μm, but is not limited thereto.

[0043] The heat sink 101 and the heat collecting plate 103 may be made of insulating materials with high thermal conductivity, such as aluminum nitride ceramics, but not limited thereto.

[0044] Furthermore, a second copper clad layer may be provided at the bottom of the heat sink 101 for bonding with an external heat sink to assist heat dissipation. The thickness of the second copper clad layer may be set according to actual needs, preferably greater than 10 μm.

[0045] In fact, the heat dissipation efficiency of the TEC substrate is proportional to the contact area (referring to the contact area between the chip 2 and the heat collecting plate 103). The larger the area of ​​the chip 2 on the upper surface of the heat collecting plate 103, the higher the heat dissipation efficiency.

[0046] Therefore, in some preferred embodiments, the area of ​​the chip 2 on the upper surface of the heat collecting plate 103 accounts for more than 95%.

[0047] By setting the area ratio of the chip 2 on the upper surface of the heat collecting plate 103 to be above 95%, the area of ​​the heat collecting plate 103 is utilized to the maximum extent. This design helps to increase the contact area between the chip 2 and the heat collecting plate 103, thereby improving the heat conduction efficiency. The large area contact between the chip 2 and the heat collecting plate 103 can more effectively transfer the heat generated by the chip 2 to the heat collecting plate 103, and then dissipate it through the PN junction layer 102 and the heat dissipation plate 101. This high-ratio design makes full use of the limited space of the substrate 1, maximizes the heat dissipation area, and helps to improve the heat dissipation performance of the entire semiconductor power device.

[0048] In some embodiments, see Figure 6 , Figure 7The chip 2 has a drain (not shown in the figure), a gate 201, a Kelvin source 202 and a source 203. The drain is arranged at the bottom of the chip 2, and the gate 201, the Kelvin source 202 and the source 203 are all arranged at the top of the chip 2; the power pin 3 includes a drain pin 301, a gate pin 302, a Kelvin source pin 303 and a source pin 304; the upper surface of the heat collecting plate 103 is provided with a first copper cladding layer 1031 and three first pads 1032 (such as Figure 4 As shown in FIG. 1 ), the bottom surface of the chip 2 is conductively mounted on the first copper clad layer 1031 (for example, the bottom surface of the chip 2 can be mounted on the first copper clad layer 1031 through a conductive solder layer 6, as shown in FIG. Figure 1 As shown; wherein the conductive solder layer 6 can be a solder sheet or solder paste, etc.), the drain pin 301 is welded on the first copper cladding layer 1031; the gate pin 302, the Kelvin source pin 303 and the source pin 304 are respectively welded on the three first pads 1032, and are electrically connected to the gate 201, the Kelvin source 202 and the source 203, respectively.

[0049] A drain electrode is arranged at the bottom of the chip 2, and is conductively mounted on the first copper clad layer 1031 on the heat collector 103, thereby realizing electrical connection between the drain electrode and the drain pin 301, and increasing the heat dissipation area. A gate electrode 201, a Kelvin source electrode 202, and a source electrode 203 are arranged on the top of the chip 2. By welding these electrodes and the corresponding power pins 3 to the three first pads 1032 on the heat collector 103, electrical connection is realized, and the reliability of the connection is ensured. The first copper clad layer 1031 is arranged on the heat collector 103, which not only provides good electrical conductivity, but also enhances the heat dissipation effect.

[0050] The thickness of the first copper cladding layer 1031 can be set according to actual needs, for example, preferably greater than 20 μm.

[0051] In some embodiments, see Figure 7 , each power pin 3 is arranged along a straight line on the same side edge of the heat collecting plate 103 ; two TEC pins 5 are welded on the upper surface of the heat dissipation plate 101 , and the power pin 3 and the TEC pin 5 are relatively arranged on both sides of the substrate 1 .

[0052] The power pins 3 are arranged in a straight line along the same side of the heat collecting plate 103. This layout can simplify the circuit design, reduce the complexity of wiring, and help reduce parasitic inductance and resistance, thereby improving the electrical performance of the device. At the same time, this arrangement is also convenient for the connection and packaging of external circuits. The TEC pins 5 are welded on the upper surface of the heat sink 101. This design can directly connect the TEC pins 5 to the heat sink 101 to improve the heat dissipation efficiency. The TEC pins 5 and the power pins 3 are arranged on both sides of the substrate 1 relative to each other, which can effectively separate the thermal management system and the electrical system and reduce the mutual interference between them. This layout design not only optimizes the electrical performance and heat dissipation performance of the device, but also improves the overall integration and space utilization of the device. By reasonably arranging the positions of the power pins 3 and the TEC pins 5, more efficient thermal management and electrical performance can be achieved in a limited space, thereby improving the overall performance and reliability of the semiconductor power device.

[0053] Among them, two second pads 1011 can be set on the side of the upper surface of the heat sink 101 away from the power pin 3, and the two TEC pins 5 are respectively welded to the two second pads 1011 (such as Figure 4 , Figure 7 as shown).

[0054] Further, see Figure 3 , Figure 7 The gate 201 and the Kelvin source 202 are both arranged on the side of the top of the chip 2 close to the power pin 3, and the source 203 is arranged on the side of the top of the chip 2 away from the power pin 3; the gate 201 and the Kelvin source 202 are electrically connected to the corresponding power pin 3 through the lead 7, and the source 203 is electrically connected to the corresponding power pin 3 through the conductive sheet 8.

[0055] By rationally arranging the electrode positions at the top of the chip 2 and adopting different connection methods, the electrical connection structure between the chip 2 and the power pin 3 is optimized. The gate 201 and the Kelvin source 202 are arranged on the side of the top of the chip 2 close to the power pin 3, which can shorten the connection distance with the corresponding power pin 3, reduce parasitic inductance and resistance, increase switching speed and reduce losses. Connection through the lead 7 can flexibly adapt to different layout requirements while ensuring good electrical performance. The source 203 is arranged on the side of the top of the chip 2 away from the power pin 3 and is connected to the power pin 3 through the conductive sheet 8. This design can increase the contact area of ​​the source 203, reduce the resistance of the source 203, and improve the current carrying capacity of the device. The use of the conductive sheet 8 can also provide a better heat dissipation path, which is conducive to the rapid diffusion of heat.

[0056] In some possible implementations, see Figure 6 , Figure 7, one gate 201 is provided, two Kelvin source electrodes 202 are provided, two source electrodes 203 are provided, and the gate 201 is provided on a symmetrical line at the top of the chip 2 (such as Figure 7 On the straight line F in the figure, two Kelvin source electrodes 202 are symmetrically arranged about the symmetry line and are respectively located on both sides of the gate electrode 201, and two source electrodes 203 are symmetrically arranged about the symmetry line. The two Kelvin source electrodes 202 are respectively connected to the two source electrodes 203 (the connection can be achieved through the metallization layer or through the doped region inside the chip 2);

[0057] The gate 201 is electrically connected to the gate pin 302 through the lead 7, one of the Kelvin sources 202 is electrically connected to the Kelvin source pin 303 through the lead 7, and the two sources 203 are electrically connected to the source pin 304 through the same conductive sheet 8 (such as Figure 3 as shown).

[0058] The symmetrical layout of the gate 201, the Kelvin source 202 and the source 203 can balance the current distribution, reduce parasitic inductance, and improve the switching speed and efficiency of the device. The interconnection design of the Kelvin source 202 and the source 203 can more accurately detect the voltage of the source 203, reduce measurement errors, and improve the control accuracy of the device. The differentiated electrode connection method can meet the electrical characteristics requirements of different electrodes and optimize the signal transmission path; wherein the gate 201 and a Kelvin source 202 are electrically connected to the corresponding pin through the lead 7, which can reduce the delay and interference of signal transmission. The lead 7 can be made of gold wire or aluminum wire, but is not limited to this. The two sources 203 are electrically connected to the source pin 304 through the same conductive sheet 8. This design can reduce the parasitic inductance of the source 203 and improve the switching performance of the device. The conductive sheet 8 can be made of copper or aluminum material, but is not limited to this.

[0059] Preferably, see Figure 8 The conductive sheet 8 includes an integrally formed first connection portion 801 and a second connection portion 802, the first connection portion 801 and the second connection portion 802 are perpendicular to each other to form an L-shaped structure (for example, the conductive sheet 8 is formed by bending an L-shaped metal sheet); the two ends of the first connection portion 801 are respectively welded to the two source electrodes 203, and the middle portion of the first connection portion 801 is bent upward to form an arch structure 8011; the end of the second connection portion 802 away from the first connection portion 801 is bent downward from the edge of the chip 2 and is welded to the source pin 304 (for example, Figure 3 as shown).

[0060] Among them, the first connecting part 801 and the second connecting part 802 are perpendicular to each other to form an L-shaped structure, which can effectively utilize the space and provide good mechanical strength; the two ends of the first connecting part 801 are respectively welded to the two source electrodes 203 to ensure a stable and reliable electrical connection; the middle part of the first connecting part 801 is bent and convex upward to form an arch structure 8011, which can increase the elasticity of the conductive sheet 8 and help alleviate thermal stress (this thermal stress is caused by the different thermal expansion coefficients of the conductive sheet 8 and the chip 2 during operation), thereby improving the reliability of the device; the end of the second connecting part 802 away from the first connecting part 801 is bent downward from the edge of the chip 2 and is welded to the source pin, which can optimize the wiring and reduce space occupancy.

[0061] The design of the curved arch structure 8011 may have many variations, for example, a circular arc protrusion, a triangular or trapezoidal protrusion may be used.

[0062] Further, see Figure 8 , the inner angle c at the connection between the first connection portion 801 and the second connection portion 802 is a right angle or an acute angle.

[0063] The thermal stress may not be completely relieved by the arch structure 8011. In this case, the inner angle c is not rounded, so as to keep the inner angle c as a right angle or an acute angle. Due to the stress concentration phenomenon, the residual thermal stress will be concentrated at the inner angle c, thereby reducing the impact of the thermal stress on other positions and further improving the stability and reliability of the electrical connection.

[0064] Among them, the specific type of chip 2 can be set according to actual needs. For example, in some embodiments, chip 2 is a silicon carbide MOSFET chip; silicon carbide material has characteristics such as wide bandgap, high critical breakdown electric field, and high thermal conductivity, so that silicon carbide-based MOSFET chips perform well in high temperature, high frequency, and high voltage applications. The selection of silicon carbide MOSFET chips can significantly improve the performance of semiconductor power devices. First, the wide bandgap characteristics of silicon carbide enable the device to work stably at higher temperatures, improving the reliability and durability of the device. Secondly, the high critical breakdown electric field allows the device to withstand higher operating voltages, expanding the scope of application. Furthermore, excellent thermal conductivity helps to better dissipate heat, reduce thermal resistance, and increase power density. In addition, the switching loss of silicon carbide MOSFET is low, and higher efficiency can be achieved in high-frequency applications. By using silicon carbide MOSFET chips and combining the thermoelectric cooling function of the TEC substrate, the heat dissipation performance and working stability of semiconductor power devices can be further optimized. This combination not only solves the heat dissipation challenges brought about by high power density, but also maintains good electrical properties over a wider temperature range, thereby improving the performance and reliability of the overall device.

[0065] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0066] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor power device, comprising a substrate (1), a chip (2) mounted on the upper surface of the substrate (1), a plurality of power pins (3) mounted on the upper surface of the substrate (1) and electrically connected to the chip (2), and a plastic package (4); characterized in that: The substrate (1) is a TEC substrate, comprising a heat sink (101), a PN junction layer (102) and a heat collecting plate (103) stacked in sequence from bottom to top, the substrate (1) being connected to two TEC pins (5); the chip (2) and the power pin (3) being mounted on the upper surface of the heat collecting plate (103), the two TEC pins (5) being respectively connected to the positive and negative current input ends of the PN junction layer (102); the connection ends of the substrate (1), the chip (2) and the power pin (3) connected to the substrate (1) and the connection ends of the TEC pin (5) connected to the substrate (1) are all plastic-sealed by the plastic sealing body (4), and the bottom surface of the heat sink (101) is exposed.

2. The semiconductor power device according to claim 1, characterized in that: The PN junction layer (102) comprises a plurality of N-type semiconductor components (1021) and a plurality of P-type semiconductor components (1022); the N-type semiconductor components (1021) and the P-type semiconductor components (1022) are alternately arranged and sequentially connected in series to form a plurality of PN junctions connected in series.

3. The semiconductor power device according to claim 1, characterized in that: The chip (2) accounts for more than 95% of the area of ​​the upper surface of the heat collecting plate (103).

4. The semiconductor power device according to claim 1, characterized in that: The chip (2) comprises a drain, a gate (201), a Kelvin source (202) and a source (203); the drain is arranged at the bottom of the chip (2); the gate (201), the Kelvin source (202) and the source (203) are all arranged at the top of the chip (2); the power pin (3) comprises a drain pin (301), a gate pin (302), a Kelvin source pin (303) and a source pin (304); the upper surface of the heat collecting plate (103) is provided with A first copper clad layer (1031) and three first solder pads (1032) are provided, the bottom surface of the chip (2) is conductively mounted on the first copper clad layer (1031), the drain pin (301) is welded on the first copper clad layer (1031); the gate pin (302), the Kelvin source pin (303) and the source pin (304) are respectively welded on the three first solder pads (1032), and are respectively electrically connected to the gate, the Kelvin source (202) and the source (203).

5. The semiconductor power device according to claim 4, characterized in that: The power pins (3) are arranged along a straight line on the same side edge of the heat collecting plate (103); the two TEC pins (5) are welded on the upper surface of the heat dissipation plate (101), and the power pins (3) and the TEC pins (5) are arranged on two sides of the substrate (1) opposite to each other.

6. The semiconductor power device according to claim 5, characterized in that: The gate electrode (201) and the Kelvin source electrode (202) are both arranged on a side of the top of the chip (2) close to the power pin (3), and the source electrode (203) is arranged on a side of the top of the chip (2) away from the power pin (3); the gate electrode (201) and the Kelvin source electrode (202) are electrically connected to the corresponding power pin (3) through a lead wire (7), and the source electrode (203) is electrically connected to the corresponding power pin (3) through a conductive sheet (8).

7. The semiconductor power device according to claim 6, characterized in that: One gate (201) is provided, two Kelvin source electrodes (202) are provided, and two source electrodes (203) are provided. The gate (201) is provided on a symmetry line at the top of the chip (2). The two Kelvin source electrodes (202) are symmetrically arranged about the symmetry line and are respectively located on both sides of the gate (201). The two source electrodes (203) are symmetrically arranged about the symmetry line. The two Kelvin source electrodes (202) are respectively connected to the two source electrodes (203). The gate (201) is electrically connected to the gate pin (302) via the lead (7), one of the Kelvin sources (202) is electrically connected to the Kelvin source pin (303) via the lead (7), and the two sources (203) are electrically connected to the source pin (304) via the same conductive sheet (8).

8. The semiconductor power device according to claim 7, characterized in that: The conductive sheet (8) comprises an integrally formed first connection portion (801) and a second connection portion (802), the first connection portion (801) and the second connection portion (802) being perpendicular to each other to form an L-shaped structure; two ends of the first connection portion (801) are respectively welded to the two source electrodes (203), and the middle portion of the first connection portion (801) is bent upward and convex to form an arch structure (8011); an end of the second connection portion (802) away from the first connection portion (801) is bent downward from the edge of the chip (2) and welded to the source electrode pin (304).

9. The semiconductor power device according to claim 8, characterized in that: The internal angle at the connection between the first connection portion (801) and the second connection portion (802) is a right angle or an acute angle.

10. The semiconductor power device according to claim 4, characterized in that: The chip (2) is a silicon carbide MOSFET chip.

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