Metal column array structure and chip packaging structure
Through the integrated circuit network and welding method within the dielectric layer of the metal column array structure, the problem of lack of circuit network and electroplated copper columns in the prior art is solved, and efficient circuit connection and signal transmission is achieved, simplifying the POP packaging process and reduces the cost and difficulty of packaging substrates.
Patent Information
- Application Number
- CN202420242207.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-31
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-01-31
AI Technical Summary
The existing metal column array structure lacks circuit network attributes in packaging connections, resulting in restrictions in application scenarios where electrical functions are required, and the height of electroplated copper columns is limited, which is easy to damage and affect the substrate function. It is difficult to manufacture POP packages.
Design a metal column array structure, in which the metal columns extend into the plastic sealing layer and connect to the dielectric layer, integrate the line network, realize the function of the circuit network, and is welded with the substrate through electroplating nickel layer and solder layer, which is compatible with the plastic sealing process, reducing costs and manufacturing Difficulty, double-layer substrates are used to improve wiring density and signal integrity, and optimize SOC chip packaging through perforation structure.
It realizes the acquisition of electrical network functions without additional costs, reduces the manufacturing cost and difficulty of packaging substrates, improves signal integrity and wiring density, simplifies the POP packaging process, adapts to different application needs, and reduces electromagnetic interference.
Smart Images
Figure CN222320265U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, in particular to a metal column array structure and a chip packaging structure. Background Art
[0002] Plastic encapsulation substrate and chip packaging are two common concepts in the field of electronic component manufacturing and integrated circuits. They are important components in the manufacturing process of electronic products, but they refer to different contents.
[0003] Plastic encapsulation substrate: Plastic encapsulation substrate refers to the basic material that connects and supports integrated circuits (such as SOC chips) and other electronic components. It is a carrier that carries and connects electronic components and is usually made of plastic materials with good insulation properties. On the plastic encapsulation substrate, circuit wiring and metal pads are manufactured through PCB (Printed Circuit Board) technology so that electronic components (such as SOC chips, sensors, memory, etc.) can be welded or installed on it.
[0004] Metal array structure refers to a group of orderly arranged metal pins or pads used to connect integrated circuit chips and external circuits. These metal pins are usually located at the bottom of the chip package and are used to establish electrical connections between the packaged chip and the plastic package substrate or PCB. The metal array structure is designed to achieve high-density signal transmission and reliable connection.
[0005] In the prior art, the packaging connection between the array structure of metal pillars and the plastic package substrate is generally achieved by the following two technical solutions:
[0006] Technical Solution 1: The metal columns are fixed by plastic packaging materials, electrically isolated from each other, and have no circuit network connection. It is suitable for general heat conduction, electrical conduction and padding applications, such as padding boards, adapter boards, etc.
[0007] The technical problems that are prone to exist in technical solution 1 are as follows:
[0008] 1. Metal columns have no circuit network properties and require additional circuit networks to achieve connections with electrical functions;
[0009] 2. Application scenarios that require electrical functions are limited; obtaining electrical network functions requires additional costs.
[0010] Technical Solution 2: The copper pillar is electroplated using a substrate processing technology, and protrudes about 100um to 200um from the substrate surface. The copper pillar connects the internal circuit network of the substrate and has electrical network properties. It is used in scenarios such as heat conduction, electrical conduction, and padding.
[0011] The technical problems existing in the second technical solution are as follows:
[0012] 1. The copper pillars are electroplated on the surface of the package substrate. The height of the copper pillars cannot be too high due to the limitations of the electroplating process;
[0013] 2. There is a large stress at the root of the connection between the electroplated copper column and the packaging substrate, which is easy to damage the copper column during processing, use, transportation, etc. In severe cases, the copper column is easy to break, thus affecting the overall function of the substrate.
[0014] Meanwhile, when the metal pillar array is applied to the packaging of chip structures, it is more difficult to manufacture than POP packaging, and it is not easy to realize mass production of POP packaging.
[0015] As described above, we have designed a metal pillar array structure and a metal pillar array structure of an integrated circuit to solve the above problems. Utility Model Content
[0016] The purpose of the utility model is to provide a metal column array structure and a chip packaging structure to solve at least one of the above problems existing in the prior art.
[0017] In order to achieve the above purpose, the utility model adopts the following technical solutions:
[0018] A metal pillar array structure comprises a substrate portion, a SOC chip mounting area is arranged in the middle of the substrate portion, a plurality of first metal pillars are arranged around the SOC chip mounting area, the substrate portion comprises a plastic sealing layer and a dielectric layer, one end of the first metal pillar extending into the plastic sealing layer is connected to a circuit in the dielectric layer, and the other end of the first metal pillar extending out of the plastic sealing layer is sequentially provided with a first electroplated nickel layer and a first solder layer.
[0019] In the present technical solution, since one end of the first metal column extends into the plastic packaging layer and is connected to the circuit in the dielectric layer, a circuit network is integrated in the dielectric layer of the metal column array structure. As an independent whole, it is used in the packaging process to realize the circuit network connection function and obtain the electrical network function without incurring additional costs.
[0020] Since the other end of the first metal column extending out of the plastic encapsulation layer is provided with a first electroplated nickel layer and a first solder layer in sequence, the first metal column and the substrate portion are electrically connected by welding, and the metal column protruding out of the plastic encapsulation layer can be compatible with the height space requirements of the molding process. At the same time, one end of the first metal column is located in the plastic encapsulation layer, and the first metal column is not processed by electroplating, which is lower in cost than the electroplating processing method of the prior art. In addition, the first metal column and the substrate portion are electrically connected by welding as described above, and when connected, the diameter and height of the metal column can have a variety of size options to meet the requirements of electrical current capacity.
[0021] A SOC chip mounting area is provided in the middle of the substrate for mounting the SOC chip. The metal column array structure of the integrated circuit has its own circuit network, which makes the output line design of the SOC chip packaging main substrate more flexible and convenient, and at the same time facilitates the reduction of the number of layers of the packaging substrate structure, thereby reducing the manufacturing cost and difficulty of the packaging substrate.
[0022] Furthermore, in order to facilitate integration with a POP storage chip and improve the conductive effect, a memory chip pad is provided at the upper end of the dielectric layer, and a copper layer is provided at the end of the memory chip pad.
[0023] Further, in order to provide different substrate parts to meet different usage requirements, the substrate part includes a single-layer substrate or a double-layer substrate, the plastic sealing layer of the single-layer substrate is a first plastic sealing layer, and a solder resist ink layer is provided on the single-layer substrate;
[0024] The double-layer substrate includes a first substrate and a second substrate, the first substrate and the second substrate are connected via a third plastic encapsulation layer, a second metal column is provided inside the third plastic encapsulation layer, the second metal column is electrically connected to the first substrate and the second substrate, and the bottom of the second substrate is electrically connected to the first metal column.
[0025] Compared with single-layer substrate plastic packaging, double-layer substrate can achieve:
[0026] 1. Higher wiring density: Double-layer substrates allow for higher wiring density within the same package area. By routing signals between two wiring layers, more signal lines can be accommodated within a limited space and the integration of wiring can be improved.
[0027] 2. Reduce signal interference: Double-layer substrates can reduce mutual interference between signals by separating the wiring of different signal layers, which helps to improve signal integrity and reduce the risk of electromagnetic interference.
[0028] 3. More flexible wiring routing: Double-layer substrates provide more flexible wiring routing options. By routing signal wires between two wiring layers, complex circuit layouts and signal transmission paths can be more easily implemented.
[0029] 4. Separation of high-speed and low-speed signals: Double-layer substrates allow high-speed and low-speed signals to be routed on different layers, which helps isolate high-frequency and sensitive signals to reduce mutual interference and crosstalk.
[0030] 5. Reduce wiring power consumption: Since the double-layer substrate provides more wiring layers, power consumption and signal paths can be better managed. Separating the signal line and the power line can reduce power consumption noise and improve the performance of the circuit.
[0031] Furthermore, in order to provide different SOC chip installation areas to meet different usage requirements, the SOC chip installation area is a solid substrate structure, or the SOC chip installation area is a solid substrate structure with a through hole in the middle.
[0032] A hole is dug in the middle of the substrate according to the size of the SOC chip to be installed, and then a metal column array is plastic-sealed, and the SOC chip is installed inside the hole. By opening a hole in the substrate, the thickness of the packaged SOC chip can be further reduced, and a thinner POP chip packaging structure can be manufactured. In addition, the SOC chip can be perfectly matched with the substrate to ensure that the chip is installed in the correct position, avoiding installation difficulties or connection problems caused by size mismatch, which helps to improve production efficiency and reduce the probability of errors during assembly.
[0033] In highly integrated circuits, EMI issues may interfere with signal transmission and the normal operation of equipment. By opening perforations on the substrate, not only can the space of the substrate be effectively utilized, but it can also help reduce electromagnetic interference between the SOC chip and other components. The signal transmission path can be better managed, EMI issues can be reduced, and after installation, a thinner POP chip packaging structure can be manufactured.
[0034] Further, in order to provide a suitable circuit according to needs, the circuit includes a laminated circuit or a rewiring circuit.
[0035] Specifically, the laminated circuit is to laminate the circuit and dielectric layer on the surface of the plastic packaging material by lamination, and process the memory chip pad on the outer surface of the substrate. The rewiring circuit is to integrate the circuit electroplating onto the dielectric layer by the RDL rewiring method, forming a circuit structure in which the RDL rewiring layer and the dielectric layer are separated.
[0036] The utility model also provides a chip packaging structure, which includes a POP storage chip, a SOC chip and a metal column array structure, wherein the POP storage chip package is connected to the top of the substrate, the SOC chip is installed in the SOC chip installation area, a packaging carrier is connected between the SOC chip and the bottom of the metal column array structure, a second plastic layer is provided between the packaging carrier and the plastic layer, the top of the first metal column extends into the interior of the first plastic layer and the second plastic layer and is connected to the circuit, and the other end of the first metal column extending out of the second plastic layer is provided with a first electroplated nickel layer and a first solder layer in sequence. Specifically, the other end of the first metal column protrudes relative to the surface of the second plastic layer, and both ends of the first metal column are connected to the first electroplated nickel layer and the first solder layer.
[0037] The chip packaging structure of the utility model simplifies the existing stacked POP packaging process, reduces the POP stacking packaging process and manufacturing difficulty, and has good mass production performance.
[0038] Furthermore, in order to facilitate welding with a PCB circuit board, a plurality of solder balls are evenly arranged on the bottom of the package carrier.
[0039] Furthermore, in order to facilitate the fixing and welding of the SOC chip on the packaging substrate, a third metal column is connected to the bottom of the SOC chip, and a second electroplated nickel layer and a second solder layer are provided at the tail end of the third metal column.
[0040] Furthermore, in order to achieve welding and fixing between the POP storage chip and the substrate portion, a solder ball is connected between the bottom of the POP storage chip and the substrate portion.
[0041] The beneficial effects of the utility model are as follows: in the technical solution, since one end of the first metal column extends into the plastic packaging layer and is connected to the circuit in the dielectric layer, a circuit network is integrated in the dielectric layer of the metal column array structure. As an independent whole, it is used in the packaging process to realize the circuit network connection function and obtain the electrical network function without incurring additional costs.
[0042] Since the other end of the first metal column extending out of the plastic encapsulation layer is provided with a first electroplated nickel layer and a first solder layer in sequence, the first metal column and the substrate portion are electrically connected by welding, and the metal column protruding out of the plastic encapsulation layer can be compatible with the height space requirements of the molding process. At the same time, one end of the first metal column is located in the plastic encapsulation layer, and the first metal column is not processed by electroplating, which is lower in cost than the electroplating processing method of the prior art. In addition, the first metal column and the substrate portion are electrically connected by welding as described above, and when connected, the diameter and height of the metal column can have a variety of size options to meet the requirements of electrical current capacity.
[0043] A SOC chip mounting area is provided in the middle of the substrate for mounting the SOC chip. The metal column array structure of the integrated circuit has its own circuit network, which makes the output line design of the SOC chip packaging main substrate more flexible and convenient, and at the same time facilitates the reduction of the number of layers of the packaging substrate structure, thereby reducing the manufacturing cost and difficulty of the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Figure 1 It is a bottom view of the laminated metal column array structure in the utility model;
[0045] Figure 2 It is a top view of the laminated metal column array structure in the utility model;
[0046] Figure 3 for Figure 1 AA section view;
[0047] Figure 4 for Figure 1 BB cross-sectional view;
[0048] Figure 5 It is a bottom view of the substrate portion of the laminated metal column array structure of the utility model as a perforated structure;
[0049] Figure 6 It is a top view of the substrate portion of the laminated metal column array structure of the utility model as a perforated structure;
[0050] Figure 7 for Figure 5 AA section view;
[0051] Figure 8 for Figure 5 BB cross-sectional view;
[0052] Fig. 9 A bottom view of the rewiring metal column array structure in the utility model;
[0053] Fig.10 It is a top view of the rewiring metal column array structure in the utility model;
[0054] Fig.11 for Fig. 9 AA section view;
[0055] Fig.12 for Fig. 9 BB cross-sectional view;
[0056] Fig.13 A bottom view of the substrate portion of the rewiring metal column array structure of the present invention as a perforated structure;
[0057] Fig.14 It is a top view of the substrate portion of the rewiring metal pillar array structure of the utility model as a perforated structure;
[0058] Fig.15 for Fig.13 AA section view;
[0059] Fig.16 for Fig.13 BB cross-sectional view;
[0060] Fig.17 It is a bottom view of the double-layer rewiring metal column array structure in the utility model;
[0061] Fig.18 A top view of a double-layer rewiring metal column array structure in the utility model;
[0062] Fig.19 for Fig.17 AA section view;
[0063] Fig. 20 for Fig.17 BB cross-sectional view;
[0064] Fig.21 It is a bottom view of the substrate portion of the double-layer rewiring metal column array structure of the utility model as a perforated structure;
[0065] Fig. 22 It is a top view of the substrate portion of the double-layer rewiring metal column array structure of the utility model as a perforated structure;
[0066] Fig.23 for Fig.21 AA section view;
[0067] Fig.24 for Fig.21 BB cross-sectional view;
[0068] Fig.25 It is a bottom view of the double-layer laminated metal column array structure in the utility model;
[0069] Fig.26 It is a top view of the double-layer laminated metal column array structure in the utility model;
[0070] Fig. 27 for Fig.25 AA section view;
[0071] Fig.28 for Fig.25 BB cross-sectional view;
[0072] Fig.29 It is a bottom view of the substrate portion of the double-layer laminated metal column array structure of the utility model as a perforated structure;
[0073] Fig.30 It is a top view of the substrate portion of the double-layer laminated metal column array structure of the present invention as a perforated structure;
[0074] Fig.31 for Fig.29 AA section view;
[0075] Fig.32 for Fig.29 BB cross-sectional view;
[0076] Fig.33 is a processing flow chart of a metal pillar array structure;
[0077] Fig.34 This is a schematic diagram of the structure of the single-layer laminated circuit metal column stacking package POP proposed by the utility model;
[0078] Fig.35 This is a schematic diagram of the structure of the single-layer rewiring metal column stacking package POP proposed by the utility model;
[0079] Fig.36 This is a schematic diagram of the structure of the double-layer laminated circuit metal column stacking package POP proposed by the utility model;
[0080] Fig.37 This is a schematic diagram of the structure of the double-layer rewiring metal column stacking package POP proposed by the utility model;
[0081] Fig.38 This is a schematic diagram of the structure of the hole-drilling double-layer rewiring metal column stacking package POP proposed by the utility model;
[0082] Fig.39 This is a schematic diagram of the structure of the hole-drilled double-layer laminated circuit metal column stacking package POP proposed by the utility model;
[0083] Fig.40 This is a schematic diagram of the structure of the hole-drilling single-layer rewiring metal column stacking package POP proposed by the utility model;
[0084] Fig.41 This is a schematic diagram of the structure of the hole-drilled single-layer laminated circuit metal column stacking package POP proposed by the utility model;
[0085] Fig.42 This is a process flow chart of the single-layer laminated circuit metal column stacking packaging proposed by the utility model;
[0086] Fig.43 This is a schematic diagram of the structure after the single-layer laminated circuit metal column stacking packaging is completed;
[0087] Fig.44 This is a process flow chart of a single-layer rewiring metal column stacking package proposed by the utility model;
[0088] Fig.45 This is a process flow chart of the hole-digging single-layer rewiring metal column stacking packaging process proposed by the utility model;
[0089] Fig.46 A schematic diagram of a structure after the hole-drilling single-layer rewiring metal column stacking package proposed by the utility model is completed;
[0090] Fig.47 It is another structural schematic diagram of the single-layer hole-drilling and rewiring metal column stacking package proposed by the present invention after completion;
[0091] Fig.48 This is a process flow chart of the metal column stacking packaging process for a single-layer laminated circuit with holes proposed by the utility model.
[0092] In the figure: substrate part 1; SOC chip mounting area 2; first metal pillar 3; first plastic sealing layer 4; second plastic sealing layer 5; third plastic sealing layer 6; dielectric layer 7; first electroplated nickel layer 8; first solder layer 9; solder resist ink layer 10; first substrate 11; second substrate 12; second metal pillar 13; perforation 14; laminated circuit 15; redistribution circuit 16; POP storage chip 17; SOC chip 18; package carrier 19; solder ball 20; third metal pillar 21; second electroplated nickel layer 22; second solder layer 23; solder ball 24; package substrate 25; memory chip pad 26; copper layer 27; PCB circuit board 28. DETAILED DESCRIPTION
[0093] In order to more clearly illustrate the technical solutions in the embodiments of the utility model or the prior art, the utility model will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the utility model, but does not constitute a limitation of the utility model.
[0094] Embodiment 1:
[0095] like Figure 1-Figure 33 As shown, the present embodiment provides a metal pillar array structure, including a substrate portion 1, a SOC chip mounting area 2 is arranged in the middle of the substrate portion 1, a plurality of first metal pillars 3 are arranged around the SOC chip mounting area 2, the substrate portion 1 includes a plastic encapsulation layer and a dielectric layer 7, one end of the first metal pillar 3 extending into the plastic encapsulation layer is connected to the circuit in the dielectric layer 7, and the other end of the first metal pillar 3 extending out of the plastic encapsulation layer is sequentially provided with a first electroplated nickel layer 8 and a first solder layer 9.
[0096] In the present technical solution, since one end of the first metal pillar 3 extends into the plastic packaging layer and is connected to the circuit in the dielectric layer 7, a circuit network is integrated in the dielectric layer 7 of the metal pillar array structure. As an independent whole, it is used in the packaging process to realize the circuit network connection function and obtain the electrical network function without incurring additional costs.
[0097] Since the other end of the first metal column 3 extending out of the plastic encapsulation layer is provided with a first electroplated nickel layer 8 and a first solder layer 9 in sequence, the first metal column 3 is electrically connected to the substrate portion 1 by welding, and the metal column protruding from the plastic encapsulation layer can be compatible with the height space requirements of the molding process. At the same time, one end of the first metal column 3 is located in the plastic encapsulation layer, and the first metal column 3 is not processed by electroplating process, which is lower in cost than the electroplating processing method of the prior art. In addition, the first metal column 3 is electrically connected to the substrate portion 1 by welding as described above, and when connected, the diameter and height of the metal column can have a variety of size options to meet the requirements of electrical current capacity.
[0098] A SOC chip mounting area 2 is provided in the middle of the substrate portion 1 for mounting the SOC chip. The metal column array structure of the integrated circuit has its own circuit network, which makes the line design of the SOC chip packaging main substrate more flexible and convenient, and at the same time facilitates the reduction of the number of layers of the packaging substrate structure, thereby reducing the manufacturing cost and difficulty of the packaging substrate.
[0099] Embodiment 2:
[0100] This embodiment is optimized based on the above-mentioned embodiment 1.
[0101] In order to facilitate integration with the POP storage chip and improve the conductive effect, a memory chip pad 26 is provided at the upper end of the dielectric layer 7 , and a copper layer 27 is provided at the end of the memory chip pad 26 .
[0102] Embodiment 3:
[0103] This embodiment is optimized based on the above-mentioned embodiment 1.
[0104] In order to provide different substrate parts 1 to meet different usage requirements, the substrate part 1 includes a single-layer substrate or a double-layer substrate, the plastic sealing layer of the single-layer substrate is a first plastic sealing layer 4, and a solder resist ink layer 10 is provided on the single-layer substrate;
[0105] The double-layer substrate includes a first substrate 11 and a second substrate 12. The first substrate 11 and the second substrate 12 are connected by a third plastic encapsulation layer 6. A second metal column 13 is provided inside the third plastic encapsulation layer 6. The second metal column 13 is electrically connected to the first substrate 11 and the second substrate 12. The bottom of the second substrate 12 is electrically connected to the first metal column 3.
[0106] Compared with single-layer substrate plastic packaging, double-layer substrate can achieve:
[0107] 1. Higher wiring density: Double-layer substrates allow for higher wiring density within the same package area. By routing signals between two wiring layers, more signal lines can be accommodated within a limited space and the integration of wiring can be improved.
[0108] 2. Reduce signal interference: Double-layer substrates can reduce mutual interference between signals by separating the wiring of different signal layers, which helps to improve signal integrity and reduce the risk of electromagnetic interference.
[0109] 3. More flexible wiring routing: Double-layer substrates provide more flexible wiring routing options. By routing signal wires between two wiring layers, complex circuit layouts and signal transmission paths can be more easily implemented.
[0110] 4. Separation of high-speed and low-speed signals: Double-layer substrates allow high-speed and low-speed signals to be routed on different layers, which helps isolate high-frequency and sensitive signals to reduce mutual interference and crosstalk.
[0111] 5. Reduce wiring power consumption: Since the double-layer substrate provides more wiring layers, power consumption and signal paths can be better managed. Separating the signal line and the power line can reduce power consumption noise and improve the performance of the circuit.
[0112] Embodiment 4:
[0113] This embodiment is optimized based on the above-mentioned embodiment 1.
[0114] In order to provide different SOC chip mounting areas 2 to meet different usage requirements, the SOC chip mounting area 2 is a solid substrate structure, or the SOC chip mounting area 2 is a solid substrate structure with a through hole 14 opened in the middle.
[0115] A through hole 14 is dug in the middle of the substrate 1 according to the size of the SOC chip to be installed, and then a metal column array is plastic-sealed, and the SOC chip is installed inside the through hole 14. By opening the through hole 14 on the substrate 1, the thickness of the packaged SOC chip can be further reduced, and a thinner POP chip packaging structure can be manufactured. In addition, the SOC chip can be perfectly matched with the substrate 1 to ensure that the chip is installed in the correct position, avoiding installation difficulties or connection problems caused by size mismatch, which helps to improve production efficiency and reduce the probability of errors during assembly.
[0116] In highly integrated circuits, EMI problems may interfere with signal transmission and the normal operation of the device. By opening the through hole 14 on the substrate portion 1, not only can the space of the substrate portion 1 be effectively utilized, but it also helps to reduce the electromagnetic interference between the SOC chip and other components. The signal transmission path can be better managed, EMI problems can be reduced, and after installation, a thinner POP chip packaging structure can be manufactured.
[0117] It should be noted that when the SOC chip is covered with a plastic layer on the back of the SOC chip in the chip mounting area, the thickness of the packaged chip can be reduced and the reliability of the SOC chip can be enhanced by plastic sealing; when the SOC chip is in the SOC chip mounting area 2 and the back of the SOC chip is exposed, the thinnest packaged chip thickness can be achieved, maximizing the heat dissipation capacity of the SOC chip.
[0118] Embodiment 5:
[0119] This embodiment is optimized based on the above-mentioned embodiment 1.
[0120] In order to provide a suitable wiring according to the need, the wiring includes a laminated wiring 15 or a rewiring wiring 16.
[0121] Specifically, the laminated circuit 15 is formed by laminating the circuit and the dielectric layer 7 on the surface of the plastic packaging material by a lamination method, and processing the memory chip pad 26 on the outer surface of the substrate portion 1. The rewiring circuit 16 is formed by electroplating the circuit onto the dielectric layer 7 by an RDL rewiring method, forming a circuit structure in which the RDL rewiring layer and the dielectric layer 7 are spaced apart.
[0122] Compared with the prior art, the metal pillar array structure in this embodiment integrates the circuit network by lamination or rewiring method, and is used as an independent integral structure in the packaging process to realize the circuit network connection function.
[0123] Embodiment 6:
[0124] like Figure 34-Figure 48 As shown, the utility model also provides a chip packaging structure, which includes a POP storage chip 17, a SOC chip 18 and a metal column array structure as described in Examples 1-5, the POP storage chip 17 is packaged and connected to the top of the substrate part 1, the SOC chip 18 is installed in the SOC chip installation area 2, a packaging carrier 19 is connected between the SOC chip 18 and the bottom of the metal column array structure, a second plastic sealing layer 5 is provided between the packaging carrier 19 and the plastic sealing layer, the top of the first metal column 3 extends into the first plastic sealing layer 4 and the second plastic sealing layer 5 and is connected to the circuit, and the other end of the first metal column 3 extending out of the second plastic sealing layer 5 is provided with a first electroplated nickel layer 8 and a first solder layer 9 in sequence. Specifically, the other end of the first metal column 3 protrudes relative to the surface of the second plastic sealing layer 5, and both ends of the first metal column 3 are connected to the first electroplated nickel layer 8 and the first solder layer 9.
[0125] The chip packaging structure of the utility model simplifies the existing stacked POP packaging process, reduces the POP stacking packaging process and manufacturing difficulty, and has good mass production performance.
[0126] Embodiment 7:
[0127] This embodiment is optimized based on the above-mentioned embodiment 6.
[0128] In order to facilitate soldering with the PCB circuit board 28 , a plurality of solder balls 20 are evenly disposed on the bottom of the package carrier 19 .
[0129] Embodiment 8:
[0130] This embodiment is optimized based on the above-mentioned embodiment 6.
[0131] In order to facilitate the fixing and welding of the SOC chip 18 on the packaging substrate, a third metal column 21 is connected to the bottom of the SOC chip 18 , and a second electroplated nickel layer 22 and a second solder layer 23 are provided at the tail end of the third metal column 21 .
[0132] Embodiment 9:
[0133] This embodiment is optimized based on the above-mentioned embodiment 6.
[0134] In order to achieve welding and fixing between the POP storage chip 17 and the substrate portion 1 , a solder ball 24 is connected between the bottom of the POP storage chip 17 and the substrate portion 1 .
[0135] The utility model also provides a packaging method for a chip packaging structure, which includes the following steps:
[0136] S1. Provide a packaging carrier 19: vertically set a plurality of first metal pillars 3 in an array on the surface of the packaging carrier 19. The diameter of the first metal pillars 3 can have a variety of sizes to meet the current flow capacity requirements of the chip; the connection method between the packaging carrier 19 and the first metal pillars 3 includes one of adhesive bonding, vertical wire bonding, and brazing point connection; wherein, the packaging carrier 19 can be a plate of different materials such as glass, wood, metal, etc.
[0137] S2, plastic sealing of the first metal column array 3: plastic sealing and reinforcement of the first metal column array are performed by using a plastic sealing process to obtain a plastic sealing body.
[0138] The first metal column array is partially encapsulated by the plastic encapsulation body to maintain the required size and shape stability. The first metal column 3 is processed by a pre-forming process, not an electroplating process, and has a competitive advantage of low cost.
[0139] S3, carrier removal: removing the package carrier 19 fixed on the plastic package body to obtain the metal needle plastic package body;
[0140] S4. Integrated circuit on the surface of plastic package: Grind and polish one side of the metal needle plastic package until the cross section of the first metal column 3 is exposed, and use a lamination method or a rewiring method to process the circuit network on the metal column cross-sectional pattern and the plastic cover of the metal array plastic package to form a circuit layer, and process the memory chip pad 26 on the outermost side of the circuit layer to realize the stacking packaging of the POP storage chip 17; compared with the prior art, the metal column array structure integrates the circuit network by lamination or rewiring method, and is used as an independent integral structure in the packaging process to realize the circuit network connection function.
[0141] S5, back grinding of the plastic package body and growing solder bumps: grinding and polishing the other side of the metal needle plastic package body until the cross section of the first metal column 3 is exposed, electroplating nickel on the cross section of the first metal column 3, and then growing solder bumps to form a first electroplated nickel layer 8 and a first solder layer 9;
[0142] S6, laser excavation of plastic encapsulation material: using laser equipment to ablate the plastic encapsulation material to a certain depth, exposing the first metal pillar 3, and selecting whether to excavate a hole 14 in the middle of the substrate portion 1 composed of the plastic encapsulation layer and the circuit layer according to the size and thickness of the SOC chip 18, to obtain a metal pillar array carrier;
[0143] The first metal column 3 protrudes relative to the surface of the plastic package body, and has a first electroplated nickel layer 8 and a first solder layer 9 at its end, so as to realize the electrical connection between the first metal column 3 and the packaging substrate 25 by welding. The protruding first metal column 3 can be compatible with the height space requirements of the molding process;
[0144] S7, cutting: cutting the metal column array carrier board integrated with the circuit network to obtain a single metal column array structure with the circuit network;
[0145] S8, preparing the SOC chip 18, the metal pillar array structure and the packaging substrate 25;
[0146] S9, packaging integration: welding the SOC chip 18 and the metal column array structure onto the packaging substrate 25 in sequence;
[0147] S10, glue dispensing of the SOC chip 18: filling the bottom area of the SOC chip 18 with glue to solidify the SOC chip 18 on the packaging substrate 25;
[0148] S11, if the SOC chip mounting area 2 is a solid substrate structure, the SOC chip 18 and the metal column array structure are encapsulated by a molding method, and the back of the SOC chip 18 is encapsulated by the molding material;
[0149] If the SOC chip mounting area 2 is a through-hole structure, a film-assisted molding method is used to perform film-assisted molding on the SOC chip 18 and the metal column array structure to expose the back of the SOC chip 18, thereby enhancing the heat dissipation capacity of the SOC chip 18 and reducing the thickness of the packaged chip;
[0150] When the SOC chip 18 is covered with plastic packaging material on the back of the chip in the SOC chip mounting area 2, the thickness of the packaged chip can be reduced and the reliability of the SOC chip 18 can be enhanced by plastic packaging; when the SOC chip 18 is in the chip mounting area and the back of the SOC chip 18 is exposed, the heat dissipation capacity of the SOC chip 18 is maximized. In the vertical direction, the SOC chip 18 can enter the perforation 14 area in full or in part, maximizing the reduction of the thickness of the overall chip package, achieving the thinnest package chip thickness, and improving the competitiveness of chip thickness.
[0151] S12, ball planting: ball planting is performed on the back side of the package substrate 25 after plastic packaging;
[0152] S13, cutting to obtain a single chip packaging structure;
[0153] S14, POP storage chip board-level SMT process integration: Integrate a single chip packaging structure on the terminal product printed PCB circuit board 28, and then integrate the POP storage chip 17 on the memory chip pad 26.
[0154] This embodiment has the following advantages: it simplifies the complex stacked POP packaging process, reduces the manufacturing difficulty of POP packaging, and facilitates mass production of POP packaging; the first metal column 3 has its own circuit network, which helps the output design of the packaging substrate 25 and the reduction of the number of substrate layers, thereby reducing the manufacturing cost and difficulty of the packaging substrate 25.
[0155] Ultra-thin POP stacking packaging with exposed die can be realized. The SOC chip 18 is first ground and thinned, and the back of the SOC chip 18 is molded with film-assisted molding (FAM molding) technology in the perforated space 14 of the plastic package body to expose the back of the SOC chip 18 and the surface of the wiring pad, further enhancing the heat dissipation capacity of the SOC chip 18 and improving performance. The metal column array integrated circuit function can realize the optimized design of the number and position of the metal column array to meet the electrical connection requirements of the storage chip.
[0156] Finally, it should be noted that the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.
Claims
1. A metal column array structure, characterized in that: It includes a substrate part, a SOC chip mounting area is arranged in the middle of the substrate part, a plurality of first metal pillars are arranged around the SOC chip mounting area, the substrate part includes a plastic packaging layer and a dielectric layer, one end of the first metal pillar extending into the plastic packaging layer is connected to the circuit in the dielectric layer, and the other end of the first metal pillar extending out of the plastic packaging layer is sequentially provided with a first electroplated nickel layer and a first solder layer.
2. A metal pillar array structure according to claim 1, characterized in that: A memory chip pad is disposed at the upper end of the dielectric layer, and a copper layer is disposed at the end of the memory chip pad.
3. The metal pillar array structure according to claim 1, characterized in that: The substrate portion includes a single-layer substrate or a double-layer substrate, the plastic sealing layer of the single-layer substrate is a first plastic sealing layer, and a solder resist ink layer is provided on the single-layer substrate; The double-layer substrate includes a first substrate and a second substrate, the first substrate and the second substrate are connected via a third plastic encapsulation layer, a second metal column is provided inside the third plastic encapsulation layer, the second metal column is electrically connected to the first substrate and the second substrate, and the bottom of the second substrate is electrically connected to the first metal column.
4. The metal pillar array structure according to claim 1, characterized in that: The SOC chip installation area is a solid substrate structure, or the SOC chip installation area is a solid substrate structure with a through hole in the middle.
5. The metal pillar array structure according to claim 1, characterized in that: The circuit includes a laminate circuit or a rewiring circuit.
6. A chip packaging structure, characterized in that: It comprises a POP storage chip, a SOC chip and a metal pillar array structure as described in any one of claims 1 to 5, wherein the POP storage chip package is connected to the top of a substrate portion, the SOC chip is installed in a SOC chip installation area, a package carrier is connected between the SOC chip and the bottom of the metal pillar array structure, a second plastic sealing layer is provided between the package carrier and the plastic sealing layer, the top end of the first metal pillar extends into the interior of the first plastic sealing layer and the second plastic sealing layer and is connected to the circuit, and the other end of the first metal pillar extending out of the second plastic sealing layer is provided with a first electroplated nickel layer and a first solder layer in sequence.
7. The chip packaging structure according to claim 6, characterized in that: A plurality of solder balls are evenly arranged on the bottom of the packaging carrier.
8. The chip packaging structure according to claim 6, characterized in that: A third metal column is connected to the bottom of the SOC chip, and a second electroplated nickel layer and a second solder layer are disposed at the tail end of the third metal column.
9. The chip packaging structure according to claim 6, characterized in that: A solder ball is connected between the bottom of the POP storage chip and the substrate.