Multi-wafer fan-out type interconnection packaging structure
Through the multi-chip fan-out interconnection package structure, high-density electrical connection is achieved using redistribution layers and interconnect bumps, solving the problems of low substrate wiring density and high cost of silicon interposer in traditional chip packages, achieving high efficiency and low cost multi-chip integration.
Patent Information
- Application Number
- CN202420873735.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-04-25
AI Technical Summary
In traditional chip packaging solutions, the substrate wiring density is low, and high-density die-to-die interconnection cannot be achieved. The silicon interposer layer is expensive and it is difficult to make a large-area interconnection structure.
The multi-chip fan-out interconnected packaging structure is adopted, and multiple wafers are encapsulated through plastic-sealing resin to form a packaging integrated structure. The interconnected bumps are set at the bottom of the redistribution layer, flip-fitting and welding to the packaging substrate, combining reflow soldering and underfill filling, Achieve high-density electrical connections.
It realizes a high-density, high-speed, and low-latency packaging solution, reduces costs and supports large-area production, which improves wiring density and interconnection efficiency compared to traditional solutions.
Smart Images
Figure CN222320268U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a multi-chip fan-out type interconnect packaging structure, belonging to the technical field of semiconductor packaging. Background Art
[0002] In traditional chip packaging solutions, a single chip or multiple chips are usually flip-chip soldered on a substrate through solder bumps or copper pillar bumps, and the chip and substrate are filled with underfill glue for flip-chip packaging. Due to the limitation of substrate process precision, the wiring density on the substrate is low, and high-density die-to-die interconnection is not possible. In order to solve this problem, the existing technology adds a layer of "silicon interposer" to the substrate, and multiple dies are connected to the silicon interposer face down, and the interconnection wiring between dies is completed on the interposer. In other words, the silicon interposer plays the role of die-die interconnection and die-substrate interconnection. The silicon interposer can be directly manufactured by semiconductor technology, so its wiring density is much higher than that of the substrate, which solves the problem of die-die interconnection.
[0003] However, the interposer needs to carry multiple dies, so its area is larger than the sum of the areas of all dies. The interposer is also made using semiconductor technology, which is costly and difficult to make in a large area. Therefore, a new solution is needed to solve this problem. Utility Model Content
[0004] The utility model aims to provide a multi-chip fan-out type interconnect packaging structure in order to overcome the deficiencies of the prior art.
[0005] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: a multi-chip fan-out interconnection packaging structure, comprising a packaging substrate, a first chip and a second chip; the first chip and the second chip are packaged together by a plastic packaging resin to form an integrated packaging structure; a redistribution layer is provided at the bottom of the first chip and the second chip to interconnect the I / O points of the first chip and the second chip; a plurality of interconnection bumps are provided at the bottom of the redistribution layer, and the packaged first chip and the second chip are flipped on the packaging substrate through the plurality of the interconnection bumps.
[0006] Preferably, the lower end of the interconnection bump is fixed to the packaging substrate by reflow soldering, so that the interconnection bump is welded to the solder joint on the packaging substrate.
[0007] Preferably, an underfill is filled between the package integrated structure formed by the first chip and the second chip and the package substrate.
[0008] Preferably, a plurality of solder balls are arranged at the bottom of the packaging substrate.
[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:
[0010] The utility model discloses a multi-chip fan-out interconnect packaging structure, which optimizes multi-chip interconnect integration by expanding electrical connections through fan-out technology, realizes heterogeneous and homogeneous integration, and integrates multiple independent chips into a fan-out packaging structure. Compared with the traditional substrate interconnect solution, the L / S of the fan-out interconnect solution can reach 2μm / 2μm, which can realize high-density, high-speed and low-latency packaging solutions; compared with the traditional silicon interposer solution, it can reduce costs and realize large-area production. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:
[0012] Attached Figure 1 The utility model is a schematic structural diagram of a multi-chip fan-out interconnect packaging structure.
[0013] In the figure: 1. Plastic encapsulation resin; 2. First chip; 3. Second chip; 4. Underfill; 5. Redistribution layer; 6. Interconnect bumps; 7. Package substrate; 8. Solder balls. DETAILED DESCRIPTION
[0014] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0015] As attached Figure 1 As shown, a multi-chip fan-out interconnect packaging structure described in the present invention includes a packaging substrate 7, a first chip 2 and a second chip 3.
[0016] The first chip 2 and the second chip 3 are packaged together by the plastic packaging resin 1 to form an integrated packaging structure. The number of chips can be increased according to actual processing needs. In this embodiment, the plastic packaging resin 1 is set to epoxy resin; a redistribution layer 5 is set at the bottom of the first chip 2 and the second chip 3 to interconnect the I / O points of the first chip 2 and the second chip 3, and the first chip 2 and the second chip 3 are interconnected with the redistribution layer 5, thereby realizing the interconnection of chips with different functions.
[0017] A plurality of interconnect bumps 6 are provided at the bottom of the redistribution layer 5, and the packaged first chip 2 and the second chip 3 are flipped on the packaging substrate 7 through the plurality of interconnect bumps 6, wherein the lower ends of the interconnect bumps 6 are fixed to the packaging substrate 7 by reflow soldering, so that the interconnect bumps 6 are welded to the solder joints on the packaging substrate 7.
[0018] An underfill 4 is filled between the package integrated structure formed by the first chip 2 and the second chip 3 and the package substrate 7 . After being cured, the underfill 4 can effectively protect the connection between the interconnect bump 6 and the package substrate 7 .
[0019] A plurality of solder balls are arranged on the bottom of the packaging substrate.
[0020] The processing process of the packaging structure described in this scheme is as follows:
[0021] Step 1: Wafer thinning and singulation;
[0022] Two wafers with different functions are thinned and cut into single chips respectively.
[0023] Step 2: Place the chip;
[0024] The semiconductor first wafer and the second wafer are placed face down on a temporary carrier (glass carrier).
[0025] Step 3: Plastic sealing;
[0026] The first chip, the second chip and the carrier are packaged together using a molding resin (usually epoxy resin). This step can provide mechanical support and protect the chip.
[0027] Step 4: Remove the carrier;
[0028] The packaged chip is removed from the temporary carrier through a carrier removal process.
[0029] Step 5: Redistribution layer (RDL) fabrication;
[0030] By making a redistribution layer on the molding material through processes such as lithography and electroplating, RDL can interconnect the I / O points of the first chip and the second chip and connect them to the surface of the carrier, thereby realizing chip interconnection between different functions and "fanning out" the I / O points.
[0031] Step 6: Bump attachment;
[0032] Interconnect bumps are formed on the RDL through a bump attachment process, and these interconnect bumps can be used to connect the packaged chip to the packaging substrate.
[0033] Step 7: Reflow soldering;
[0034] The packaged chip is flip-chip mounted on the packaging substrate and reflowed to weld the interconnect bumps to the solder joints on the packaging substrate.
[0035] Step 8: Bottom filling;
[0036] The underfill is filled between the packaged chip and the package substrate using the capillary phenomenon. After the underfill is cured, it can effectively protect the connection between the bump and the package substrate.
[0037] Step 9: Solder ball attachment;
[0038] Solder balls are formed on the package substrate through a solder ball attachment process.
[0039] The current mainstream single chip or multiple chips in the market are flip-chip soldered on the substrate through solder bumps or copper pillar bumps, and the underfill is filled between the chip and the substrate for flip-chip packaging. The difference of this solution is that the RDL redistribution layer interconnects two or more chips and fans out the I / O points. The fan-out technology is used to expand the electrical connection to optimize the interconnection and integration of multiple chips, realize heterogeneous and homogeneous integration, and integrate multiple independent chips into a fan-out package.
[0040] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.
Claims
1. A multi-chip fan-out interconnect packaging structure, characterized in that: The invention comprises a packaging substrate (7), a first chip (2) and a second chip (3); the first chip (2) and the second chip (3) are packaged together by a plastic packaging resin (1) to form a packaged integrated structure; a redistribution layer (5) is arranged at the bottom of the first chip (2) and the second chip (3) to interconnect the I / O points of the first chip (2) and the second chip (3); a plurality of interconnection bumps (6) are arranged at the bottom of the redistribution layer (5); and the packaged first chip (2) and the second chip (3) are flip-mounted on the packaging substrate (7) via the plurality of interconnection bumps (6).
2. A multi-chip fan-out interconnect packaging structure according to claim 1, characterized in that: The lower end of the interconnection bump (6) is fixed to the packaging substrate (7) by reflow soldering, so that the interconnection bump (6) is soldered to the solder joint on the packaging substrate (7).
3. The multi-chip fan-out interconnect packaging structure according to claim 1, characterized in that: An underfill (4) is filled between the integrated packaging structure formed by the first chip (2) and the second chip (3) and the packaging substrate (7).
4. The multi-chip fan-out interconnect packaging structure according to claim 1, characterized in that: A plurality of solder balls (8) are arranged at the bottom of the packaging substrate (7).