Integrated circuit with capacitive isolator
By forming a basic structure in the wafer manufacturing stage and increasing the dielectric layer thickness in the packaging stage, the problem of difficulty in improving the voltage resistance performance of the capacitor isolator in the prior art is solved, and cost reduction and strong process compatibility are achieved effect.
Patent Information
- Application Number
- CN202420855627.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-23
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-04-23
AI Technical Summary
When existing capacitive isolators improve voltage resistance, they need to develop special thick dielectric film processes, resulting in complex processes, high cost and incompatible with ordinary wafer manufacturing processes.
The first metal layer and the first dielectric layer are formed during the wafer manufacturing stage, and a capacitive isolator is constructed through the rewiring layer and the second dielectric layer during the packaging stage, increasing the dielectric layer thickness to improve voltage resistance while reducing the difficulty and cost of preparation , compatible with ordinary processes.
It is realized that without changing the ordinary wafer manufacturing process, the voltage withstand performance of the capacitive isolator is improved, the production cost and difficulty is reduced, and the special thick dielectric film process is not required, which enhances compatibility.
Smart Images
Figure CN222320272U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices, and in particular to an integrated circuit with a capacitive isolator. Background Art
[0002] In circuit design, the use of digital isolators is essential for safety, noise control, and interactive operation. There are three main isolation methods for current digital isolators, namely photoelectric coupling, electromagnetic coupling, and capacitive coupling. Among them, capacitive isolators using capacitive coupling isolation are usually compatible with standard complementary metal oxide semiconductor (CMOS) processes, and the main structure is a parallel plate capacitor with a metal layer as the upper and lower plates, and an insulating material with silicon dioxide as the main dielectric is filled between the two plates. Due to its small size, high integration, low power consumption, and high communication speed, it has been increasingly used in the fields of industry, medicine, and automobiles.
[0003] Generally speaking, a capacitor isolator can include a high-voltage capacitor isolator. The two parts of the circuit that need to be isolated are electrically coupled to the upper and lower plates respectively. The capacitor isolator conducts displacement current between the circuits to achieve signal transmission. At the same time, the thick insulating medium between the capacitor plates achieves low-frequency voltage isolation. Its voltage resistance performance is positively correlated with the thickness of the dielectric layer. When the dielectric layer increases, its voltage resistance performance is higher. Utility Model Content
[0004] In order to solve the above technical problems, the present application provides an integrated circuit with a capacitor isolator, which is compatible with ordinary wafer manufacturing processes while effectively increasing the thickness of the capacitor dielectric layer, is easy to implement, and has low cost.
[0005] According to a first aspect of the present application, an integrated circuit with a capacitive isolator is provided, characterized in that it includes:
[0006] at least one first device located in a first integrated region of the integrated circuit;
[0007] A second device, located in a second integrated region of the integrated circuit, comprises a first metal layer and a first dielectric layer located on the first metal layer;
[0008] A second dielectric layer is disposed above at least one of the first device and the second device;
[0009] a redistribution layer, located above the second dielectric layer, the redistribution layer being connected to at least one of the first devices;
[0010] a package body, covering at least one of the first device, the second device, the second dielectric layer and the redistribution layer,
[0011] The second device, the second dielectric layer and the redistribution layer constitute the capacitor isolator.
[0012] Optionally, the first dielectric layer includes at least one stacked oxide layer and / or at least one stacked silicide layer.
[0013] Optionally, the thickness of the second dielectric layer is positively correlated with the withstand voltage value of the capacitor isolator.
[0014] Optionally, the second dielectric layer is a polyimide layer.
[0015] Optionally, at least one of the first device and the second device is disposed on the same substrate.
[0016] Optionally, the first device includes at least one of an active device and a passive device.
[0017] Optionally, the first metal layer serves as a lower plate of the capacitor isolator, and the redistribution layer serves as an upper plate of the capacitor isolator.
[0018] Optionally, the integrated circuit has a first node and a second node, the upper plate of the capacitor isolator is connected to the first node, the lower plate of the capacitor isolator is connected to the second node, and the potential of the first node is greater than the potential of the second node.
[0019] Optionally, the integrated circuit further includes:
[0020] A pad bump is located on the surface of the redistribution layer above the second integrated region, and the upper plate of the capacitor isolator is externally connected through the pad bump.
[0021] The beneficial effects of this application include at least:
[0022] The embodiment of the present application combines the first metal layer and the first dielectric layer formed in the wafer manufacturing process with the second dielectric layer and the redistribution layer formed in the packaging process to form a capacitor isolator. Compared with the traditional solution, on the one hand, the second device formed in the wafer manufacturing stage of the present application only includes one metal layer (i.e., the first metal layer). Since fewer metal layers need to be formed, the wafer manufacturing cost can be reduced. On the other hand, the present application uses the packaging stage to add the second dielectric layer. While ensuring that the dielectric layer thickness of the capacitor isolator can be effectively increased to increase the withstand voltage of the capacitor isolator, there are no special requirements for the manufacturing process, that is, there is no need to develop a special thick dielectric film process, and the compatibility is strong, making the capacitor isolator in the integrated circuit easier to implement.
[0023] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 A cross-sectional view of an existing capacitor isolator is shown;
[0025] Figure 2 A cross-sectional view of an integrated circuit with a capacitive isolator provided according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0026] In order to facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.
[0027] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0028] In the description of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments. "And / or" herein is a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" refers to two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.
[0029] In addition, the same figure marks in the figures represent the same or similar structures, and thus their repeated description will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manners, and each part focuses on the differences from other parts. The same or similar parts between the various parts can be referenced to each other.
[0030] Figure 1 A cross-sectional view of an existing capacitor isolator is shown in FIG. Figure 1 As shown, the capacitor isolator 100 includes a substrate 110, a CONT layer (via contact layer) 190 located on the substrate, multiple metal layers (including a first metal layer 120, a second metal layer 140 and a third metal layer 160), multiple insulating layers (including a first insulating layer 130, a second insulating layer 150) and a protective layer (including a SiO2 layer 170 and a Si3N4 layer 180, the multiple metal layers and the multiple insulating layers are stacked in a certain order to form the capacitor isolator 100. Among them, the first metal layer 120 or the second metal layer 140 close to the substrate 110 serves as the lower plate of the capacitor isolator 100, the third metal layer 160 far from the substrate 110 serves as the upper plate of the capacitor isolator 100, and at least one insulating layer between the upper plate and the lower plate serves as the dielectric layer of the capacitor isolator 100.
[0031] In the field of high and low voltage circuit isolation, when it is necessary to prepare high voltage resistant capacitor isolators, the mainstream approach is to develop a special thick dielectric film process based on the standard CMOS process. Figure 1 Taking the capacitor isolator 100 in the example, generally, it is only necessary to prepare a dielectric layer (such as SiO2 film) of several microns to tens of microns between the upper and lower plates of the capacitor isolator 100. The preparation of the required thick dielectric film is difficult, and the process requires more metal layers, which has high requirements for FAB (Fabrication, semiconductor manufacturing process) and high costs.
[0032] In response to the above problems, an embodiment of the present application provides an integrated circuit with a capacitor isolator, wherein the capacitor isolator in the integrated circuit has device components completed in the wafer manufacturing stage and the packaging stage respectively, thereby utilizing the cooperation of the wafer manufacturing stage and the packaging stage to achieve better high-voltage resistance while reducing the difficulty and cost of preparing the capacitor isolator in the integrated circuit, and has good compatibility with ordinary FAB processes.
[0033] Figure 2 A cross-sectional view of the integrated circuit with the capacitive isolator is shown. Figure 2 As shown, the integrated circuit 200 includes: at least one first device 230 , a second device 220 , a second dielectric layer 240 , a redistribution layer 250 , and a package body 280 .
[0034] At least one first device 230 is located in a first integrated region of the integrated circuit 200 , and each first device 230 includes at least one of an active device and a passive device.
[0035] The second device 220 is located in the second integrated region of the integrated circuit 200 . The second device 220 includes a first metal layer 221 and a first dielectric layer 222 located on the first metal layer 221 .
[0036] The first dielectric layer 222 includes at least one stacked oxide layer and / or at least one silicide layer, wherein each oxide layer may include, for example, silicon oxide (SiO2) material, and each nitride layer may include, for example, silicon nitride (Si3N4) material.
[0037] It should be noted that the "device" mentioned in this article specifically refers to a device structure in an unpackaged state manufactured in a wafer foundry using a wafer manufacturing process (i.e., a FAB process, such as a front-end process, a mid-end process, and a back-end process).
[0038] In the integrated circuit 200, at least one first device 230 and a second device 220 may be disposed on the same substrate (or base plate) 210. Exemplarily, the substrate 210 may include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate 210 may also be made of electrically non-conductive materials such as glass, plastic, or sapphire wafers. In some examples, the substrate 210 may also refer to an integrated device integrated on a semiconductor material such as silicon, germanium, gallium arsenide, indium phosphide, etc. In this case, a similar device may be disposed between the substrate 210 and the bottom metal layer 221 of the second device 220. Figure 1 The CONT layer in the substrate 210 is provided to realize electrical connection between the substrate 210 and the metal layer 221.
[0039] The second dielectric layer 240 is disposed above at least one of the first device 230 and the second device 220. The second dielectric layer 240 includes, for example, a polyimide layer. Of course, the second dielectric layer 240 may also be a layer structure formed by other insulating materials.
[0040] A redistribution layer (RDL layer) 250 is located above the second dielectric layer 240, and the redistribution layer 250 is connected to at least one first device 230. Exemplarily, the second dielectric layer 240 located on the first device 230 has a plurality of through holes 241, and the redistribution layer 250 is connected to at least one first device 230 through the plurality of through holes 241. The redistribution layer 250 is made of, for example, a metal material (such as aluminum or copper).
[0041] The package body 280 covers at least one first device 230 , a second device 220 , a second dielectric layer 240 and a redistribution layer 250 .
[0042] In this embodiment, the second device 220, the second dielectric layer 240 and the redistribution layer 250 constitute the capacitor isolator 270 in the integrated circuit 200. In other words, in this embodiment, the capacitor isolator 270 in the integrated circuit 200 is composed of the first metal layer 221, the first dielectric layer 222, the second dielectric layer 240 and the redistribution layer 250 stacked in sequence, wherein the first metal layer 221 serves as the lower plate of the capacitor isolator 270, the redistribution layer 250 serves as the upper plate of the capacitor isolator 270, and the first dielectric layer 222 and the second dielectric layer 240 located between the first metal layer 221 and the redistribution layer 250 serve together as the dielectric layer between the upper and lower plates of the capacitor isolator 270.
[0043] In this embodiment, the thickness of the second dielectric layer 240 can be adjusted according to the required withstand voltage value, so that the withstand voltage value of the capacitor isolator 270 can be adjusted by adjusting the thickness of the second dielectric layer 240. For example, the thickness of the second dielectric layer 240 can be made thicker, and this adjustment method is easier to implement. It should be noted that when the structure of the second device 220 is determined, the thickness of the second dielectric layer 240 is positively correlated with the withstand voltage value of the capacitor isolator 270, that is, the thicker the thickness of the second dielectric layer 240, the higher the withstand voltage value of the capacitor isolator 270 finally formed.
[0044] In some optional examples, the metal layer in the second device 220 can also be multi-layered, and each metal layer can be isolated by an insulating dielectric layer. It can be understood that by increasing the number of metal layers in the second device 220, it is beneficial to increase the breakdown voltage of the capacitor isolator 270. Of course, as the number of metal layers in the second device 220 increases, the manufacturing cost will also increase accordingly.
[0045] In some examples, the integrated circuit 200 also includes a pad bump (BUMP) 260 located on the surface of the redistribution layer 250 above the second integrated region, and the upper plate of the capacitor isolator 270 is externally connected or connected to at least one first wafer device 230 through the pad bump 270. For example, the upper plate of the capacitor isolator 270 can be connected to the first node (high voltage node) in the integrated circuit 200 through the pad bump 270.
[0046] In some examples, the integrated circuit 200 further includes a ground electrode ( Figure 2), the first metal layer 221 (i.e., the lower plate of the capacitor isolator 270) is connected to the ground electrode of the integrated circuit 200. Of course, the first metal layer 221 (i.e., the lower plate of the capacitor isolator 270) is not limited to this connection relationship. In other examples, the first metal layer 221 (i.e., the lower plate of the capacitor isolator 270) can also be connected to the second node (low voltage node) in the integrated circuit 200.
[0047] It can be understood that when the upper plate of the capacitor isolator 270 is connected to the first node (high voltage node) of the high voltage part (or module) of the integrated circuit 200, and the lower plate of the capacitor isolator 270 is connected to the second node (low voltage node) of the low voltage part (or module) of the integrated circuit 200, the capacitor isolator 270 can achieve isolation between the high voltage part and the low voltage part of the integrated circuit 200. Among them, the high voltage node and the low voltage node are relative concepts, that is, the potential of the first node is greater than the potential of the second node.
[0048] It can be understood that in this embodiment, the first metal layer 221 and the first dielectric layer 222 in the capacitor isolator 270 are formed in the wafer manufacturing stage, and the second dielectric layer 240 and the redistribution layer 250 in the capacitor isolator 270 are formed in the packaging stage. That is to say, the capacitor isolator 270 in the integrated circuit 200 disclosed in this embodiment is manufactured and formed only after the integrated circuit 200 is packaged. When it is necessary to prepare the capacitor isolator 270 in the integrated circuit 200, the embodiment of the present application places the part of the dielectric layer and the upper plate structure required to form the capacitor isolator 270 in the packaging stage, so that the metal layers required to be prepared in the wafer manufacturing stage are less (such as only one metal layer close to the substrate needs to be prepared), the cost is lower, and there is no need to develop a special thick dielectric film process in the wafer manufacturing stage, which is easy to be compatible with the ordinary FAB process and has a low difficulty in preparation.
[0049] In addition, although the embodiment of the present application places part of the dielectric layer and the upper plate structure required to form the capacitor isolator 270 in the packaging stage, since the redistribution layer (RDL) 250 is a metal layer used to connect different functional areas inside the integrated circuit during the packaging stage, the second dielectric layer 240 is equivalent to the passivation layer (Passivation Interlayer, PI layer) located between the redistribution layer 250 and the integrated circuit. Both are indispensable hierarchical structures in integrated circuit packaging. That is to say, the capacitor isolator 270 disclosed in the embodiment of the present application does not add additional process steps during the packaging stage during preparation, making the capacitor isolator 270 disclosed in the embodiment of the present application easier to prepare.
[0050] It should also be noted that the topmost structure of the second device 220 formed in the wafer manufacturing stage of the embodiment of the present application is composed of a nitride layer or an oxide layer, which can serve as a surface protection layer of the device to prevent impurities, moisture, etc. in the external environment from damaging the device, so that the embodiment of the present application does not need to specially prepare a protection layer for the second device 220 in the wafer manufacturing stage, which is equivalent to saving process steps, or the nitride layer or oxide layer is the protection layer of the second device 220. At this time, it is equivalent to using the protection layer of the second device 220 to additionally serve as the dielectric layer of the capacitor isolator 270, thereby further increasing the thickness of the dielectric layer of the capacitor isolator 270, while increasing the high voltage resistance of the capacitor isolator 270 and reducing the demand and dependence of the capacitor isolator 270 on the thick dielectric film process.
[0051] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present application, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present application.
Claims
1. An integrated circuit having a capacitive isolator, characterized in that: include: at least one first device located in a first integrated region of the integrated circuit; A second device, located in a second integrated region of the integrated circuit, comprises a first metal layer and a first dielectric layer located on the first metal layer; A second dielectric layer, disposed above at least one of the first device and the second device; a redistribution layer, located above the second dielectric layer, the redistribution layer being connected to at least one of the first devices; a package body, covering at least one of the first device, the second device, the second dielectric layer and the redistribution layer, The second device, the second dielectric layer and the redistribution layer constitute the capacitor isolator.
2. The integrated circuit according to claim 1, wherein: The first dielectric layer includes at least one stacked oxide layer and / or at least one stacked silicide layer.
3. The integrated circuit according to claim 1, wherein: The thickness of the second dielectric layer is positively correlated with the withstand voltage value of the capacitor isolator.
4. The integrated circuit according to any one of claims 1 to 3, wherein: The second dielectric layer is a polyimide layer.
5. The integrated circuit according to claim 1, wherein: At least one of the first device and the second device is disposed on the same substrate.
6. The integrated circuit of claim 1, wherein: The first device includes at least one of an active device and a passive device.
7. The integrated circuit according to claim 1, wherein: The first metal layer serves as a lower plate of the capacitor isolator, and the redistribution layer serves as an upper plate of the capacitor isolator.
8. The integrated circuit according to claim 7, wherein: The integrated circuit has a first node and a second node, the upper plate of the capacitor isolator is connected to the first node, the lower plate of the capacitor isolator is connected to the second node, and the potential of the first node is greater than the potential of the second node.
9. The integrated circuit according to claim 7, wherein: The integrated circuit further comprises: A pad bump is located on the surface of the redistribution layer above the second integrated region, and the upper plate of the capacitor isolator is externally connected through the pad bump.