SiC MOSFET structure capable of improving conduction performance of body diode
By setting up multi-layer P-Well and N-type heavily doped and source drive systems in SiC MOSFETs, decomposing the current path, the problems of conduction loss and bipolar degradation of SiC MOSFET body diode are solved, and the conduction performance is improved and enhancement of flow capacity.
Patent Information
- Application Number
- CN202420964948.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-07
- Publication Date
- 2025-01-07
- Estimated Expiration
- 2034-05-07
AI Technical Summary
The high opening voltage of the parasitic diode inside the SiC MOSFET causes large losses, and long-term use can easily lead to bipolar degradation, affecting device reliability. The existing Schottky diodes improve reverse conduction performance will lead to device reverse blocking capabilities. Degradation and leakage current increase.
In the SiC MOSFET structure, a source driving groove is formed by setting up multi-layer P-Well and N-type heavily doped in the epitaxial layer, and spaced source driving system and gate driving system in the source electrode metal layer. , decompose the current path to reduce conduction loss.
It effectively reduces the on-off loss of the device in the third quadrant, improves the flow capacity, simplifies the manufacturing process, and significantly improves the performance of the device, and is suitable for complex circuit systems.
Smart Images
Figure CN222322090U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor device, in particular to a SiC MOSFET structure with improved body diode conduction performance. Background Art
[0002] Based on the advantages of high breakdown field strength, wide bandgap, high thermal conductivity, etc., SiC has become the most attractive power semiconductor material. Among the many SiC-based power devices, SiC MOSFET has lower specific on-resistance (Ron,sp) and higher switching frequency. Therefore, SiC MOSFET is more suitable for circuit systems with high power conversion density and high efficiency. However, in some power conversion circuit systems, diodes are often required as freewheeling tubes. For price and cost considerations, SiC MOSFET can be used as a switch tube, and the internal parasitic PiN body diode can also be used for freewheeling tubes. The bandgap width of SiC is 3 times that of Si. The parasitic body diode inside SiC MOSFET has a higher turn-on voltage (2.5 ~ 3V at room temperature), which is much higher than the body diode turn-on voltage of Si-based MOSFET (0.7 ~ 0.8V at room temperature), which leads to a large turn-on loss of the parasitic body diode inside SiC MOSFET. Another problem is that the long-term use of SiC MOSFET parasitic body diode is prone to bipolar degradation, which has a great impact on the long-term reliability of the device.
[0003] In recent years, a large number of research hotspots at home and abroad have focused on reducing the conduction loss of SiC MOSFET body diodes and solving the problem of bipolar degradation. Schottky diodes and junction barrier Schottky diodes are embedded in the MOSFET structure to improve the reverse conduction performance. However, these Schottky barrier metals will cause the device's reverse blocking ability to degrade and increase the leakage current.
[0004] Therefore, how to improve the conduction performance of the SiC MOSFET body diode and the current carrying capacity in the third quadrant to adapt to applications in more complex circuit systems is a task that needs to be solved urgently. Utility Model Content
[0005] In view of the above problems, the utility model provides a SiC MOSFET structure which reduces the conduction loss of the device in the third quadrant and improves the conduction performance of the body diode.
[0006] The technical solution of the utility model is:
[0007] Improve the body diode conduction performance SiC MOSFET structure, from bottom to top, including drain electrode, substrate, epitaxial layer and source electrode metal layer;
[0008] The epitaxial layer is provided with:
[0009] A plurality of P-Well well regions are provided, each extending downward from the top surface of the epitaxial layer;
[0010] P-type heavily doped, with a plurality of P-Well well regions extending downward from the top surface of the P-Well well region;
[0011] N-type heavy doping is provided, and is respectively extended downward from the top surface of the P-Well well region and connected to the P-type heavy doping; N-type heavy doping is respectively provided on both sides of the P-type heavy doping in the middle of the epitaxial layer;
[0012] The source electrode metal layer is provided with a source driving system and a gate driving system arranged at intervals;
[0013] The bottom of the source driving system and the bottom of the gate driving system are respectively connected to the corresponding N-type heavily doped, P-Well well region and JFET region, and the tops are respectively wrapped by corresponding passivation layers.
[0014] The source driving system comprises a source driving gate oxide layer and a source driving Ploy which are sequentially connected from bottom to top; the source driving gate oxide layer overlaps with the P-Well well region to form a source driving channel.
[0015] The gate driving system comprises a gate driving gate oxide layer and a gate driving Ploy which are sequentially connected from bottom to top; the gate driving gate oxide layer overlaps with the P-Well well region to form a gate driving channel.
[0016] Specifically, a buffer layer is provided on the upper surface of the substrate and is located between the substrate and the epitaxial layer.
[0017] Specifically, the depth of the P-type heavy doping is 0.3-0.4 um.
[0018] Specifically, the depth of the N-type heavy doping is 0.2-0.3 um.
[0019] The utility model provides a SiC MOS structure of a source-driven channel diode. When the SiC MOS device works in the third quadrant, a positive voltage is applied to the source to open part of the channel, so that part of the current flows from the source to the drain through the channel, and part of the current flows to the drain through the parasitic PiN diode. The current path can be decomposed into two directions, which greatly reduces the conduction loss of the device in the third quadrant. The method of the utility model has a simple manufacturing process and significant effect, and can be applied to the manufacture of new silicon carbide MOSFET power devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It is a schematic diagram of the structure of an N-type heavily doped substrate.
[0021] Figure 2 It is a schematic diagram of the structure of an N-type lightly doped epitaxial layer covering the upper surface.
[0022] Figure 3 is a schematic diagram of the structure of forming several P-Well well regions 6,
[0023] Figure 4 It is a schematic diagram of P-type heavy doping and N-type heavy doping structure.
[0024] Figure 5 is a schematic diagram of the structure of step S500,
[0025] Figure 6 It is a schematic diagram of the structure of forming the gate electrode Ploy.
[0026] Figure 7 This is a schematic diagram of the structure after the source region is opened.
[0027] Figure 8 is a schematic diagram of the structure of the deposited passivation layer.
[0028] Fig. 9 This is a schematic diagram of the structure after etching the passivation layer.
[0029] Fig.10 This is a schematic diagram of the source drive window structure.
[0030] Fig.11 It is a schematic diagram of depositing electrode metal to form a source contact structure.
[0031] Fig.12 is a schematic diagram of the structure of the drain electrode.
[0032] Fig.13 This is the current path diagram when SiC MOSFET works in the third quadrant;
[0033] 1 is the drain electrode, 2 is the drain ohmic contact layer, 3 is the substrate, 4 is the buffer layer, 5 is the epitaxial layer, 6 is the P-Well well region, 7 is the P-type heavily doped (or called P-plus), 8 is the ohmic contact metal layer, 9 is the source electrode metal layer, 10 is the passivation layer, 11 is the gate drive oxide layer, 12 is the gate electrode Ploy, 13 is the gate drive channel, 14 is the N-type heavily doped (or called N-plus), 15 is the source drive gate oxide layer, 16 is the source drive Ploy, 17 is the source drive channel, 18 is the JFET region, and 19 is the source drive contact metal. DETAILED DESCRIPTION
[0034] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.
[0035] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0036] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0037] Reference below Figure 1-13 Describe the utility model;
[0038] A method for preparing a SiC MOSFET structure with improved body diode conduction performance comprises the following steps:
[0039] Step S100, providing a doping concentration of 1e19cm -3 N-type heavily doped substrate 3; Figure 1 As shown;
[0040] Specifically, the N+ type heavily doped substrate 3 uses 4H-SiC material as the substrate, and the doping concentration is 1e19cm -3 , the doping element is N, the thickness is 360um, the thickness of the buffer layer 4 is 1um~1.2um, the thickness of this implementation case is 1um, and the doping concentration is 1e18cm -3 The drift layer thickness is 6~15um, and the doping concentration is 4e15~1e16cm -3 The epitaxial specifications of this case are 12um, 9.5e15cm -3 ;
[0041] The heavily doped substrate 3 has two surfaces, namely, an upper surface and a lower surface. The upper surface is covered with an N-type lightly doped epitaxial layer 5, and the lower surface forms a metal electrode layer; Figure 2 As shown, a buffer layer 4 is formed between the substrate 3 and the epitaxial layer 5;
[0042] Preferably, in step S100, a buffer layer 4 is provided on the upper surface of the heavily doped substrate 3, and is located between the substrate 3 and the epitaxial layer 5. The thickness of the epitaxial layer 5 is 6-15 um, and the doping concentration is 4e15-1e16 cm -3 .
[0043] Step S200, a window region is formed on the surface of the epitaxial layer 5 by mask lithography, and the window region is P-type doped to form a plurality of P-Well well regions 6, such as Figure 3 As shown;
[0044] Specifically, the P-Well adopts P-type doping, the doping element is Al, and an ion implanter is used to dope it. Before the P-Well well region 6 is implanted, a 30-50 nm SiO2 layer needs to be deposited on the surface of the drift layer. 2 The thin film cushion layer prevents high-energy ion implantation from damaging the surface of the SiC drift layer. The junction depth of the P-Well region 6 is 1~1.5um, the energy of each implantation is 80~500 Kev, and the implantation dose is 5e11~1e15 cm -3 The number of injections is 3 to 5. The P-Well region 6 is injected 3 times. The energy and dose of the injections are: 400Kev 1e14 cm -3 , 250Kev 1e12cm -3 ,110Kev5e11cm -3 ;
[0045] Step S300, the interval area between adjacent P-well well regions 6 is the JFET region 18, and the JFET region 18 is lightly doped through a mask;
[0046] JFET region 18 doping usually involves general ion implantation of the source region, and only the terminal region needs to be protected by a mask. The number of implantations is 4 to 5, and the energy of each implantation is 50 to 600 Kev, with an implantation dose of 5e11 to 1e12 cm -3 .
[0047] Step S400, P-type heavy doping 7 and N-type heavy doping 14 are performed on the surface of the P-Well region 6 by mask photolithography to form a source region and an ohmic contact region, such as Figure 4 As shown;
[0048] The depth of P-type heavy doping 7 is 0.3~0.4um, the doping energy is 100-300Kev, and the doping dose is 1e14~2e15cm -3 , the doping times are 2~3 times.
[0049] The depth of N-type heavy doping 14 is 0.2~0.3um, the doping energy is 70-150Kev, and the doping dose is 1e14~1e15cm -3 , the doping times are 2~3 times.
[0050] After all ion implantation is completed, activation annealing is required to activate the ions in the lattice gap to release electrical properties and repair the lattice damaged after ion implantation. In this case, a high-temperature vacuum annealing furnace is used, the annealing temperature is 1700℃, and the annealing time is 30 minutes; before activation annealing, a layer of C film needs to be covered on the wafer surface to protect the wafer surface.
[0051] Step S500, forming a gate drive oxide layer 11 on the top surface of the epitaxial layer 5 by a high temperature dry oxygen oxidation process, such as Figure 5 As shown;
[0052] Preferably, the gate driving oxide layer 11 is formed into an oxide film on the surface by high temperature dry thermal oxidation; the thermal oxidation temperature is 1250-1350° C., and the thickness of the gate driving oxide layer 11 is 50-100 nm.
[0053] In this case, the gate oxide growth temperature is 1300℃ and the growth thickness is 60nm. The grown gate oxide structure needs to be annealed with nitrogen-based gas to reduce the interface state of the gate oxide growth and improve the electron mobility. In this case, N 2 O was used as the annealing gas, and the annealing temperature and time were 1250°C and 2H respectively.
[0054] Step S600, Ploy is deposited on the surface of the gate driving oxide layer 11 to form a gate electrode Ploy12, and then a source region is opened by photolithography, development and dry etching processes, such as Figure 6-7 As shown;
[0055] Polysilicon Ploy is deposited by CVD, and the element doped with polysilicon is usually P element. The resistivity is reduced by in-situ saturation doping. The thickness of the deposited Ploy is 5000 ~ 8000A, and the ohmic contact area Ploy and the gate driving oxide layer 11 are etched synchronously by photolithography and then dry etching, and the source driving gate oxide layer 15 and the source driving Ploy16 are formed together.
[0056] Step S700, the gate electrode structure is isolated from the contact region by depositing a passivation layer 10. Figure 8 As shown;
[0057] The deposited passivation layer 10 is SiO 2 Or SiN film, the thickness of the film layer is 5000~8000A, and it is usually deposited by CVD method.
[0058] Step S800, etching the passivation layer 10 to open an ohmic contact window, and forming a good ohmic contact layer by depositing metal and alloying it with high temperature annealing; Fig. 9 As shown;
[0059] Further defined, an ohmic contact window is opened by dry etching, metal Ni, Ti or Ti / Ni composite is deposited by sputtering, and high temperature rapid annealing is performed after the metal deposition to form a metal compound with SiC; the annealing temperature is 950~1100℃, and the annealing time is 3~5min.
[0060] Step S900, a source driving window is opened on the surface of the passivation layer 10 by dry etching, such as Fig.10 As shown;
[0061] Step S1000: forming a source contact 19 by depositing electrode metal on the front side. Fig.11 As shown;
[0062] It is further defined that the front electrode metal is deposited by sputtering or evaporation, the common electrode metal is Al / Cu, and the thickness of the electrode metal is 4~6um.
[0063] Step S1100, the back side is thinned, metal is deposited, laser annealed and electrode metal is deposited to form a drain electrode 1, and a drain ohmic contact layer is formed between the drain electrode 1 and the substrate 3, such as Fig.12 shown.
[0064] Step S1100 includes:
[0065] Step S1101, thinning the substrate 3 through a back thinning process to reduce the on-resistance;
[0066] It is further defined that the front side is protected and the back side is thinned by mechanical grinding, and the thickness after thinning is 120-200 um;
[0067] Step S1102, depositing metal and performing laser annealing to form a back ohmic contact layer;
[0068] Further defined, a back ohmic contact metal is deposited, and commonly deposited metals include Ni, Ti, etc., and a back local laser annealing is performed to form an alloy;
[0069] Step S1103, depositing electrode metal on the back side to form a drain contact.
[0070] It is further defined that an electrode metal is deposited on the back to form a drain contact, and common metals include Ti, Ni, Ag, etc.
[0071] In summary, a method for manufacturing a SiC MOS device with a source-driven channel diode is provided. The advantage of this case is that a source-driven channel 17 is provided. When the device operates in the third quadrant, as shown in FIG. Fig.13 As shown, when a positive voltage is applied to the source, the current can flow through the channel and the body diode at the same time, reducing the conduction loss and improving the current carrying capacity; the utility model has a significant effect and a simple manufacturing process, and has broad prospects in the manufacture and application of new silicon carbide MOS.
[0072] Improve the body diode conduction performance SiC MOSFET structure, from bottom to top, including a drain electrode 1, a substrate 3, an epitaxial layer 5 and a source electrode metal layer 9;
[0073] The epitaxial layer 5 is provided with:
[0074] A plurality of P-Well well regions 6 are provided, each extending downward from the top surface of the epitaxial layer 5;
[0075] A plurality of P-type heavily doped regions 7 are provided, each extending downward from the top surface of the P-Well region 6;
[0076] There are several N-type heavy doping 14, which extend downward from the top surface of the P-Well well region 6 and are connected to the P-type heavy doping 7; N-type heavy doping 14 is provided on both sides of the P-type heavy doping 7 in the middle of the epitaxial layer 5;
[0077] The source electrode metal layer 9 is provided with a source driving system and a gate driving system arranged at intervals;
[0078] The bottom of the source driving system and the bottom of the gate driving system are respectively connected to the corresponding N-type heavily doped 14 , P-Well well region 6 and JFET region 18 , and the tops are respectively wrapped by corresponding passivation layers 10 .
[0079] The source driving system includes a source driving gate oxide layer 15 and a source driving Ploy 16 connected in sequence from bottom to top; the source driving gate oxide layer 15 overlaps with the P-Well well region 6 to form a source driving channel 17 .
[0080] The gate driving system includes a gate driving gate oxide layer 11 and a gate driving Ploy 12 connected in sequence from bottom to top; the gate driving gate oxide layer 11 overlaps with the P-Well well region 6 to form a gate driving channel 13 .
[0081] The source driver Ploy is set on the source driver gate oxide layer, and the overlapping interface with the P-well well area is the source driver channel area. Through dry etching, the gate channel and the source channel are formed at the same time;
[0082] like Fig.12 As shown, the left passivation layer 10 is wrapped around the source driver gate oxide layer 15 and the source driver Ploy 16 ; the right passivation layer 10 is wrapped around the gate driver gate oxide layer 11 and the gate driver Ploy 12 to isolate them from the source metal 9 .
[0083] Regarding the contents disclosed in this case, there are a few points that need to be explained:
[0084] (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design;
[0085] (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments;
[0086] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.
Claims
1. Improve the body diode conduction performance SiC MOSFET structure, characterized in that, It includes, from bottom to top, a drain electrode (1), a substrate (3), an epitaxial layer (5), and a source electrode metal layer (9); The epitaxial layer (5) is provided with: A plurality of P-Well well regions (6) are provided, each extending downward from the top surface of the epitaxial layer (5); A plurality of P-type heavily doped layers (7) are provided, each extending downward from the top surface of the P-Well well region (6); A plurality of N-type heavy doping (14) are provided, each extending downward from the top surface of the P-Well well region (6) and connected to the P-type heavy doping (7); N-type heavy doping (14) is provided on both sides of the P-type heavy doping (7) in the middle of the epitaxial layer (5); the height of the P-type heavy doping (7) is smaller than the height of the N-type heavy doping (14); The source electrode metal layer (9) is provided with a source driving system and a gate driving system which are arranged at intervals; The bottom of the source driving system and the bottom of the gate driving system are respectively connected to the corresponding N-type heavily doped (14), P-Well well region (6) and JFET region (18), and the tops are respectively wrapped by corresponding passivation layers (10).
2. The SiC MOSFET structure for improving body diode conduction performance according to claim 1, characterized in that: The source driving system comprises a source driving gate oxide layer (15) and a source driving Ploy (16) connected in sequence from bottom to top; the source driving gate oxide layer (15) overlaps with the P-Well well region (6) to form a source driving channel (17); The gate driving system comprises a gate driving gate oxide layer (11) and a gate driving Ploy (12) connected in sequence from bottom to top; the gate driving gate oxide layer (11) overlaps with a P-Well well region (6) to form a gate driving channel (13).
3. The SiC MOSFET structure for improving body diode conduction performance according to claim 1, characterized in that: A buffer layer (4) is provided on the upper surface of the substrate (3), and is located between the substrate (3) and the epitaxial layer (5).
4. The SiC MOSFET structure for improving body diode conduction performance according to claim 1, characterized in that: The depth of the P-type heavy doping (7) is 0.3-0.4 um.
5. The SiC MOSFET structure for improving body diode conduction performance according to claim 1, characterized in that: The depth of the N-type heavy doping (14) is 0.2-0.3 um.