Semiconductor device, cellular structure of semiconductor device and mask plate

Abstract

The utility model provides a semiconductor device, a cellular structure of the semiconductor device and a mask plate, the semiconductor device comprises a plurality of cells, at least one of the cells comprises a first control gate part and a second control gate part, the first control gate part and the second control gate part are separated from each other, and the first control gate part and the second control gate part are separated from each other. The first control gate part and the second control gate part are connected through the third control gate part, the first control gate part, the second control gate part and the third control gate part form a control gate, the first control gate part and the second control gate part are located in an active region of the semiconductor device, and the third control gate part is located in a transition region of the semiconductor device. The transition region is located between the active region and a terminal region of the semiconductor device. According to the semiconductor device, the gate-drain capacitance is controlled by controlling the widths of the first control gate part and the second control gate part and the distance between the first control gate part and the second control gate part.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a semiconductor device, a cell structure of the semiconductor device, and a mask. Background Art

[0002] Power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are widely used in power systems due to their superior characteristics. In order to control energy loss during power processing, power MOSFET devices are required to have lower resistance in the on state. The higher the breakdown voltage requirement of high-power systems, the higher the specific on-resistance (R on,sp ) and the breakdown voltage (BV, BreakdownVoltage) are becoming more and more serious. on,sp ∝BV 2.4~2.6 , that is, the specific on-resistance increases exponentially with the increase of breakdown voltage. Traditional power MOSFET devices have a "silicon limit" relationship. Superjunction power MOSFET devices use unique charge compensation technology to form a charge compensation structure using alternating P-type and N-type semiconductor regions, thereby breaking through the so-called silicon limit problem in the field of ordinary power MOSFET devices in the industry and achieving ultra-low specific on-resistance. While increasing the concentration in the drift region, it has an optimized distributed rectangular electric field with full depletion in the off state, and the breakdown voltage remains unchanged.

[0003] The excellent static performance lays the foundation for the application of super-junction power MOSFET devices in high-voltage and low-loss scenarios, making it one of the most widely used technologies in the field of silicon-based high-voltage discrete devices. It is used as a power switch in DC-DC, PFC, LLC and other circuit systems. At the same time, the switch application also puts forward higher requirements on the dynamic characteristics of low-loss super-junction power MOSFET devices. In order to realize the ease of use of super-junction power MOSFET devices in circuits, it is necessary to optimize the capacitance characteristics of super-junction power MOSFET devices, especially the gate-drain capacitance C GD , the capacitance characteristics significantly affect the dynamic performance, such as switching speed and unwanted ringing. Therefore, it is necessary to improve the semiconductor device and mask to improve the gate-drain capacitance C GD . Utility Model Content

[0004] In view of the above problems, the purpose of the present disclosure is to provide a semiconductor device, a cell structure of the semiconductor device and a mask, which controls the gate-drain capacitance by controlling the width of the first control gate part and the second control gate part and the distance therebetween.

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor device, comprising a plurality of cells, wherein at least one cell comprises a first control gate portion and a second control gate portion,

[0006] The first control gate portion and the second control gate portion are separated from each other, the first control gate portion and the second control gate portion are connected via a third control gate portion, and the first control gate portion, the second control gate portion and the third control gate portion constitute a control gate,

[0007] The first control gate portion and the second control gate portion are located in an active region of the semiconductor device, and the third control gate portion is located in a transition region of the semiconductor device.

[0008] The transition region is located between the active region and a termination region of the semiconductor device.

[0009] Optionally, the transition region surrounds the active region, and the termination region surrounds the transition region.

[0010] Optionally, it further includes a control gate lead-out portion located in the transition region,

[0011] Wherein, the third control gate portion is connected to the control gate lead-out portion.

[0012] Optionally, the third control gate portion is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the first control gate portion and the second control gate portion, and the main trunk of the Y-shape is connected to the control gate lead-out portion.

[0013] Optionally, the control gate lead-out portion is located at at least one end of the control gate.

[0014] Optionally, the width of the control gate lead-out portion is greater than the widths of the first control gate portion, the second control gate portion, and the third control gate portion.

[0015] Optionally, the structures of all the cells are the same as the structure of the at least one cell.

[0016] Optionally, the structure of some of the cells is the same as the structure of the at least one cell.

[0017] Optionally, it also includes:

[0018] substrate;

[0019] an epitaxial layer, located on the substrate;

[0020] a plurality of doped columns, the plurality of doped columns are located in the epitaxial layer and are spaced apart from each other;

[0021] A body region, located in the epitaxial layer of the active region and the transition region, the body region extending from the surface of the epitaxial layer toward the substrate, the body region being located on the doped column of the active region and on the doped column at the junction of the active region and the transition region;

[0022] a source region located in the body region;

[0023] a gate dielectric layer, wherein a first portion of the gate dielectric layer is located on the epitaxial layer between two adjacent source regions, and a second portion of the gate dielectric layer extends from the first portion of the gate dielectric layer to a portion of the epitaxial layer in the transition region; and

[0024] a field oxide layer extending from the second portion of the gate dielectric layer to the epitaxial layer of the terminal region,

[0025] The first control gate portion and the second control gate portion are located on the first portion of the gate dielectric layer, the third control gate portion is located on the second portion of the gate dielectric layer, and the control gate lead-out portion is located on a portion of the field oxide layer.

[0026] Optionally, the body region includes a first partial body region and a second partial body region, the first partial body region is located in the active region, the second partial body region extends from the active region to the transition region, the second partial body region surrounds the first partial body region, and the source region is located in the first partial body region;

[0027] The semiconductor device further includes a guard ring located in the epitaxial layer of the transition region, surrounding the second partial body region and connected to the second partial body region.

[0028] Optionally, an orthographic projection of the control gate lead-out portion on the surface of the epitaxial layer is located inside an orthographic projection of the guard ring on the surface of the epitaxial layer.

[0029] Optionally, it also includes:

[0030] a contact region located in the body region;

[0031] An isolation layer, covering the epitaxial layer, the gate dielectric layer, the field oxide layer, the control gate and the control gate lead-out portion;

[0032] a gate electrode, located on the isolation layer and connected to the control gate lead-out portion via a connecting column; and

[0033] The source electrode is located on the isolation layer and is connected to the contact area and the source area via a connecting column.

[0034] Optionally, the substrate, the epitaxial layer and the source region are of a first doping type, the body region, the doped column, the guard ring and the contact region are of a second doping type, and the first doping type is opposite to the second doping type.

[0035] Optionally, the semiconductor device is a metal-oxide semiconductor field effect transistor.

[0036] Optionally, at least a portion of the control gate lead-out portion is connected to at least one of the connection pillars.

[0037] Optionally, the second portion of the body region is electrically connected to the source electrode through the connecting column.

[0038] Optionally, a stop ring is further included, which is located in the epitaxial layer of the terminal region and is separated from the guard ring.

[0039] Optionally, the cutoff ring is of a second doping type.

[0040] Optionally, the epitaxial layer includes:

[0041] A first epitaxial layer is located on the substrate; and

[0042] The second epitaxial layer is located on the first epitaxial layer.

[0043] Optionally, the substrate is any one of a silicon substrate, a silicon carbide substrate, and a gallium nitride substrate.

[0044] Optionally, a drain electrode is further included, and the drain electrode is located on a surface of the substrate away from the epitaxial layer.

[0045] Optionally, the semiconductor device is an insulated gate bipolar transistor, the epitaxial layer and the source region are of a first doping type, the substrate, the body region, the doped column, the guard ring and the contact region are of a second doping type, and the first doping type is opposite to the second doping type.

[0046] According to a second aspect of an embodiment of the present disclosure, a cell structure is provided, comprising a plurality of cells, wherein at least one cell comprises a first control gate portion and a second control gate portion,

[0047] The first control gate portion and the second control gate portion are separated from each other, the first control gate portion and the second control gate portion are connected via a third control gate portion, and the first control gate portion, the second control gate portion and the third control gate portion constitute a control gate of the semiconductor device,

[0048] The first control gate portion and the second control gate portion are located in an active region of the semiconductor device, and the third control gate portion is located in a transition region of the semiconductor device.

[0049] The transition region is located between the active region and a termination region of the semiconductor device.

[0050] Optionally, the transition region surrounds the active region, and the termination region surrounds the transition region.

[0051] Optionally, the semiconductor device further comprises a control gate lead-out portion located in the transition region,

[0052] Wherein, the third control gate portion is connected to the control gate lead-out portion.

[0053] Optionally, the third control gate portion is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the first control gate portion and the second control gate portion, and the main trunk of the Y-shape is connected to the control gate lead-out portion.

[0054] Optionally, the control gate lead-out portion is located at at least one end of the control gate.

[0055] Optionally, the width of the control gate lead-out portion is greater than the widths of the first control gate portion, the second control gate portion, and the third control gate portion.

[0056] Optionally, the structures of all the cells are the same as the structure of the at least one cell.

[0057] Optionally, the structure of some of the cells is the same as the structure of the at least one cell.

[0058] According to a third aspect of the embodiments of the present disclosure, a mask is provided, comprising a plurality of cell patterns, wherein at least one cell pattern comprises a first control gate portion pattern and a second control gate portion pattern,

[0059] The first control gate portion pattern and the second control gate portion pattern are separated from each other, and the first control gate portion pattern and the second control gate portion pattern are connected via a third control gate portion pattern.

[0060] The first control gate portion pattern, the second control gate portion pattern and the third control gate portion pattern constitute a control gate pattern,

[0061] The first control gate partial pattern and the second control gate partial pattern are located in a first region, the third control gate partial pattern is located in a second region, and the second region surrounds the first region.

[0062] Optionally, the mask is used to form the semiconductor device as described above.

[0063] Optionally, the first region corresponds to an active region of the semiconductor device, and the second region corresponds to a transition region of the semiconductor device.

[0064] Optionally, it further includes a control gate lead-out pattern located in the second region,

[0065] Wherein, the third control gate portion pattern is connected to the control gate lead-out portion pattern.

[0066] Optionally, the third control gate partial pattern is in a Y shape, two branches of the Y shape are respectively connected to the ends of the first control gate partial pattern and the second control gate partial pattern, and the main trunk of the Y shape is connected to the control gate lead-out pattern.

[0067] Optionally, the control gate lead-out pattern is located at at least one end of the control gate pattern.

[0068] Optionally, the width of the control gate lead-out pattern is greater than the width of the first control gate portion pattern.

[0069] The width of the second control gate portion pattern and the third control gate portion pattern.

[0070] Optionally, shapes of all the cellular patterns are the same as the shape of the at least one cellular pattern.

[0071] Optionally, the shape of some of the cellular patterns is the same as the shape of the at least one cellular pattern.

[0072] According to the semiconductor device provided by the embodiment of the present disclosure, the first control gate part and the second control gate part are spaced apart from each other, replacing the integral control gate structure of the prior art, so that the area of ​​the entire control gate is reduced, and the projection area of ​​the first control gate part and the second control gate part on the substrate is reduced, thereby reducing the parasitic capacitance C between the control gate and the drain electrode (substrate). GD Reduce.

[0073] The separation distance between the first control gate portion and the second control gate portion reserves space for adjusting the width of each of the first control gate portion and the second control gate portion, thereby reducing the parasitic capacitance C between the overall control gate and the drain electrode. GD Can be adjusted accordingly according to specific needs.

[0074] Furthermore, the first control gate portion located in the active area is connected to the adjacent second control gate portion located in the transition area through the corresponding third control gate portion located in the transition area and the control gate lead-out portion located in the transition area. Compared with the solution in the prior art that provides a separate lead-out portion for the entire control gate, the number of lead-out portions is not increased while the entire control gate area is reduced by utilizing the separated first control gate portion and the second control gate portion.

[0075] Furthermore, the width of the control gate lead-out portion is greater than the widths of the first control gate portion, the second control gate portion, and the third control gate portion to facilitate the potential lead-out of the control gate.

[0076] Furthermore, the third control gate portion and the control gate lead-out portion are arranged on the transition region surrounding the active region, without occupying the space of the active region, thus leaving more space for adjusting the width of the first control gate and the second control gate.

[0077] Furthermore, an impurity doping region surrounding the control gate lead is provided in the epitaxial layer to reduce the influence on the potential distribution at the top of the transition region, which is beneficial to maintaining the breakdown voltage characteristics of the semiconductor device, saves the area of ​​the transition region, and improves the process stability and reliability of the transition region and the terminal region.

[0078] Furthermore, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked from bottom to top, wherein the doping concentration of the second epitaxial layer is less than the doping concentration of the first epitaxial layer. When the drain electrode voltage is low voltage, due to the effect of the second epitaxial layer with a lower doping concentration, the junction field-effect transistor (JFET) region between the body regions can be more easily depleted, thereby adjusting the capacitance curve of the reverse transfer capacitance Crss. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0080] Figure 1 A top view showing a partial structure of a semiconductor device according to an embodiment of the present disclosure.

[0081] Figure 2 Shown along Figure 1 Cross-sectional view taken along line aa.

[0082] Figure 3 Shown along Figure 1 Cross-sectional view taken along line bb.

[0083] Figure 4 Shows Figure 1 Schematic diagram of the structure of the mask template of the control gate structure layer.

[0084] Figure 5 Shows Figure 4 Schematic diagram of the enlarged structure within the dotted box A. DETAILED DESCRIPTION

[0085] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0086] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0087] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0088] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0089] In order to improve the above problems, the present invention provides an improved semiconductor device, a cell structure of the semiconductor device and a mask, so that the first control gate part and the second control gate part are spaced apart from each other, replacing the control gate structure of the prior art, so that the area of ​​the entire control gate is reduced, and the projection area of ​​the first control gate part and the second control gate part on the substrate is reduced, so that the parasitic capacitance C between the control gate and the drain electrode (substrate) is reduced. GD The present disclosure may be presented in various forms, some examples of which will be described below.

[0090] Figure 1 A top view showing a partial structure of a semiconductor device according to an embodiment of the present disclosure is shown. Figure 2 Shown along Figure 1 The cross-section taken along line aa is shown in the figure. Figure 3 Shown along Figure 1 Cross-sectional view taken along line bb.

[0091] The semiconductor device includes a plurality of cells S11, and in this embodiment, the structures of all cells S11 are the same for illustration. It is understandable that in other embodiments, at least one of the plurality of cells of the semiconductor device has the structure of the cell S11 in this embodiment, that is, at least one cell S11 includes a first control gate portion 181 and a second control gate portion 182 of a control gate 180, and the first control gate portion 181 and the second control gate portion 182 are separated from each other. In other embodiments, only some of the cells may have the structure of the cell S11 in this embodiment, and the cells S11 may be arranged at intervals or continuously, and the number of cells S11 may account for 40%, 50%, 80%, 90%, etc., of the total number of cells.

[0092] like Figures 1 to 3 As shown, the semiconductor device of the embodiment of the present disclosure includes: a substrate 101, an epitaxial layer, a plurality of doped pillars 110, a body region 120, a guard ring 130, a stop ring 140, a source region 150, a contact region 160, a gate dielectric layer 170, a field oxide layer 171, a control gate 180, a control gate lead-out portion 210, an isolation layer 104, a connecting pillar 105, a gate electrode 230, and a source electrode 240. The substrate 101, the epitaxial layer, and the source region 150 are of a first doping type, and the doped pillars 110, the body region 120, the guard ring 130, the stop ring 140, and the contact region 160 are of a second doping type, wherein the first doping type is selected from one of P-type and N-type, and the second doping type is selected from the other of P-type and N-type.

[0093] In this embodiment, the semiconductor device includes: an active area S1, a transition area S2 and a terminal area S3, wherein the transition area S2 surrounds the active area S1, and the terminal area S3 surrounds the transition area S2. The active area S1 is the working area of ​​all cells, the terminal area S3 is the area for alleviating the edge electric field concentration and expanding the electric field, and the transition area S2 is a part used to connect the active area S1 and the terminal area S3.

[0094] Optionally, the substrate 101 is any one of a silicon substrate, a silicon carbide substrate, and a gallium nitride substrate, but is not limited thereto.

[0095] The epitaxial layer includes a first epitaxial layer 102 and a second epitaxial layer 103, wherein the first epitaxial layer 102 is located on the substrate 101, and the second epitaxial layer 103 is located on the first epitaxial layer 102. Specifically, the thickness of the second epitaxial layer 103 is less than the thickness of the first epitaxial layer 102. In some specific embodiments, the doping concentration of the second epitaxial layer 103 is less than the doping concentration of the first epitaxial layer 102. Of course, the doping concentration of the second epitaxial layer 103 may also be greater than the doping concentration of the first epitaxial layer 102; the epitaxial layer may also include only the first epitaxial layer 102.

[0096] A plurality of doped columns 110 are located in the epitaxial layer of the active region S1, the transition region S2, and the terminal region S3 and are spaced from each other. The plurality of doped columns 110 extend from the surface of the epitaxial layer toward the substrate 101. The plurality of doped columns 110 extend along a first direction (Y-axis direction) and are spaced apart along a second direction (X-axis direction). The widths of the plurality of doped columns 110 may be the same or different, and the spacings between adjacent doped columns 110 may be the same or different.

[0097] The body region 120 is located in the epitaxial layer, extending from the surface of the epitaxial layer toward the substrate 101, and includes a first partial body region and a second partial body region, wherein the first partial body region is located in the active region S1, and the second partial body region extends from the active region S1 to the transition region S2, and the second partial body region surrounds the first partial body region. Specifically, the first partial body regions extend along the first direction (Y-axis direction) and are arranged at intervals along the second direction (X-axis direction), wherein the first direction, the second direction, and the thickness direction of the substrate 101 are perpendicular to each other.

[0098] The guard ring 130 is located in the epitaxial layer in the transition region S2, specifically in the second epitaxial layer 103. The guard ring 130 surrounds the second partial body region and is connected to the second partial body region.

[0099] Specifically, the first part of the body region is located on the doped column 110 of the active region S1, and the second part of the body region is located on the doped column 110 at the junction of the active region S1 and the transition region S2. The guard ring 130 is located on part of the doped column 110 of the transition region S2.

[0100] The stop ring 140 is located in the epitaxial layer of the termination region S3, specifically in the second epitaxial layer 103. The stop ring 140 surrounds the guard ring 130 and is separated from the guard ring 130.

[0101] The contact region 160 and the source region 150 are located in the first portion of the body region. Preferably, the contact region 160 is located between and adjacent to the two source regions 150, but is not limited thereto. The contact region 160 is also located in the second portion of the body region.

[0102] The gate dielectric layer 170 is located on the surface of a portion of the epitaxial layer (the second epitaxial layer 103 ). Specifically, a first portion of the gate dielectric layer 170 is located on the epitaxial layer between two adjacent source regions 150 , and a second portion of the gate dielectric layer 170 extends from the first portion of the gate dielectric layer 170 to a portion of the epitaxial layer (the second epitaxial layer 103 ) in the transition region S2 .

[0103] The field oxide layer 171 extends from the second portion of the gate dielectric layer 170 to the epitaxial layer (the second epitaxial layer 103 ) of the terminal region S3 .

[0104] The control gate 180 is located on the gate dielectric layer 170, and the control gate lead-out portion 210 is located on a portion of the field oxide layer 171. Specifically, the material of the control gate 180 and the control gate lead-out portion 210 includes polysilicon.

[0105] In a specific embodiment, each control gate 180 includes a first control gate portion 181, a second control gate portion 182, and a third control gate portion 183, wherein the first control gate portion 181 and the second control gate portion 182 are located on the first portion of the gate dielectric layer 170 and extend along the first direction, and the first control gate portion 181 is arranged in parallel with the second control gate portion 182, and the third control gate portion 183 is located on the second portion of the gate dielectric layer 170, and the first control gate portion 181 and the second control gate portion 182 are connected through the third control gate portion 183. The first control gate portion 181 and the second control gate portion 182 are both located in the active region S1 and are separated from each other.

[0106] In some other embodiments, the first control gate portion 181 and the second control gate portion 182 may also be arranged in an S-shape or other shapes.

[0107] Optionally, each third control gate portion 183 is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the corresponding first control gate portion 181 and the second control gate portion 182 , and the main trunk of the Y-shape is connected to the corresponding control gate lead-out portion 210 .

[0108] In another specific embodiment, the control gate 180 near one side edge of the active area S1 includes only a first control gate portion 181 and a third control gate portion 183, the third control gate portion 183 is in a semi-Y shape, the branch of the semi-Y shape is connected to the first control gate portion 181, and the main trunk of the semi-Y shape is connected to the corresponding control gate lead-out portion 210; the control gate 180 near the other side edge of the active area S1 includes only a second control gate portion 182 and a third control gate portion 183, the third control gate portion 183 is in a semi-Y shape, the branch of the semi-Y shape is connected to the second control gate portion 182, and the main trunk of the semi-Y shape is connected to the corresponding control gate lead-out portion 210.

[0109] The control gate lead-out portion 210 is located at at least one end of the control gate 180. The plurality of third control gate portions 183 are separated from each other, and the plurality of control gate lead-out portions 210 are separated from each other.

[0110] Specifically, the plurality of control gate lead-out portions 210 located at the same side of the active region S1 are aligned along the first direction, but the present invention is not limited thereto.

[0111] Specifically, the width W1 of the control gate lead-out portion 210 is greater than the width W2 of the first control gate portion 181 , the second control gate portion 182 , and the third control gate portion 183 .

[0112] Specifically, the spacings between adjacent first control gate portions 181 and second control gate portions 182 are the same. Of course, the spacings between adjacent first control gate portions 181 and second control gate portions 182 may also be different or the same.

[0113] Specifically, the shape of the control gate lead-out portion 210 may be a rectangle, a circle, an ellipse, a polygon, etc., wherein the rectangle may be provided with chamfers or rounded corners.

[0114] Specifically, the orthographic projection of the control gate lead-out portion 210 on the surface of the epitaxial layer (the second epitaxial layer 103 ) is located inside the orthographic projection of the guard ring 130 on the surface of the epitaxial layer (the second epitaxial layer 103 ).

[0115] An impurity doped region surrounding the control gate lead-out portion 210 is arranged in the second epitaxial layer 103, and the impurity doped region includes a second partial body region and a guard ring 130. The edge of the control gate lead-out portion 210 does not exceed the second partial body region and the guard ring 130, thereby reducing the influence on the potential distribution at the top of the transition region S2, which is beneficial to maintaining the breakdown voltage characteristics of the semiconductor device and improving the process stability and reliability of the transition region S2 and the terminal region S3.

[0116] The isolation layer 104 covers the epitaxial layer (the second epitaxial layer 103 ), the gate dielectric layer 170 , the field oxide layer 171 , the control gate 180 , and the control gate lead-out portion 210 .

[0117] The gate electrode 230 and the source electrode 240 are located on the isolation layer 104 , wherein the gate electrode 230 is connected to the control gate lead-out portion 210 via the connection column 105 . The source electrode 240 is connected to the source region 150 and the contact region 160 via the connection column 105 .

[0118] Optionally, at least a portion of the control gate lead-out portion 210 is connected to at least one connection pillar 105 .

[0119] Optionally, the substrate 101 serves as a drain electrode.

[0120] Optionally, a metal layer (not shown) is formed on a surface of the substrate 101 away from the epitaxial layer as a drain electrode.

[0121] The semiconductor device in this embodiment is, for example, a metal-oxide semiconductor field effect transistor (MOSFET). In some other embodiments, the doping types of the substrate 101 and the epitaxial layer are opposite, that is, the substrate 101 is the second doping type and the epitaxial layer is the first doping type, forming an insulated gate bipolar transistor (IGBT).

[0122] Figure 4 Shows Figure 1A schematic diagram of the structure of the mask template of the control gate structure layer in the middle. Figure 5 Shows Figure 4 Schematic diagram of the enlarged structure within the dotted box A.

[0123] The mask plate includes a plurality of cell patterns. In this embodiment, the shapes of all the cell patterns are the same for illustration, that is, the mask plate in this embodiment is used to form the control gate structure layer (including the control gate and the control gate lead-out portion) in the aforementioned semiconductor device. It can be understood that in other embodiments, the shape of at least one cell pattern among the plurality of cell patterns of the mask plate is the shape of the cell pattern in this embodiment, that is, at least one cell pattern includes a first control gate portion pattern 311 and a second control gate portion pattern 312 of a control gate pattern 310, and the first control gate portion pattern 311 and the second control gate portion pattern 312 are separated from each other. In other embodiments, only some of the cell patterns may have the shape of the cell pattern in this embodiment, and these cell patterns may be arranged at intervals or continuously, and the proportion of the number of these cell patterns to the number of all cell patterns is, for example, 40%, 50%, 80%, 90%, etc.

[0124] like Figures 4 to 5 As shown, the mask plate 300 of the control gate structure layer of the semiconductor device of the embodiment of the present disclosure includes: a control gate pattern 310 and a control gate lead-out portion pattern 330. The control gate 180 of the semiconductor device is formed by the control gate pattern 310, and the control gate lead-out portion 210 of the semiconductor device is formed by the control gate lead-out portion pattern 330.

[0125] The control gate pattern 310 includes a first control gate portion pattern 311, a second control gate portion pattern 312, and a third control gate portion pattern 313. The first control gate portion pattern 311 and the second control gate portion pattern 312 are located in the first region. The first control gate portion pattern 311 and the second control gate portion pattern 312 extend along a first direction and are separated from each other, and the first control gate portion pattern 311 is arranged in parallel with the second control gate portion pattern 312. The third control gate portion pattern 313 is located in the second region, and the first control gate portion pattern 311 and the second control gate portion pattern 312 are connected through the third control gate portion pattern 313. The second region surrounds the first region, the first region corresponds to the active region S1 of the semiconductor device, and the second region corresponds to the transition region S2 of the semiconductor device.

[0126] In some other embodiments, the first control gate partial pattern 311 and the second control gate partial pattern 312 may also be arranged in an S-shape or other shapes.

[0127] The control gate lead-out pattern 330 is located in the second region, and the third control gate portion pattern 313 is connected to the control gate lead-out pattern 330 , wherein a plurality of third control gate portion patterns 313 are separated from each other, and a plurality of control gate lead-out patterns 330 are separated from each other.

[0128] In a specific embodiment, each third control gate partial pattern 313 is Y-shaped, and the two branches 313a and 313b of the Y-shape are respectively connected to the ends of the corresponding first control gate partial pattern 311 and the second control gate partial pattern 312, and the Y-shaped trunk 313c is connected to the corresponding control gate lead-out pattern 330.

[0129] In another specific embodiment, the control gate pattern 310 near the edge of one side of the first region only includes the first control gate partial pattern 311 and the third control gate partial pattern 313, the third control gate partial pattern 313 is in a half-Y shape, the branch of the half-Y shape is connected to the first control gate partial pattern 311, and the trunk of the half-Y shape is connected to the corresponding control gate lead-out portion pattern 330. The control gate pattern 310 near the edge of the other side of the first region only includes the second control gate partial pattern 312 and the third control gate partial pattern 313, the third control gate partial pattern 313 is in a half-Y shape, the branch of the half-Y shape is connected to the second control gate partial pattern 312, and the trunk of the half-Y shape is connected to the corresponding control gate lead-out portion 330.

[0130] The control gate lead-out pattern 330 is located at at least one end of the control gate pattern 310 along the first direction.

[0131] Specifically, the width W1 of the control gate lead-out portion pattern 330 is greater than the width W2 of the first control gate portion pattern 311 , the second control gate portion pattern 312 , and the third control gate portion pattern 313 .

[0132] Specifically, a plurality of control gate lead-out patterns 330 located at the same side of the first region are aligned along the first direction, but the present invention is not limited thereto.

[0133] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The semiconductor device includes a plurality of cells, wherein at least one cell includes a first control gate portion and a second control gate portion, The first control gate portion and the second control gate portion are separated from each other, the first control gate portion and the second control gate portion are connected via a third control gate portion, and the first control gate portion, the second control gate portion and the third control gate portion constitute a control gate, The first control gate portion and the second control gate portion are located in an active region of the semiconductor device, and the third control gate portion is located in a transition region of the semiconductor device. The transition region is located between the active region and a termination region of the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The transition region surrounds the active region, and the termination region surrounds the transition region.

3. The semiconductor device according to claim 2, characterized in that It also includes a control gate lead-out portion located in the transition region, Wherein, the third control gate portion is connected to the control gate lead-out portion.

4. The semiconductor device according to claim 3, characterized in that The third control gate portion is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the first control gate portion and the second control gate portion, and the main trunk of the Y-shape is connected to the control gate lead-out portion.

5. The semiconductor device according to claim 3, characterized in that The control gate lead-out portion is located at at least one end of the control gate.

6. The semiconductor device according to claim 3, characterized in that The width of the control gate lead-out portion is greater than the widths of the first control gate portion, the second control gate portion, and the third control gate portion.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The structures of all the cells are the same as the structure of the at least one cell.

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The structure of some of the cells is the same as the structure of the at least one cell.

9. The semiconductor device according to any one of claims 3 to 6, characterized in that: Also includes: substrate; an epitaxial layer, located on the substrate; a plurality of doped columns, the plurality of doped columns are located in the epitaxial layer and are spaced apart from each other; A body region, located in the epitaxial layer of the active region and the transition region, the body region extending from the surface of the epitaxial layer toward the substrate, the body region being located on the doped column of the active region and on the doped column at the junction of the active region and the transition region; a source region located in the body region; a gate dielectric layer, wherein a first portion of the gate dielectric layer is located on the epitaxial layer between two adjacent source regions, and a second portion of the gate dielectric layer extends from the first portion of the gate dielectric layer to a portion of the epitaxial layer in the transition region; as well as a field oxide layer extending from the second portion of the gate dielectric layer to the epitaxial layer of the terminal region, The first control gate portion and the second control gate portion are located on the first portion of the gate dielectric layer, the third control gate portion is located on the second portion of the gate dielectric layer, and the control gate lead-out portion is located on a portion of the field oxide layer.

10. The semiconductor device according to claim 9, characterized in that The body region includes a first partial body region and a second partial body region, the first partial body region is located in the active region, the second partial body region extends from the active region to the transition region, the second partial body region surrounds the first partial body region, and the source region is located in the first partial body region; The semiconductor device further includes a guard ring located in the epitaxial layer of the transition region, surrounding the second partial body region and connected to the second partial body region.

11. The semiconductor device according to claim 10, characterized in that An orthographic projection of the control gate lead portion on the surface of the epitaxial layer is located inside an orthographic projection of the guard ring on the surface of the epitaxial layer.

12. The semiconductor device according to claim 10, characterized in that Also includes: a contact region located in the body region; An isolation layer, covering the epitaxial layer, the gate dielectric layer, the field oxide layer, the control gate and the control gate lead-out portion; a gate electrode, located on the isolation layer and connected to the control gate lead-out portion via a connecting column; and The source electrode is located on the isolation layer and is connected to the contact area and the source area via a connecting column.

13. The semiconductor device according to claim 12, characterized in that The substrate, the epitaxial layer and the source region are of a first doping type, the body region, the doped column, the guard ring and the contact region are of a second doping type, and the first doping type is opposite to the second doping type.

14. The semiconductor device according to claim 13, characterized in that The semiconductor device is a metal-oxide semiconductor field effect transistor.

15. The semiconductor device according to claim 12, characterized in that At least a portion of the control gate lead-out portion is connected to at least one of the connection pillars.

16. The semiconductor device according to claim 12, wherein: The second portion of the body region is electrically connected to the source electrode through the connection column.

17. The semiconductor device according to claim 12, characterized in that A stop ring is also included, which is located in the epitaxial layer in the termination region and is separated from the guard ring.

18. The semiconductor device according to claim 17, wherein: The cut-off ring is of the second doping type.

19. The semiconductor device according to claim 9, characterized in that The epitaxial layer comprises: A first epitaxial layer is located on the substrate; and The second epitaxial layer is located on the first epitaxial layer.

20. The semiconductor device according to claim 9, characterized in that The substrate is any one of a silicon substrate, a silicon carbide substrate and a gallium nitride substrate.

21. The semiconductor device according to claim 12, characterized in that It also includes a drain electrode, which is located on a surface of the substrate away from the epitaxial layer.

22. The semiconductor device according to claim 12, wherein: The semiconductor device is an insulated gate bipolar transistor, the epitaxial layer and the source region are of a first doping type, the substrate, the body region, the doped column, the guard ring and the contact region are of a second doping type, and the first doping type is opposite to the second doping type.

23. A cell structure of a semiconductor device, characterized in that: The cell structure includes a plurality of cells, wherein at least one cell includes a first control gate portion and a second control gate portion, The first control gate portion and the second control gate portion are separated from each other, the first control gate portion and the second control gate portion are connected via a third control gate portion, and the first control gate portion, the second control gate portion and the third control gate portion constitute a control gate of the semiconductor device, The first control gate portion and the second control gate portion are located in an active region of the semiconductor device, and the third control gate portion is located in a transition region of the semiconductor device. The transition region is located between the active region and a termination region of the semiconductor device.

24. The cellular structure according to claim 23, characterized in that: The transition region surrounds the active region, and the termination region surrounds the transition region.

25. The cellular structure according to claim 24, characterized in that: The semiconductor device further comprises a control gate lead-out portion located in the transition region. Wherein, the third control gate portion is connected to the control gate lead-out portion.

26. The cellular structure according to claim 25, characterized in that: The third control gate portion is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the first control gate portion and the second control gate portion, and the main trunk of the Y-shape is connected to the control gate lead-out portion.

27. The cellular structure according to claim 25, characterized in that: The control gate lead-out portion is located at at least one end of the control gate.

28. The cellular structure according to claim 25, characterized in that: The width of the control gate lead-out portion is greater than the widths of the first control gate portion, the second control gate portion, and the third control gate portion.

29. The cellular structure according to any one of claims 23 to 28, characterized in that: The structures of all the cells are the same as the structure of the at least one cell.

30. The cellular structure according to any one of claims 23 to 28, characterized in that: The structure of some of the cells is the same as the structure of the at least one cell.

31. A mask, characterized in that: The mask includes a plurality of cell patterns, wherein at least one cell pattern includes a first control gate portion pattern and a second control gate portion pattern. The first control gate portion pattern and the second control gate portion pattern are separated from each other, and the first control gate portion pattern and the second control gate portion pattern are connected via a third control gate portion pattern. The first control gate portion pattern, the second control gate portion pattern and the third control gate portion pattern constitute a control gate pattern, The first control gate partial pattern and the second control gate partial pattern are located in a first region, the third control gate partial pattern is located in a second region, and the second region surrounds the first region.

32. The mask according to claim 31, characterized in that: The mask is used to form the semiconductor device according to any one of claims 1 to 22.

33. The mask according to claim 32, characterized in that: The first region corresponds to an active region of the semiconductor device, and the second region corresponds to a transition region of the semiconductor device.

34. The mask according to claim 33, characterized in that: It also includes a control gate lead-out pattern located in the second region, Wherein, the third control gate portion pattern is connected to the control gate lead-out portion pattern.

35. The mask according to claim 34, characterized in that: The third control gate partial pattern is Y-shaped, two branches of the Y-shape are respectively connected to the ends of the first control gate partial pattern and the second control gate partial pattern, and the main trunk of the Y-shape is connected to the control gate lead-out portion pattern.

36. The mask according to claim 34, characterized in that: The control gate lead-out pattern is located at at least one end of the control gate pattern.

37. The mask according to claim 34, characterized in that: The width of the control gate lead-out pattern is greater than the widths of the first control gate portion pattern, the second control gate portion pattern, and the third control gate portion pattern.

38. The mask according to claim 31, characterized in that: The shapes of all the cellular patterns are the same as the shape of the at least one cellular pattern.

39. The mask according to claim 31, characterized in that: The shape of some of the cellular patterns is the same as the shape of the at least one cellular pattern.

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