Vertically-conducted gallium nitride MOS (Metal Oxide Semiconductor) chip
By setting through holes in the gallium nitride MOS chip and filling the metal leads out the drain to the bottom surface, the problem of large drain occupancy is solved, a larger conduction area and a smaller chip size are achieved, and the chip performance is improved and efficiency.
Patent Information
- Application Number
- CN202421044286.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-14
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-05-14
AI Technical Summary
In existing gallium nitride MOS chips, the drain occupies a large chip area, resulting in a small effective conduction area, which limits the chip size and power performance.
By providing through holes on the substrate and filling metal, the drain electrode is introduced to the bottom surface of the chip, thereby reducing the area occupied by the drain electrode and achieving vertical conduction.
It effectively increases the conduction area of the chip, making the gallium nitride MOS chip area smaller with the same power, and improves the performance and efficiency of the chip.
Smart Images
Figure CN222365593U_ABST
Abstract
Description
Technical Field
[0001] The invention discloses a vertically conductive gallium nitride MOS chip, belonging to the technical field of semiconductors. Background Art
[0002] Gallium nitride belongs to the third generation of semiconductor materials. Compared with silicon, gallium nitride has a wider gap and better conductivity. As gallium nitride technology continues to mature, more and more semiconductor devices are beginning to use gallium nitride. Among them, MOS tubes, as the most common switching devices, are also gradually beginning to use gallium nitride. In the existing technology, there are two types of gallium nitride MOS chips:
[0003] (1) One is as follows Fig.11 The AlGaN / GaN HEMT device with planar conduction shown in FIG. AlGaN / GaN HEMT is a representative of GaN-based devices. Currently, the mainstream AlGaN / GaN HEMTs are all grown along the Ga surface. An oxide layer 17 is provided in the chip, and a passivation layer 18 is provided on the top. The drain 15 and the source 2 are led out from the passivation layer 18. Because the bandgap widths of AlGaN and GaN materials are different, the bandgap width of AlGaN is higher than that of GaN, so that there is a band step difference at the bottom of the conduction band of the two. This band step difference of the conduction band plus the large amount of positive charges at the interface analyzed above will cause the energy band of the conduction band to bend. The energy band bending forms a two-dimensional potential well at the heterojunction interface.
[0004] When the gate voltage bias of the AlGaN / GaN HEMT device is large during operation, the energy band of the AlGaN barrier is pulled down, and the 2DEG at the heterojunction interface will directly cross the barrier and move into the AlGaN barrier layer through tunneling or thermal excitation. For lateral GaN transistors, in order to obtain a higher breakdown voltage, a longer gate-to-drain distance is required, which increases the device size and reduces the on-state current density. In addition, when the gate-to-drain distance reaches a certain value, the breakdown voltage is mainly limited by the buffer leakage current, thereby limiting the breakdown voltage rating of the lateral GaN power transistor.
[0005] (2) Another is Fig.12 The semi-vertical GaN MOS chip shown has a similar mechanism and device structure to the silicon-based MOS in the surface structure of the chip. A deep trench 16 is provided around the cell until the high-concentration GaN epitaxy is formed so that the current flows from the chip surface drain through the deep trench 16 into the high-concentration GaN epitaxial layer, and then flows out from the source on the chip surface after passing through the low-concentration GaN epitaxial layer and the MOS structure of the epitaxial layer. In Si vertical trench MOS chips, the P-type layer and the top N+ contact layer are usually formed by injection. For GaN vertical trench MOSFET, its P-type layer (drain) and the top N+ contact layer (source) are usually formed by epitaxial growth.
[0006] Therefore, the drain and gate of the above two types of gallium nitride MOS tubes in the prior art are both led out from the surface of the chip, so the chip drain occupies part of the chip area, reducing the effective conduction area of the chip, and the chip itself will have a larger area for chips with the same conductive area. Utility Model Content
[0007] The technical problem to be solved by the utility model is: to overcome the shortcomings of the prior art and provide a through hole that penetrates the substrate and the buffer layer, fills the through hole with metal and leads out the drain, so that the drain is arranged at the bottom surface of the chip, thereby reducing the problem that the drain occupies the chip area in the prior art gallium nitride MOS chip, so that the effective conduction area of the chip is small, and the conduction area of the chip can be effectively increased to make a vertically conductive gallium nitride MOS chip with a smaller chip area of the same power.
[0008] The technical solution adopted by the utility model to solve the technical problem is: the vertically conductive gallium nitride MOS chip comprises a substrate made of gallium nitride material, a drift region, a base region and a source region made of gallium nitride material are sequentially arranged above the substrate, an insulating layer is arranged above the source region, a groove is arranged, the groove passes through the base region, the source region and enters the drift region, a MOS structure is formed by filling in the groove, contact holes are arranged between adjacent grooves, the contact holes pass through the insulating layer, the source region and extend to the base region, and the utility model is characterized in that: the drift region comprises a buffer layer and an epitaxial layer, a through hole is arranged passing through the substrate and the buffer layer, the through hole extends to the epitaxial layer, a filling metal layer is filled in the through hole, and a drain is led out from the filling metal layer.
[0009] Preferably, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located below the base region, and the second epitaxial layer is located above the buffer layer.
[0010] Preferably, the first epitaxial layer is an N-type lightly doped gallium nitride epitaxial layer, the second epitaxial layer is an N+ type heavily doped gallium nitride epitaxial layer, and the buffer zone is an i-GaN type buffer zone.
[0011] Preferably, the base region is a P+GaN region, and the source region is an N+GaN region.
[0012] Preferably, a top metal layer is provided at the insulating layer, the top metal layer is connected to the contact hole and leads to the source electrode.
[0013] Preferably, a bottom metal layer is provided at the bottom of the substrate, the bottom metal layer is connected to the filling metal layer, and the drain electrode is led out from the bottom metal layer.
[0014] Compared with the prior art, the utility model has the following beneficial effects:
[0015] In the vertically conductive gallium nitride MOS chip, the drain of the chip is set at the bottom layer, so that the current is conducted in the vertical direction, which reduces the problem that the drain occupies the chip area in the prior art gallium nitride MOS chip, resulting in a small effective conduction area of the chip. The conduction area of the chip can be effectively increased to make the chip area smaller with the same power. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 Schematic diagram of the vertically conductive gallium nitride MOS chip structure.
[0017] Figures 2~10 Schematic diagram of the manufacturing process of vertically conductive gallium nitride MOS chip.
[0018] Fig.11 It is a schematic diagram of the structure of a planar gallium nitride MOS chip in the prior art.
[0019] Fig.12 It is a schematic diagram of the structure of a semi-vertical gallium nitride MOS chip in the prior art.
[0020] Among them: 1, gate 2, source 3, top metal layer 4, trench 5, contact hole 6, insulating layer 7, N+GaN region 8, P+GaN region 9, first epitaxial layer 10, second epitaxial layer 11, buffer layer 12, substrate 13, filling metal layer 14, bottom metal layer 15, drain 16, deep trench 17, oxide layer 18, passivation layer. DETAILED DESCRIPTION
[0021] Figures 1 to 10 It is the best embodiment of the utility model, and the following Figures 1 to 10 The utility model is further described.
[0022] like Figure 1 As shown, a vertically conductive gallium nitride MOS chip includes a substrate 12, and a buffer layer 11, a second epitaxial layer 10, a first epitaxial layer 9, a P+GaN region 8, and an N+GaN region 7 are sequentially arranged on the upper end of the substrate 12. A groove 4 is opened on the surface of the N+GaN region 7, and an insulating layer 6 is arranged on the inner wall of the groove 4 and the surface of the N+GaN region 7.
[0023] A contact hole 5 is provided between any two adjacent trenches 4, and a conductor is filled in the contact hole 5. The contact hole 5 penetrates downward through the insulating layer 6 and the N+GaN region 7 and extends to the P+GaN region 8. A top metal layer 3 is provided on the upper surface of the insulating layer 6, and the upper surface of the conductor filled in the contact hole 5 is connected to the top metal layer 3, and the lower surface of the conductor is connected to the P+GaN region 8. The top metal layer 3, the insulating layer 6, the N+GaN region 7, and the P+GaN region 8 form the MOS structure of the vertically conductive gallium nitride MOS chip.
[0024] The trench 4 is filled, and the gate 1 of the MOS structure is led out from the filling position in the trench 4, and the source 2 and the drain 15 of the MOS structure are led out from the top metal layer 3 and the bottom metal layer, respectively. A plurality of through holes are formed at intervals on the top of the bottom metal layer 14, and the through holes are filled with a filling metal layer 13. After the filling metal layer 13 passes through the substrate 12 and the buffer layer 11 upward, the top of the filling metal layer 13 is connected to the second epitaxial layer 10, and the bottom of the filling metal layer 13 is connected to the bottom metal layer 14.
[0025] The specific working process and working principle are as follows:
[0026] When the MOS chip is in use, that is, the positive electrode of the external power supply is connected to the drain 15, and the negative electrode of the external power supply is connected to the source 2. When the voltage between the gate 1 and the source 2 is less than the start-up voltage of the MOS chip, the MOS chip is not turned on. At this time, the PN junction formed between the N+GaN region 7 and the P+GaN region 8 is reversely cut off, so there is no current flow in the MOS chip. When the voltage value of the forward voltage is greater than the start-up voltage of the MOS chip, a conductive channel is formed in the MOS structure. At this time, the current flows out from the source 2 through the conductive channel after passing through the filling metal layer 13, the second epitaxial layer 10, and the first epitaxial layer 9.
[0027] Therefore, through the vertically conductive gallium nitride MOS chip, the drain of the chip is set at the bottom layer, so that the current is conducted in the vertical direction, which reduces the problem that the drain occupies the chip area in the gallium nitride MOS chip in the prior art, so that the effective conduction area of the chip is small. The conduction area of the chip can be effectively increased to make the chip area smaller with the same power.
[0028] Manufacturing Figure 1 The vertically conductive gallium nitride MOS chip shown includes Figures 2~10 The following steps are shown:
[0029] Step 1, one-time deposition. A GaN structure of n+-p+-n--n+ of a vertical trench MOSFET is grown on a silicon or sapphire substrate 12 using metal organic chemical vapor deposition (MOCVD) technology, such as Figure 2 shown.
[0030] Take the 650V GaN MOSFET as an example: from bottom to top, the i-GaN buffer layer 11, the N+GaN second epitaxial layer 10 (N+ heavily doped silicon nitride epitaxial layer), the 3μm thick N-GaN first epitaxial layer 9, the 400nm thick P+GaN region 8 and the 200nm thick N+GaN region 7 are formed in sequence.
[0031] Step 2, one-step etching.2 / bcl 3 The trench 4 is formed by dry etching. Figure 3 shown.
[0032] Step 3: Secondary deposition: Atomic layer deposition (ALD) is used to prepare a 50 nm Al 2 O 3 Insulation materials, such as Figure 4 shown.
[0033] Step 4: trench filling. Sputter a Ti / Al metal layer and etch it onto the chip surface as a gate trench filling, and lead it out from the chip edge to the gate area on the chip surface, such as Figure 5 shown.
[0034] Step 5, three depositions. Using atomic layer deposition (ALD), 50-100nm Al is deposited on the surface of N+GaN region 7. 2 O 3 of insulating material, and forming an insulating layer 6, such as Figure 6 shown.
[0035] Step 6, secondary etching. Use SiO2 hard mask for ICP etching to form a contact hole 5 with the surface contacting the N+GaN region 7 and the bottom overetching the P+GaN region 8 by about 50 nm. Use buffered oxide etching (BOE) to remove the SiO2 etching mask, as shown in Figure 7 shown.
[0036] Step 7: Annealing and activation. After the contact hole 5 is formed, the buried P+GaN region 8 is annealed at 800°C. 2 The samples were activated by rapid thermal annealing (RTA) in ambient temperature for 10 min.
[0037] Step 8. Four times of deposition. A Ni / Au metal stack is deposited in the contact hole 5 and annealed. Figure 8 shown.
[0038] Step 9. Five depositions. Deposit a Ti / Al / Ni / Au metal stack as ohmic contacts for the source 2 and the gate 1 to form a top metal layer 3, such as Fig. 9 shown.
[0039] Step 10: Deposit a passivation layer six times, and remove the passivation layer of the source 2 and the gate 1 by photolithography to expose the metal of the source 2 and the gate 1.
[0040] Step 11. Back filling. The back of the chip is perforated through the substrate 12 of silicon or sapphire material, the buffer layer 11 to the bottom of the second epitaxial layer 10, to form a through hole, and the back through hole is filled with conductive metal and polished to form a filling metal layer 13, such as Fig.10 shown.
[0041] Step 12: Forming the bottom metal layer 14. Finally, making the back metal of the chip such as aluminum, titanium, nickel, or silver to complete the chip manufacturing.
[0042] The above is only the preferred embodiment of the utility model, and does not limit the utility model in other forms. Any technician familiar with the profession may use the technical content disclosed above to change or modify it into an equivalent embodiment with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiment based on the technical essence of the utility model without departing from the technical solution of the utility model still belongs to the protection scope of the technical solution of the utility model.
Claims
1. A vertically conductive gallium nitride MOS chip, comprising a gallium nitride substrate (12), a drift region, a base region and a source region made of gallium nitride arranged in sequence above the substrate (12), an insulating layer (6) arranged above the source region, a groove (4) arranged on the surface of the source region, the groove (4) passing through the source region, the base region and entering the drift region, the groove (4) being filled to form a MOS structure, a contact hole (5) being arranged between adjacent grooves (4), the contact hole passing through the insulating layer (6), the source region and extending to the base region, characterized in that: The base region is a P+GaN region (8), the source region is an N+GaN region (7), the drift region includes a buffer layer (11) and an epitaxial layer, a through hole penetrating the substrate (12) and the buffer layer (11) is provided, the through hole extends to the epitaxial layer, a filling metal layer (13) is filled in the through hole, and a drain (15) is led out from the filling metal layer (13).
2. The vertically conductive gallium nitride MOS chip according to claim 1, characterized in that: The epitaxial layer comprises a first epitaxial layer (9) and a second epitaxial layer (10), wherein the first epitaxial layer (9) is located below the base region, and the second epitaxial layer (10) is located above the buffer layer.
3. The vertically conductive gallium nitride MOS chip according to claim 2, characterized in that: The first epitaxial layer (9) is an N-type lightly doped gallium nitride epitaxial layer, the second epitaxial layer (10) is an N+ type heavily doped gallium nitride epitaxial layer, and the buffer layer (11) is an i-GaN type buffer zone.
4. The vertically conductive GaN MOS chip according to claim 1, characterized in that: A top metal layer (3) is provided at the insulating layer (6); the top metal layer (3) is connected to the contact hole (5) and leads to the source electrode (2).
5. The vertically conductive GaN MOS chip according to claim 1, characterized in that: A bottom metal layer (14) is arranged at the bottom of the substrate, the bottom metal layer (14) is connected to the filling metal layer (13), and a drain electrode (15) is led out from the bottom metal layer (14).