Circuit for reducing system energy consumption
By introducing pull-down resistors and buffer units between the MCU and the chipset unit, the leakage problem of SPI interface in an uncertain state is solved, effective power supply cutoff and leakage current are achieved, and battery life is extended.
Patent Information
- Application Number
- CN202420816659.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-18
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2034-04-18
AI Technical Summary
In complex business scenarios, when the MCU and the chip interact through the SPI interface, SPI enable is in an uncertain state, resulting in leakage power consumption, affecting battery life.
Design a circuit to reduce the energy power consumption of the system, including the processor MCU, chipset unit, power supply unit and pull-down unit, and isolate the SPI output node by pull-down resistor R1 and buffer unit (composed of two-stage inverters) to ensure that the power supply is It is effectively cut off when not in use to reduce leakage current.
Effectively eliminate leakage power consumption, extend battery life, and achieve ultra-low power consumption of the system.
Smart Images
Figure CN222366264U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the field of low-power consumption technology improvement of electronic circuits, and in particular relates to a circuit for reducing system energy consumption. Background Art
[0002] As the functions of system chips become more complex, power consumption requirements are increasing, and low-power design is becoming more and more important, especially in the field of handheld terminal IOT chips.
[0003] A common low-power design method is to intervene in MCU management and power management when the chip is working. The MCU main control chip detects the business flow of the chip. When the chip is in the idle state, the clock frequency is reduced and the relevant power supply is turned off to achieve the purpose of low power consumption.
[0004] However, when the power is turned off, in complex business scenarios, some power must be present to meet related control. For example, the MCU and the chip interact through the SPI interface. When the MCU sends instructions and does not need to interact, the SPI enable is in an uncertain state, which will cause the original working module to be continuously turned off, resulting in leakage power consumption and reducing battery life.
[0005] After the SPI interface is turned off, the SPI loses control capability, and the chip leaks electricity, causing unnecessary leakage power consumption. Figure 1 shown. Utility Model Content
[0006] The utility model aims to provide a circuit for reducing system energy consumption, aiming to solve the above technical problems.
[0007] The utility model is implemented as follows: a circuit for reducing system energy consumption, the circuit for reducing system energy consumption comprises a processor MCU, a chipset unit and a power supply unit, the processor MCU is connected to the chipset unit via an SPI interface communication, the power supply unit is electrically connected to the processor MCU and the chipset unit respectively, the circuit for reducing system energy consumption also comprises a pull-down unit, one end of the pull-down unit is respectively connected to the processor MCU and the chipset unit, and the other end of the pull-down unit is grounded.
[0008] A further technical solution of the present invention is: the pull-down unit adopts a resistor R1, one end of the resistor R1 is respectively connected to the processor unit and the chipset unit, and the other end of the resistor R1 is grounded.
[0009] A further technical solution of the utility model is: the circuit for reducing system energy consumption also includes a buffer unit, the input end of the buffer unit is connected to the output end of the processor MCU, the output end of the buffer unit is respectively connected to one end of the pull-down unit and the chipset unit, and the power supply unit is electrically connected to the power supply end of the buffer unit.
[0010] A further technical solution of the utility model is: the buffer unit is composed of a two-stage inverter, which includes a MOS tube PM1, a MOS tube PM4, a MOS tube NM2 and a MOS tube NM3, the source of the MOS tube PM1 is connected to the source of the MOS tube PM4, the drain of the MOS tube PM1 is respectively connected to the drain of the MOS tube NM2, the gate of the MOS tube PM4 and the gate of the MOS tube NM3, the drain of the MOS tube PM4 is connected to the drain of the MOS tube NM3, the source of the MOS tube NM2 is connected to the source of the MOS tube NM3, and the gate of the MOS tube PM1 is connected to the gate of the MOS tube NM2.
[0011] A further technical solution of the utility model is: the power supply unit is powered by a lithium battery or a switching power supply.
[0012] A further technical solution of the utility model is: the chipset unit is composed of various functional chips, and is composed of multiple chips in a system circuit.
[0013] The beneficial effects of the utility model are as follows: the circuit has a simple structure, the working module can be effectively shut down by the circuit, leakage power consumption can be effectively eliminated, and the service life of the battery is increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 This is a schematic diagram of the internal leakage of the chip.
[0015] Figure 2 This is a circuit for reducing system energy consumption provided by an embodiment of the utility model.
[0016] Figure 3 This is the second circuit for reducing system energy consumption provided by the embodiment of the utility model.
[0017] Figure 4 It is an electrical schematic diagram of the buffer unit provided in the embodiment of the utility model. DETAILED DESCRIPTION
[0018] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0019] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, in the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.
[0020] like Figure 2-4 As shown, the circuit for reducing system energy consumption provided by the utility model comprises a processor MCU, a chipset unit and a power supply unit, wherein the processor MCU is connected to the chipset unit via an SPI interface communication, and the power supply unit is electrically connected to the processor MCU and the chipset unit respectively, and the circuit for reducing system energy consumption also comprises a pull-down unit, one end of which is connected to the processor unit and the chipset unit respectively, and the other end of which is grounded. The structure of the circuit is simple, and the working module can be effectively shut down by the circuit, and the leakage power consumption can be effectively eliminated, thereby increasing the service life of the battery.
[0021] The pull-down unit adopts a resistor R1, one end of the resistor R1 is respectively connected to the processor unit and the chipset unit, and the other end of the resistor R1 is grounded.
[0022] The circuit for reducing system energy consumption also includes a buffer unit, the input end of the buffer unit is connected to the output end of the processor MCU, the output end of the buffer unit is respectively connected to one end of the pull-down unit and the chipset unit, and the power supply unit is electrically connected to the power supply end of the buffer unit.
[0023] The buffer unit is composed of a two-stage inverter, which includes a MOS transistor PM1, a MOS transistor PM4, a MOS transistor NM2 and a MOS transistor NM3. The source of the MOS transistor PM1 is connected to the source of the MOS transistor PM4, the drain of the MOS transistor PM1 is respectively connected to the drain of the MOS transistor NM2, the gate of the MOS transistor PM4 and the gate of the MOS transistor NM3, the drain of the MOS transistor PM4 is connected to the drain of the MOS transistor NM3, the source of the MOS transistor NM2 is connected to the source of the MOS transistor NM3, and the gate of the MOS transistor PM1 is connected to the gate of the MOS transistor NM2.
[0024] The power supply unit is powered by a lithium battery or a switching power supply.
[0025] The chipset unit is composed of various functional chips, and in a system circuit it is composed of multiple chips.
[0026] After the MCU ends control during use, it will no longer issue instructions, and the SPI interface output is in an uncertain state, such as Figure 1 As shown. It may be high or low. When V_ctrol is high, SW1 and SW2 will be opened, forming a path from Vdd1 to the ground, causing the power supply to inevitably leak to the ground. When the system tends to be complex, the leakage caused by the addition of these leakages is still considerable.
[0027] Add pull-down resistor R1, and V_ctrol is fixed at a low level. Turn off SW1 and SW2, which cuts off the path from vdd1 to ground and reduces the leakage of vdd1. However, this will introduce leakage current from the SPI output node to ground through R1, because the SPI interface is a standard high voltage 3.3V, which will cause the SPI power supply leakage to be extremely large.
[0028] In order to solve the leakage from SPI output to ground, Figure 2-4 As shown in the figure, a buffer composed of two-stage inverters and a Vdd2_low_power power supply network are added, and the buffer circuit is used to isolate the leakage path from the SPI output node to the ground. Finally, the Vdd2_low_power power supply is cut off to reduce the leakage of B1 and B2, achieving ultra-low power consumption of the system.
[0029] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims
1. A circuit for reducing system energy consumption, characterized in that: The circuit for reducing system energy consumption includes a processor MCU, a chipset unit and a power supply unit. The processor MCU is connected to the chipset unit via an SPI interface communication. The power supply unit is electrically connected to the processor MCU and the chipset unit respectively. The circuit for reducing system energy consumption also includes a pull-down unit. One end of the pull-down unit is connected to the processor MCU and the chipset unit respectively, and the other end of the pull-down unit is grounded.
2. The circuit for reducing system energy consumption according to claim 1, characterized in that: The pull-down unit adopts a resistor R1, one end of the resistor R1 is respectively connected to the processor unit and the chipset unit, and the other end of the resistor R1 is grounded.
3. The circuit for reducing system energy consumption according to claim 1 or 2, characterized in that: The circuit for reducing system energy consumption also includes a buffer unit, the input end of the buffer unit is connected to the output end of the processor MCU, the output end of the buffer unit is respectively connected to one end of the pull-down unit and the chipset unit, and the power supply unit is electrically connected to the power supply end of the buffer unit.
4. The circuit for reducing system energy consumption according to claim 3, characterized in that: The buffer unit is composed of a two-stage inverter, which includes a MOS transistor PM1, a MOS transistor PM4, a MOS transistor NM2 and a MOS transistor NM3. The source of the MOS transistor PM1 is connected to the source of the MOS transistor PM4, the drain of the MOS transistor PM1 is respectively connected to the drain of the MOS transistor NM2, the gate of the MOS transistor PM4 and the gate of the MOS transistor NM3, the drain of the MOS transistor PM4 is connected to the drain of the MOS transistor NM3, the source of the MOS transistor NM2 is connected to the source of the MOS transistor NM3, and the gate of the MOS transistor PM1 is connected to the gate of the MOS transistor NM2.
5. The circuit for reducing system energy consumption according to claim 4, characterized in that: The power supply unit is powered by a lithium battery or a switching power supply.