Display device

Abstract

There is provided a display device including: an active pattern disposed on a substrate; a gate electrode disposed on the active pattern; a first connection electrode disposed on the active pattern and connected to the active pattern; a first electrode line disposed on the first connection electrode; a second electrode line disposed on the same layer as the first electrode line and forming a first capacitor with the first electrode line; a third electrode line disposed on the same layer as the first electrode line and forming a second capacitor with the second electrode line; a first data line disposed on the third electrode line; and a second data line spaced apart from the first data line. The display device has improved display quality.

Description

Technical Field

[0001] Embodiments disclosed herein generally relate to a display device and more particularly to a display device that provides visual information. Background Art

[0002] A display device is a device that displays an image to provide visual information to a user. Among display devices, organic light emitting diode displays (OLED displays) have attracted attention and have been used in many different applications. One application is in head mounted displays (HMDs) and the like that can be used in virtual reality (VR) or augmented reality (AR). Micro displays can be applied in products such as head mounted displays. As a micro display, an organic light emitting diode on silicon (OLEDoS) display can be used.

[0003] The OLEDoS display may include pixels, each pixel including an anode electrode, an organic light emitting layer, and a cathode electrode formed on a semiconductor substrate. The semiconductor substrate may include a CMOS circuit for controlling each pixel. Utility Model Content

[0004] The purpose of the utility model is to provide a display device with improved display quality.

[0005] A display device according to an embodiment may include: an active pattern disposed on a substrate; a gate electrode disposed on the active pattern; a first connection electrode disposed on the active pattern and connected to the active pattern; a first electrode line disposed on the first connection electrode; a second electrode line disposed on the same layer as the first electrode line and forming a first capacitor with the first electrode line; a third electrode line disposed on the same layer as the first electrode line and forming a second capacitor with the second electrode line; a first data line disposed on the third electrode line; and a second data line spaced apart from the first data line.

[0006] In an embodiment, the first data line and the second data line may be at different layers.

[0007] In an embodiment, no electrode line may be disposed on the second data line.

[0008] In an embodiment, no electrode line may be disposed between the first data line and the second data line.

[0009] In an embodiment, the display device may further include a fourth electrode line disposed on the first electrode line, and a MIM (Metal-Insulator-Metal) capacitor may be formed between the first electrode line and the fourth electrode line.

[0010] A display device according to another embodiment of the present disclosure may include: an active pattern, which is arranged on a substrate; a gate electrode, which is arranged on the active pattern; a first connection electrode, which is arranged on the active pattern and connected to the active pattern; a 1-1 electrode line, which is arranged on the first connection electrode; a 2-1 electrode line, which is arranged on the same layer as the 1-1 electrode line and forms a first capacitor with the 1-1 electrode line; a first data line, which is arranged on the 2-1 electrode line; a 3-1 electrode line, which is arranged on the first data line; a 2-3 electrode line, which is arranged on the same layer as the 3-1 electrode line and forms a second capacitor with the 3-1 electrode line; and a second data line, which is arranged on the 2-3 electrode line.

[0011] In an embodiment, the display device may further include: a 1-2 electrode line, arranged on the 1-1 electrode line and electrically connected to the 1-1 electrode line; and a 2-2 electrode line, arranged on the 2-1 electrode line, electrically connected to the 2-1 electrode line and forming a third capacitor with the 1-2 electrode line, the third capacitor being connected in parallel with the first capacitor.

[0012] In an embodiment, the first data line may be disposed on the same layer as the 2-2 electrode line.

[0013] In an embodiment, the display device may further include: a 3-2 electrode line, arranged on the 3-1 electrode line and electrically connected to the 3-1 electrode line; and a 2-4 electrode line, arranged on the 2-3 electrode line, electrically connected to the 2-3 electrode line and forming a fourth capacitor with the 3-2 electrode line, the fourth capacitor being connected in parallel with the second capacitor.

[0014] In an embodiment, the second data line may be disposed on the same layer as the 2-4 electrode line.

[0015] In an embodiment, the display device may further include a MIM capacitor between the 1-1 electrode line and the 1-2 electrode line.

[0016] According to another embodiment of the present disclosure, a display device may include: an active pattern, which is arranged on a substrate; a gate electrode, which is arranged on the active pattern; a first connection electrode, which is arranged on the active pattern and connected to the active pattern; a 1-1 electrode line, which is arranged on the first connection electrode; a 2-1 electrode line, which is arranged on the same layer as the 1-1 electrode line and forms a 1-1 capacitor with the 1-1 electrode line; a 3-1 electrode line, which is arranged on the 1-1 electrode line; a 2-2 electrode line, which is arranged on the same layer as the 3-1 electrode line, is electrically connected to the 2-1 electrode line, and forms a 2-1 capacitor with the 3-1 electrode line; a first data line, which is arranged on the 3-1 electrode line; and a second data line, which is arranged separately from the first data line.

[0017] In an embodiment, the first data line and the second data line may be at different layers.

[0018] In an embodiment, no electrode line may be disposed on the second data line.

[0019] In an embodiment, the electrode line may not be formed on a layer between the second data line and the first data line.

[0020] In an embodiment, the display device may further include: a 1-2 electrode line, arranged on the 1-1 electrode line and electrically connected to the 1-1 electrode line; and a 2-3 electrode line, arranged on the 2-1 electrode line and electrically connected to the 2-1 electrode line, and the 1-2 electrode line and the 2-3 electrode line may form a 1-2 capacitor.

[0021] In an embodiment, the display device may further include: a 3-2 electrode line, arranged on the 3-1 electrode line and electrically connected to the 3-1 electrode line; and a 2-4 electrode line, arranged on the 2-2 electrode line and electrically connected to the 2-2 electrode line, and the 3-2 electrode line and the 2-4 electrode line may form a 2-2 capacitor.

[0022] In an embodiment, the first data line may be in the same layer as the 1-2 electrode line.

[0023] In an embodiment, the second data line may be in the same layer as the 3-2 electrode line.

[0024] In an embodiment, the display device may further include a MIM capacitor between the 1-1 electrode line and the 3-1 electrode line.

[0025] Therefore, in the display device according to the embodiment of the present disclosure, by setting the existing data line from the same layer as the connection electrode to the electrode line layer, the interaction with the gate electrode can be reduced to prevent the formation of parasitic capacitance. Therefore, the charging rate of the capacitor can be ensured. In this case, the data line can be separated from the connection electrode by one layer. Thus, when designing high-speed drive pixels, it is possible to achieve the desired brightness in each pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are included to illustrate and provide a further understanding of the embodiments described below in detail.

[0027] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0028] Figure 2 yes Figure 1 An enlarged plan view of portion P.

[0029] Figure 3 It is shown that the Figure 1 A circuit diagram of a sub-pixel in a display device.

[0030] Figure 4 is a cross-sectional view showing a sub-pixel.

[0031] Figure 5 It is shown that the Figure 4 A plan view of the 1-1 electrode line and the 2-3 electrode line in a sub-pixel.

[0032] Figure 6 It is shown that the Figure 4 A plan view of the 2-1 electrode line and the 3-1 electrode line in a sub-pixel.

[0033] Figure 7 is a cross-sectional view showing a sub-pixel included in a display device according to an embodiment of the present disclosure.

[0034] Figure 8 It is shown that the Figure 7 A plan view of the 1-1 electrode line, the 2-1 electrode line, and the 3-1 electrode line in a sub-pixel.

[0035] Fig. 9 It is shown that the Figure 7 A plan view of a 1-3 electrode line, a 2-3 electrode line, a 3-3 electrode line and a first data line in a sub-pixel.

[0036] Fig.10 It is shown that the Figure 7 A plan view of the 1-4 electrode line, the 2-4 electrode line, the 3-4 electrode line and the second data line in a sub-pixel.

[0037] Fig.11 is a cross-sectional view illustrating a sub-pixel included in a display device according to another embodiment of the present disclosure.

[0038] Fig.12 It is shown that the Fig.11 A plan view of the 1-1 electrode line and the 2-1 electrode line in a sub-pixel.

[0039] Fig.13 It is shown that the Fig.11 A plan view of a 1-2 electrode line, a 2-2 electrode line and a first data line in a sub-pixel.

[0040] Fig.14 It is shown that the Fig.11 A plan view of the 2-3 electrode line and the 3-1 electrode line in a sub-pixel.

[0041] Fig.15 It is shown that the Fig.11 A plan view of the 2-4 electrode line, the 3-2 electrode line, and the second data line in a sub-pixel.

[0042] Fig.16 is a cross-sectional view illustrating a sub-pixel included in a display device according to still another embodiment of the present disclosure.

[0043] Fig.17 It is shown that the Fig.16 A plan view of the 1-1 electrode line and the 2-1 electrode line in a sub-pixel.

[0044] Fig.18 It is shown that the Fig.16 A plan view of the 2-2 electrode line and the 3-1 electrode line in a sub-pixel.

[0045] Fig.19 It is shown that the Fig.16 A plan view of the 1-2 electrode line, the 2-3 electrode line and the first data line in a sub-pixel.

[0046] Fig. 20 It is shown that the Fig.16 A plan view of the 2-4 electrode line, the 3-2 electrode line, and the second data line in a sub-pixel.

[0047] Fig.21 is a cross-sectional view illustrating a sub-pixel included in a display device according to still another embodiment.

[0048] Fig. 22 It is shown that the Fig.21 Magnified view of the first MIM capacitor and the second MIM capacitor in the sub-pixel. DETAILED DESCRIPTION

[0049] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0050] Figure 1 is a plan view showing a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 , the display device 100 according to the illustrated embodiment may include a display portion 130 and driving portions CON, 110, and 120. The display portion 130 may be a region capable of displaying an image by generating light or adjusting the transmittance of light provided from an external light source. The driving portions CON, 110, and 120 may be a region where an image is not displayed. The driving portions CON, 110, and 120 may be located around the display portion 130.

[0052] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 may be perpendicular to the second direction DR2.

[0053] A plurality of sub-pixels 160 and 161 may be provided in the display portion 130. The plurality of sub-pixels 160 and 161 may be arranged in an array or matrix form having rows extending along a first direction DR1 and columns extending along a second direction DR2. Each of the plurality of sub-pixels 160 and 161 may emit light. When the plurality of sub-pixels 160 and 161 emit light, the display portion 130 may display an image.

[0054] Lines connected to the plurality of sub-pixels 160 and 161 may also be provided in the display portion 130. For example, the lines in the display portion 130 may include data signal lines, gate signal lines, and power lines.

[0055] Devices for driving the plurality of sub-pixels 160 and 161 may be provided in the driving parts CON, 110, and 120. For example, the driving parts CON, 110, and 120 may include a data driving part 120, a gate driving part 110, and a timing controller CON. The plurality of sub-pixels 160 and 161 may emit light based on a signal transmitted from the driving part.

[0056] Figure 2 yes Figure 1 An enlarged plan view of portion P.

[0057] Reference Figure 2 , the display device 100 according to an embodiment of the present disclosure may include a first data line 140 and a second data line 141 that respectively apply signals to sub-pixels 160 and 161. The first data line 140 may transmit a data voltage to the first sub-pixel 160, and the second data line 141 may transmit a data voltage to the second sub-pixel 161.

[0058] Figure 3 It is shown that the Figure 1 A circuit diagram of a sub-pixel in a display device.

[0059] Reference Figures 1 to 3 , each of the sub-pixels 160 and 161 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5, a first capacitor CAP1, and a second capacitor CAP2.

[0060] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the first capacitor CAP1. In another embodiment, the gate electrode of the first transistor T1 may be connected to the second capacitor CAP2 and the first electrode of the third transistor T3. The first electrode of the first transistor T1 may be connected to the second electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The driving voltage ELVDD may be applied to the second electrode of the first transistor T1.

[0061] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. A data write signal GW may be applied to the gate electrode of the second transistor T2. A data voltage DATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first capacitor CAP1.

[0062] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The compensation gate signal GC may be applied to the gate electrode of the third transistor T3. The second capacitor CAP2 may be connected to the first electrode of the third transistor T3. The second electrode of the third transistor T3 may be connected to the first electrode of the first transistor T1 and the second electrode of the fifth transistor T5.

[0063] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. A reference gate signal GR may be applied to the gate electrode of the fourth transistor T4. A first capacitor CAP1 may be connected to the first electrode of the fourth transistor T4. A reference voltage VREF may be applied to the second electrode of the fourth transistor T4.

[0064] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. The emission control signal EM may be applied to the gate electrode of the fifth transistor T5. The first electrode of the fifth transistor T5 may be connected to the anode of the light emitting element. The second electrode of the fifth transistor T5 may be connected to the first electrode of the first transistor T1 and the second electrode of the third transistor T3. One end of the light emitting element may be connected to the first electrode of the fifth transistor T5, and the other end thereof may receive the second voltage ELVSS.

[0065] The first capacitor CAP1 may include a first electrode and a second electrode. The first electrode of the first capacitor CAP1 may be connected to the second electrode of the second transistor T2. The second electrode of the first capacitor CAP1 may be connected to the gate electrode of the first transistor T1. In another embodiment, the second electrode of the first capacitor CAP1 may be connected to the first electrode of the second capacitor CAP2 or the third transistor T3.

[0066] The second capacitor CAP2 may include a first electrode and a second electrode. The driving voltage ELVDD may be applied to the first electrode of the second capacitor CAP2. The second electrode of the second capacitor CAP2 may be connected to the second electrode of the first capacitor CAP1. In another embodiment, the second electrode of the second capacitor CAP2 may be connected to the gate electrode of the first transistor T1 and the first electrode of the third transistor T3.

[0067] However, although it has been described that each of the sub-pixels 160 and 161 includes 5 transistors and 2 capacitors, the embodiment is not limited thereto. For example, each of the sub-pixels 160 and 161 may include at least one transistor and at least one storage capacitor.

[0068] Figure 4 is a cross-sectional view showing a sub-pixel for comparison.

[0069] Reference Figure 4 The display device 200 includes a substrate 201, active patterns 202, 203 and 204, a gate electrode 205, a first connection electrode 210, a second connection electrode 211, a third connection electrode 220, first electrode lines 250 and 260, second electrode lines 231, 241, 251 and 261, third electrode lines 232 and 242, a data line 270, a first insulating layer 21, a second insulating layer 22, a third insulating layer 23, a fourth insulating layer 24, a fifth insulating layer 25, a sixth insulating layer 26, a seventh insulating layer 27 and an eighth insulating layer 28.

[0070] The first electrode lines 250 and 260 include 1-1 electrode lines 250 and 1-2 electrode lines 260 , the second electrode lines 231 , 241 , 251 and 261 include 2-1 electrode lines 231 , 2-2 electrode lines 241 , 2-3 electrode lines 251 and 2-4 electrode lines 261 , and the third electrode lines 232 and 242 include 3-1 electrode lines 232 and 3-2 electrode lines 242 .

[0071] like Figure 4 As shown in FIG. 1 , the first insulating layer 21, the second insulating layer 22, the third insulating layer 23, the fourth insulating layer 24, the fifth insulating layer 25, the sixth insulating layer 26, the seventh insulating layer 27, and the eighth insulating layer 28 separate the layers on which the active patterns 202, 203, and 204, the gate electrode 205, the first connection electrode 210, the second connection electrode 211, the third connection electrode 220, the first electrode lines 250 and 260, the second electrode lines 231, 241, 251, and 261, the third electrode lines 232 and 242, and the data line 270 are respectively formed. Each of the first insulating layer 21, the second insulating layer 22, the third insulating layer 23, the fourth insulating layer 24, the fifth insulating layer 25, the sixth insulating layer 26, the seventh insulating layer 27, and the eighth insulating layer 28 may be formed of an inorganic material or an organic material.

[0072] The substrate 201 may be a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates, etc. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, a second organic layer, etc. Alternatively, the substrate 201 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a F-doped quartz substrate, a soda-lime glass or non-alkaline glass substrate, etc. These may be used alone or in combination with each other.

[0073] Active patterns 202 , 203 , and 204 are disposed on a substrate 201 .

[0074] The gate electrode 205 and the connection electrodes 210 , 211 , and 220 are disposed on the active patterns 202 , 203 , and 204 .

[0075] exist Figure 4 In the embodiment, the data line 270 and the third connection electrode 220 are disposed on the same layer, and the data line 270 transmits a data signal to adjust the brightness of the display device 200 .

[0076] The 1-1 electrode line 250 , the 1-2 electrode line 260 , the 2-3 electrode line 251 , and the 2-4 electrode line 261 form a first capacitor 281 .

[0077] The 2-1 electrode line 231 , the 2-2 electrode line 241 , the 3-1 electrode line 232 , and the 3-2 electrode line 242 form a second capacitor 282 .

[0078] The first electrode lines 250 and 260 , the second electrode lines 231 , 241 , 251 , and 261 , and the third electrode lines 232 and 242 forming the first capacitor 281 and the second capacitor 282 form a MOM (Metal-Oxide-Metal) capacitor.

[0079] Figure 5 It is shown that the Figure 4 A plan view of the 1-1 electrode line and the 2-3 electrode line in the sub-pixel, Figure 6 It is shown that the Figure 4 A plan view of the 2-1 electrode line and the 3-1 electrode line in a sub-pixel.

[0080] Reference Figure 5 , the 1-1 electrode line 250 and the 2-3 electrode line 251 are interlaced with each other, and the finger-like protrusions of the 1-1 electrode line 250 are located between the finger-like protrusions of the 2-3 electrode line 251. Optionally, each of the 1-1 electrode line 250 and the 2-3 electrode line 251 can have a serpentine shape, a repeated "S" shape, or a zigzag shape, and each electrode line can be positioned to provide a long perimeter adjacent to the electrode line corresponding to the counter electrode of the capacitor. For example, the 1-1 electrode line 250 and the 2-3 electrode line 251 form a first capacitor 281.

[0081] Reference Figure 6, the 2-1 electrode line 231 and the 3-1 electrode line 232 are interlaced with each other, and the finger-like protrusions of the 2-1 electrode line 231 are located between the finger-like protrusions of the 3-1 electrode line 232. Optionally, each of the 2-1 electrode line 231 and the 3-1 electrode line 232 can have a serpentine shape, a repeated "S" shape, or a zigzag shape. In addition, the 2-1 electrode line 231 and the 3-1 electrode line 232 form a second capacitor 282. However, the shape of the electrode line is not limited to the shape shown in the figure, and can be arranged in various shapes.

[0082] In the embodiment, the 1-1 electrode line 250 and the 1-2 electrode line 260 have the same shape, and the 2-3 electrode line 251 and the 2-4 electrode line 261 have the same shape. Figure 5 An electrode line of the same shape as shown in FIG. 1 is formed on a layer above the 1-1 electrode line 250 .

[0083] In the embodiment, the 3-1 electrode line 232 and the 3-2 electrode line 242 have the same shape, and the 2-1 electrode line 231 and the 2-2 electrode line 241 have the same shape. Figure 6 An electrode line of the same shape as shown in FIG. 2 is formed on a layer above the 3-1 electrode line 232 .

[0084] At least one first via 290 electrically connects the first electrode lines 250 and 260. The second electrode lines 231, 241, 251, and 261 may be electrically connected through at least one second via 291, and the third electrode lines 232 and 242 may be electrically connected through at least one third via 292. The electrically connected first electrode lines, second electrode lines, and third electrode lines share the same voltage, respectively. The first via 290, the second via 291, and the third via 292 may be collectively referred to as vias 290, 291, and 292.

[0085] Figure 7 384, 386, and 388. The first capacitors 381, 383, 385, and 387 may include a 1-1 capacitor 381, a 1-2 capacitor 383, a 1-3 capacitor 385, and a 1-4 capacitor 387. The second capacitors 382, ​​384, 386, and 388 may include a 2-1 capacitor 382, ​​a 2-2 capacitor 384, a 2-3 capacitor 386, and a 2-4 capacitor 388. In an embodiment, the 1-1 capacitor 381 and the 2-1 capacitor 382 may be formed on the same layer, and the 1-2 capacitor 383 and the 2-2 capacitor 384 may be formed on the same layer.

[0086] according to Figure 7The display device 300 of the embodiment shown in may include a substrate 301, active patterns 302, 303 and 304, a gate electrode 305, connecting electrodes 310, 311, 320 and 321, electrode lines 330, 331, 332, 340, 341, 342, 350, 351, 352, 361 and 362 forming first capacitors 381, 383, 385 and 387 and second capacitors 382, ​​384, 386 and 388, a first data line 370, a second data line 371, a first insulating layer 31, a second insulating layer 32, a third insulating layer 33, a fourth insulating layer 34, a fifth insulating layer 35, a sixth insulating layer 36, a seventh insulating layer 37 and an eighth insulating layer 38.

[0087] like Figure 7 As shown in FIG. 1 , the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the fourth insulating layer 34, the fifth insulating layer 35, the sixth insulating layer 36, the seventh insulating layer 37, and the eighth insulating layer 38 may separate the layers on which the active patterns 302, 303, and 304, the gate electrode 305, the first connection electrode 310, the second connection electrode 311, the third connection electrode 320, and the fourth connection electrode 321, the electrode lines 330, 331, 332, 340, 341, 342, 350, 351, 352, 361, and 362 forming the capacitors 381 to 388, and the first data line 370 and the second data line 371 are respectively formed. Each of the first insulating layer 31, the second insulating layer 32, the third insulating layer 33, the fourth insulating layer 34, the fifth insulating layer 35, the sixth insulating layer 36, the seventh insulating layer 37, and the eighth insulating layer 38 may be formed of an inorganic material or an organic material.

[0088] The substrate 301 may include a transparent material or an opaque material. For example, the substrate 301 may include a rigid glass substrate, a polymer substrate, a flexible film, a metal substrate, etc. These may be used alone or in combination with each other. In an embodiment, the substrate 301 may include a rigid glass substrate.

[0089] The active patterns 302, 303, and 304 may be disposed on the substrate 301. The active patterns 302, 303, and 304 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, etc. The active patterns 302, 303, and 304 may include a source region 303, a drain region 304, and a channel region 302 located between the source region 303 and the drain region 304.

[0090] The metal oxide semiconductor forming the active patterns 302, 303 and 304 may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z ). For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These may be used alone or in combination with each other.

[0091] Therefore, a transistor including a gate electrode 305 , a source region 303 , and a drain region 304 may be disposed on the substrate 301 .

[0092] The first connection electrode 310, the second connection electrode 311, the third connection electrode 320 and the fourth connection electrode 321 may be disposed on the transistor. For example, the first connection electrode 310 and the third connection electrode 320 may overlap and be electrically connected to the source region 303, and the second connection electrode 311 and the fourth connection electrode 321 may overlap and be electrically connected to the drain region 304.

[0093] The first electrode lines 330, 340 and 350, the second electrode lines 331, 341, 351 and 361 and the third electrode lines 332, 342, 352 and 362 may be disposed on the connection electrodes 310, 311, 320 and 321, or formed in a layer covering the connection electrodes 310, 311, 320 and 321. The first electrode lines 330, 340 and 350 may include a 1-1 electrode line 330, a 1-2 electrode line 340 and a 1-3 electrode line 350, respectively. The second electrode lines 331, 341, 351 and 361 may include a 2-1 electrode line 331, a 2-2 electrode line 341, a 2-3 electrode line 351 and a 2-4 electrode line 361, respectively. The third electrode lines 332 , 342 , 352 , and 362 may include a 3-1 electrode line 332 , a 3-2 electrode line 342 , a 3-3 electrode line 352 , and a 3-4 electrode line 362 , respectively.

[0094] Figure 8 , Fig. 9 and Fig.10 shows where it can be formed Figure 7 A plan view of the layers of the capacitor shown in FIG. Figure 8 In the layer shown in FIG. 1 , the 1-1 electrode line 330 and the 2-1 electrode line 331 are adjacent to each other in a region and can form a 1-1 capacitor 381. Figure 8In another layer of a layout similar to the layout shown in FIG, the 1-2 electrode line 340 and the 2-2 electrode line 341 can form a 1-2 capacitor 383. Fig. 9 In the layer shown in , the 1-3 electrode line 350 and the 2-3 electrode line 351 are adjacent to each other in a region and can form a 1-3 capacitor 385. Fig.10 In the layers shown in , the 1-4 electrode line 360 ​​and the 2-4 electrode line 361 are adjacent to each other and may form a 1-4 capacitor 387. In another embodiment, the 1-1 electrode line 330 and the 1-2 electrode line 340 may form a MIM capacitor.

[0095] In addition, Figure 8 In the layer shown in FIG. 3 , the 2-1 electrode line 331 and the 3-1 electrode line 332 are adjacent to each other in a region and may form a 2-1 capacitor 382 . The 2-2 electrode line 341 and the 3-2 electrode line 342 may have a similar layout and may form a 2-2 capacitor 384 . Fig. 9 In the layer shown in FIG. 1 , the 2-3 electrode line 351 and the 3-3 electrode line 352 are adjacent to each other in a region and can form a 2-3 capacitor 386, and in Fig.10 In the layer shown in , the 2-4 electrode line 361 and the 3-4 electrode line 362 are adjacent to each other in a region and may form a 2-4 capacitor 388 .

[0096] 1-1 capacitor 381, 1-2 capacitor 383, 1-3 capacitor 385, and 1-4 capacitor 387 may be connected in parallel to form a larger capacitor (e.g., Figure 3 The first capacitor CAP1), and the 2-1 capacitor 382, ​​the 2-2 capacitor 384, the 2-3 capacitor 386 and the 2-4 capacitor 388 may be connected in parallel to form a structure having, for example, Figure 3 The larger capacitor of the second capacitor CAP2. In particular, the via 390 can electrically connect the first electrode lines 330, 340, 350 and 360, the via 391 can electrically connect the second electrode lines 331, 341, 351 and 361, and the via 392 can electrically connect the third electrode lines 332, 342, 352 and 362. The connected electrode lines can have the same voltage by transmitting and receiving electrical signals through the vias 390, 391 or 392 connecting the electrode lines. The vias 390, 391 and 392 can include a first via 390, a second via 391 and a third via 392, respectively. In an embodiment, the electrode lines can be electrically connected to each other, for example, the 1-1 electrode line 330 can be electrically connected to the 1-2 electrode line 340 through the first via 390.

[0097] Each of the first capacitors 381 , 383 , 385 , and 387 and the second capacitors 382 , 384 , 386 , and 388 may be a MOM capacitor.

[0098] like Fig. 9 As shown in , the first data line 370 can be disposed on the same layer as the 2-3 electrode line 351. Fig.10 As shown in , the second data line 371 may be disposed on a layer covering the first data line 370, and may be disposed on the same layer as the 2-4 electrode line 361. In another embodiment, the first data line 370 and the second data line 371 are not disposed on the same layer as the 2-3 electrode line 351 and the 2-4 electrode line 361, respectively, but may be disposed on respective layers separated from the third connection electrode 320 and the fourth connection electrode 321 by one layer.

[0099] Figure 8 It is shown that the Figure 7 A plan view of the 1-1 electrode line, the 2-1 electrode line, and the 3-1 electrode line in a sub-pixel.

[0100] Reference Figure 8 , each of the 1-1 electrode line 330 and the 3-1 electrode line 332 may have a serpentine shape, a repeated "S" shape or a zigzag shape, and the 2-1 electrode line 331 may have a protrusion extending into a fold within the shape of the 1-1 electrode line 330 and the 3-1 electrode line 332. In addition, the 1-1 electrode line 330 and the 2-1 electrode line 331 may form a 1-1 capacitor 381, and the 2-1 electrode line 331 and the 3-1 electrode line 332 may form a 2-1 capacitor 382. However, the embodiment is not limited to a specific shape or plan view, and various types of MOM capacitors may be formed.

[0101] In an embodiment, the 1-1 electrode line 330 and the 1-2 electrode line 340 may have the same shape, the 2-1 electrode line 331 and the 2-2 electrode line 341 may have the same shape, and the 3-1 electrode line 332 and the 3-2 electrode line 342 may have the same shape. Figure 8 Electrode wires of the shape shown in .

[0102] Fig. 9 It is shown that the Figure 7 A plan view of the 1-3 electrode line, the 2-3 electrode line, the 3-3 electrode line and the first data line in the sub-pixel, Fig.10 It is shown that the Figure 7 A plan view of the 1-4 electrode line, the 2-4 electrode line, the 3-4 electrode line and the second data line in a sub-pixel.

[0103] As shown, each of the 1-3 electrode lines 350, 1-4 electrode lines 360, 2-3 electrode lines 351, 2-4 electrode lines 361, 3-3 electrode lines 352 and 3-4 electrode lines 362 can have a repeating "S" shape, a finger shape or a Z shape, and each electrode line can be interwoven or staggered with the opposing electrode lines to increase the capacitance that can be provided in the area.

[0104] In addition, 1-3 electrode line 350 and 2-3 electrode line 351 can form 1-3 capacitor 385, 2-3 electrode line 351 and 3-3 electrode line 352 can form 2-3 capacitor 386, 1-4 electrode line 360 ​​and 2-4 electrode line 361 can form 1-4 capacitor 387, and 2-4 electrode line 361 and 3-4 electrode line 362 can form 2-4 capacitor 388. However, the embodiment is not limited to a specific shape of the plan view, and various types of MOM capacitors can be formed.

[0105] In another embodiment, the first data line 370 and the second data line 371 are not only formed on the same layer as the 2-3 electrode line 351 and the 2-4 electrode line 361 respectively, but the first data line 370 and the second data line 371 can also be formed on each layer separated from the third connection electrode 320 and the fourth connection electrode 321 by one layer.

[0106] exist Figure 7 In the embodiment, the data line is not in the same layer as the connection electrode, and this arrangement of the data line can prevent the formation of parasitic capacitance by reducing the interaction of the data line with the gate electrode. Therefore, the charging rate of the capacitor can be improved. In this case, the data line can be separated from the connection electrode by at least one layer. Thus, the pixels can be driven at high speed while still providing the desired brightness in each pixel.

[0107] Fig.11 is a cross-sectional view illustrating a portion of a sub-pixel included in a display device 400 according to another embodiment of the present disclosure. Fig.11 The display device 400 includes a sub-pixel in which a first capacitor 481 and a second capacitor 482 may be formed at different layers.

[0108] Reference Fig.11 The display device 400 may include a substrate 401, active patterns 402, 403 and 404, a gate electrode 405 and connecting electrodes 410, 411, 420 and 421, electrode lines 430, 431, 440, 441, 451, 452, 461 and 462 forming capacitors 481 and 482, a first data line 470 and a second data line 471, a first insulating layer 41, a second insulating layer 42, a third insulating layer 43, a fourth insulating layer 44, a fifth insulating layer 45, a sixth insulating layer 46, a seventh insulating layer 47 and an eighth insulating layer 48.

[0109] like Fig.11 As shown in the figure, the first insulating layer 41, the second insulating layer 42, the third insulating layer 43, the fourth insulating layer 44, the fifth insulating layer 45, the sixth insulating layer 46, the seventh insulating layer 47 and the eighth insulating layer 48 can separate the layers on which active patterns 402, 403 and 404, the gate electrode 405, the first connecting electrode 410, the second connecting electrode 411, the third connecting electrode 420 and the fourth connecting electrode 421, the electrode lines 430, 431, 440, 441, 451, 452, 461 and 462, the first data line 470 and the second data line 471 are respectively formed.

[0110] For example, each of the first insulating layer 41 , the second insulating layer 42 , the third insulating layer 43 , the fourth insulating layer 44 , the fifth insulating layer 45 , the sixth insulating layer 46 , the seventh insulating layer 47 , and the eighth insulating layer 48 may be formed of an inorganic material or an organic material.

[0111] The substrate 401 may include a transparent material or an opaque material. For example, the substrate 401 may include a rigid glass substrate, a polymer substrate, a flexible film, a metal substrate, etc. These may be used alone or in combination with each other. In an embodiment, the substrate 401 may include a rigid glass substrate.

[0112] The active patterns 402, 403, and 404 may be disposed on the substrate 401. The active patterns 402, 403, and 404 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, etc. The active patterns 402, 403, and 404 may include a source region 403, a drain region 404, and a channel region 402 located between the source region 403 and the drain region 404.

[0113] The metal oxide semiconductor forming the active patterns 402, 403 and 404 may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z ). For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These may be used alone or in combination with each other.

[0114] The gate electrode 405 may cover the channel region 402. Therefore, a transistor including the gate electrode 405, the source region 403 and the drain region 404, and the channel region 402 may be disposed on the substrate 401.

[0115] The first connection electrode 410 , the second connection electrode 411 , the third connection electrode 420 , and the fourth connection electrode 421 may be disposed on the transistor.

[0116] Portions of the first electrode lines 430 and 440 , the second electrode lines 431 , 441 , 451 , and 461 , and the third electrode lines 452 and 462 may be disposed on the third connection electrode 420 and the fourth connection electrode 421 .

[0117] The first electrode lines 430 and 440 may include 1-1 electrode lines 430 and 1-2 electrode lines 440. The second electrode lines 431, 441, 451, and 461 may include 2-1 electrode lines 431, 2-2 electrode lines 441, 2-3 electrode lines 451, and 2-4 electrode lines 461. The third electrode lines 452 and 462 may include 3-1 electrode lines 452 and 3-2 electrode lines 462.

[0118] 1-1 electrode line 430, 1-2 electrode line 440, 2-1 electrode line 431 and 2-2 electrode line 441 can form a first capacitor 481, and 2-3 electrode line 451, 2-4 electrode line 461, 3-1 electrode line 452 and 3-2 electrode line 462 can form a second capacitor 482. In other words, 1-1 electrode line 430 and 2-1 electrode line 431 can form a capacitor, and 1-2 electrode line 440 and 2-2 electrode line 441 can form another capacitor at different layers. 2-3 electrode line 451 and 3-1 electrode line 452 can form a capacitor, and 2-4 electrode line 461 and 3-2 electrode line 462 can form another capacitor at different layers. The first capacitor 481 and the second capacitor 482 can be MOM capacitors.

[0119] The first electrode lines 430 and 440 may be formed by Fig.12 and Fig.13 The second electrode lines 431, 441, 451 and 461 can be electrically connected through the via 490 shown in FIG. Figures 12 to 15 The third electrode lines 452 and 462 can be electrically connected through the via 491 shown in Fig.14 and Fig.15The electrically connected electrode lines may have the same voltage by transmitting and receiving electrical signals through the vias 490, 491, or 492. The vias 490, 491, and 492 may include a first via 490, a second via 491, and a third via 492.

[0120] The first data line 470 may be disposed in the same layer as the 1-2 electrode line 440. The second data line 471 may be disposed in a layer on the first data line 470 or in a layer covering the first data line 470, and may be disposed in the same layer as the 2-4 electrode line 461. In another embodiment, the first data line 470 and the second data line 471 may not be disposed in the same layer as the 1-2 electrode line 440 and the 2-4 electrode line 461, respectively, but may be disposed on respective layers separated from the third connection electrode 420 and the fourth connection electrode 421 by at least one layer.

[0121] Fig.12 It is shown that the Fig.11 A plan view of an embodiment of a 1-1 electrode line 430 and a 2-1 electrode line 431 in a sub-pixel, Fig.13 It is shown that the Fig.11 A plan view of an embodiment of a 1-2 electrode line 440, a 2-2 electrode line 441 and a first data line 470 in a sub-pixel of FIG. Fig.14 It is shown that the Fig.11 A plan view of an embodiment of a 2-3 electrode line 451 and a 3-1 electrode line 452 in a sub-pixel, Fig.15 It is shown that the Fig.11 1 and 2. A plan view of an embodiment of a 2-4 electrode line 461, a 3-2 electrode line 462, and a second data line 471 in a sub-pixel of FIG.

[0122] like Fig.12 and Fig.13 As shown in , the 1-1 electrode line 430 , the 2-1 electrode line 431 , the 1-2 electrode line 440 , and the 2-2 electrode line 441 may form a first capacitor 481 .

[0123] like Fig.14 and Fig.15 As shown in , the 2-3 electrode line 451 , the 2-4 electrode line 461 , the 3-1 electrode line 452 , and the 3-2 electrode line 462 may form a second capacitor 482 .

[0124] In addition, each of the first electrode lines 430 and 440, the second electrode lines 431, 441, 451 and 461 and the third electrode lines 452 and 462 can have a serpentine shape, a repeated "S" shape, a zigzag shape or a finger shape. Each of the electrode lines can be shaped and positioned to provide a long perimeter length adjacent to the perimeter of another electrode line formed in the same layer. However, the embodiment is not limited to the specific shape of the plan view, and various types of MOM capacitors can be formed.

[0125] like Fig.11 As shown in , the existing data lines 470 and 471 are arranged in the same layer as the electrode lines of the capacitor, rather than in the same layer as the connecting electrode, which can reduce the interaction with the gate electrode of the transistor to prevent the formation of parasitic capacitance. Therefore, the charging rate of the capacitor can be improved. In this case, the data line can be arranged to be separated from the connecting electrode by one or more layers. Thus, when designing high-speed drive pixels, it is possible to achieve the desired brightness in each pixel. However, with Figure 7 different, Fig.11 The embodiment shown in is characterized in that the first capacitor 481 is provided in a layer separate from the layer in which the second capacitor 482 is formed.

[0126] Fig.16 is a cross-sectional view showing a portion of a sub-pixel included in a display device 500 according to still another embodiment of the present disclosure. Fig.16 In FIG. 5 , the subpixel has first capacitors 581 and 583 and second capacitors 582 and 584 arranged alternately in different layers.

[0127] The first capacitors 581 and 583 may include a 1-1 capacitor 581 and a 1-2 capacitor 583, and the second capacitors 582 and 584 may include a 2-1 capacitor 582 and a 2-2 capacitor 584. In an embodiment, the 2-1 capacitor 582 may be formed on the 1-1 capacitor 581, and the 1-2 capacitor 583 may be formed on the 2-1 capacitor 582.

[0128] Reference Fig.16 The display device 500 may include a substrate 501, active patterns 502, 503 and 504, a gate electrode 505, connecting electrodes 510, 511, 520 and 521, electrode lines 530, 531, 541, 542, 550, 551, 561 and 562, a first data line 570, a second data line 571, a first insulating layer 51, a second insulating layer 52, a third insulating layer 53, a fourth insulating layer 54, a fifth insulating layer 55, a sixth insulating layer 56, a seventh insulating layer 57 and an eighth insulating layer 58.

[0129] like Fig.16As shown in the figure, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, the fourth insulating layer 54, the fifth insulating layer 55, the sixth insulating layer 56, the seventh insulating layer 57 and the eighth insulating layer 58 can separate the layers on which active patterns 502, 503 and 504, the gate electrode 505, the connecting electrodes 510, 511, 520 and 521, the electrode lines 530, 531, 541, 542, 550, 551, 561 and 562 forming the first capacitors 581 and 583 and the second capacitors 582 and 584, the first data line 570 and the second data line 571 are respectively formed.

[0130] For example, each of the first insulating layer 51 , the second insulating layer 52 , the third insulating layer 53 , the fourth insulating layer 54 , the fifth insulating layer 55 , the sixth insulating layer 56 , the seventh insulating layer 57 , and the eighth insulating layer 58 may be formed of an inorganic material or an organic material.

[0131] The substrate 501 may include a transparent material or an opaque material. For example, the substrate 501 may include a rigid glass substrate, a polymer substrate, a flexible film, a metal substrate, etc. These may be used alone or in combination with each other. In an embodiment, the substrate 501 may include a rigid glass substrate.

[0132] The active patterns 502, 503, and 504 may be disposed on the substrate 501. The active patterns 502, 503, and 504 may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor, etc. The active patterns 502, 503, and 504 may include a source region 503, a drain region 504, and a channel region 502 located between the source region 503 and the drain region 504.

[0133] The metal oxide semiconductor used in the active patterns 502, 503, and 504 may include a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ), quaternary compounds (AB x C y D z ). For example, the metal oxide semiconductor may include zinc oxide (ZnO x ), gallium oxide (GaO x ), tin oxide (SnO x ), indium oxide (InO x ), indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), etc. These may be used alone or in combination with each other.

[0134] A transistor including a gate electrode 505 , a source region 503 , a drain region 504 , and a channel region 502 may be disposed on a substrate 501 .

[0135] The first connection electrode 510 , the second connection electrode 511 , the third connection electrode 520 , and the fourth connection electrode 521 may be disposed on the transistor.

[0136] The first electrode lines 530 and 550 , the second electrode lines 531 , 541 , 551 , and 561 , and the third electrode lines 542 and 562 may be formed in a layer covering the third and fourth connection electrodes 520 and 521 .

[0137] The first electrode lines 530 and 550 may include 1-1 electrode lines 530 and 1-2 electrode lines 550. The second electrode lines 531, 541, 551, and 561 may include 2-1 electrode lines 531, 2-2 electrode lines 541, 2-3 electrode lines 551, and 2-4 electrode lines 561. The third electrode lines 542 and 562 may include 3-1 electrode lines 542 and 3-2 electrode lines 562.

[0138] 1-1 electrode line 530 and 2-1 electrode line 531 may form 1-1 capacitor 581, 2-2 electrode line 541 and 3-1 electrode line 542 may form 2-1 capacitor 582. In addition, 1-2 electrode line 550 and 2-3 electrode line 551 may form 1-2 capacitor 583, 2-4 electrode line 561 and 3-2 electrode line 562 may form 2-2 capacitor 584.

[0139] Fig.17 and Fig.19 The via hole 590 shown in FIG. 5 may electrically connect the first electrode lines 530 and 550 . Figures 17 to 20 The via hole 591 shown in FIG. 5 can electrically connect the second electrode lines 531 , 541 , 551 , and 561 . Fig.18 and Fig. 20 The via 592 shown in FIG. 5 may electrically connect the third electrode lines 542 and 562. The electrically connected electrode lines may have the same voltage by transmitting and receiving electrical signals through the via 590, 591, or 592. The vias 590, 591, and 592 may include a first via 590, a second via 591, and a third via 592.

[0140] The first capacitors 581 and 583 and the second capacitors 582 and 584 may be MOM capacitors. In addition, in the display device 500, the first capacitors 581 and 583 and the second capacitors 582 and 584 may be arranged at different layers. In an embodiment, the 2-1 capacitor 582 may be formed on the 1-1 capacitor 581, and the 1-2 capacitor 583 may be formed on the 2-1 capacitor 582.

[0141] The first data line 570 may be disposed on the same layer as the 2-3 electrode line 551. The second data line 571 may be disposed on the first data line 570 and may be disposed on the same layer as the 2-4 electrode line 561. However, in another embodiment, the first data line 570 and the second data line 571 may not only be formed on the same layer as the 2-3 electrode line 551 and the 2-4 electrode line 561, respectively, but may also be formed on respective layers separated from the connection electrodes 520 and 521 by one layer.

[0142] Fig.17 It is shown that the Fig.16 A plan view of the 1-1 electrode line 530 and the 2-1 electrode line 531 in the sub-pixel, Fig.18 It is shown that the Fig.16 A plan view of the 3-1 electrode line 542 and the 2-2 electrode line 541 in the sub-pixel, Fig.19 It is shown that the Fig.16 A plan view of the 1-2 electrode line 550, the 2-3 electrode line 551 and the first data line 570 in the sub-pixel, Fig. 20 It is shown that the Fig.16 A plan view of the 2-4 electrode line 561, the 3-2 electrode line 562 and the second data line 571 in a sub-pixel.

[0143] In addition, each of the first electrode lines 530 and 550, the second electrode lines 531, 541, 551 and 561 and the third electrode lines 542 and 562 can have a serpentine shape, a repeated "S" shape, a zigzag shape or a finger shape. Each of the electrode lines can be positioned or arranged to be staggered with another electrode line formed in the same layer. However, the embodiment is not limited to the specific shape of the plan view, and various types of MOM capacitors can be formed.

[0144] like Fig.16 As shown in , by arranging the data line and the electrode line in the same layer, the interaction with the gate electrode of the transistor below can be reduced to prevent the formation of parasitic capacitance. Therefore, the charging rate of the capacitor can be improved. In this case, the data line can be arranged to be separated from the connecting electrode by one or more layers. Thus, when driven at high speed, each pixel in the display device can achieve the desired brightness. However, Fig.16 Examples and Fig.11 The embodiment is different in that the first capacitor and the second capacitor may be formed in different layers and alternately formed.

[0145] Fig.21 is a cross-sectional view illustrating a portion of a sub-pixel included in a display device 600 according to another embodiment.

[0146] The display device 600 may include a substrate 601, active patterns 602, 603 and 604, a gate electrode 605, connecting electrodes 610, 611, 620 and 621, a first MIM capacitor i1, a second MIM capacitor i2, a capacitor forming part 680, a first insulating layer 61, a second insulating layer 62, a third insulating layer 63, a fourth insulating layer 64, a fifth insulating layer 65, a sixth insulating layer 66, a seventh insulating layer 67 and an eighth insulating layer 68.

[0147] like Fig.21 As shown in the figure, the first insulating layer 61, the second insulating layer 62, the third insulating layer 63, the fourth insulating layer 64, the fifth insulating layer 65, the sixth insulating layer 66, the seventh insulating layer 67 and the eighth insulating layer 68 can separate the layers on which active patterns 602, 603 and 604, the gate electrode 605, the connecting electrodes 610, 611, 620 and 621, the first MIM capacitor i1, the second MIM capacitor i2 and the capacitor forming part 680 are respectively formed.

[0148] For example, each of the first insulating layer 61 , the second insulating layer 62 , the third insulating layer 63 , the fourth insulating layer 64 , the fifth insulating layer 65 , the sixth insulating layer 66 , the seventh insulating layer 67 , and the eighth insulating layer 68 may be formed of an inorganic material or an organic material.

[0149] The substrate 601 may include a transparent material or an opaque material.

[0150] Fig. 22 It is shown that the Fig.21 An enlarged view of the structure of the first MIM capacitor i1 and the second MIM capacitor i2 in the sub-pixel.

[0151] The MIM capacitor is formed with an insulating layer 631 interposed between a lower metal 632 and an upper metal 633. The lower metal 632 is on the lower electrode line 630.

[0152] The lower metal 632 may be electrically connected to the upper electrode line 641 through the via 691 by contacting the lower electrode line 630. In addition, the upper metal 633 may be electrically connected to the upper electrode line 640 through the via 690.

[0153] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the utility model concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display device, characterized in that: The display device comprises: An active pattern is disposed on a substrate; A gate electrode, disposed on the active pattern; a first connection electrode disposed on the active pattern and connected to the active pattern; A first electrode line, arranged on the first connecting electrode; a second electrode line, which is disposed in the same layer as the first electrode line and forms a first capacitor with the first electrode line; a third electrode line, which is disposed in the same layer as the first electrode line and forms a second capacitor with the second electrode line; A first data line is arranged on the third electrode line; and The second data line is spaced apart from the first data line.

2. The display device according to claim 1, characterized in that The first data line and the second data line are in different layers.

3. A display device, characterized in that: The display device comprises: An active pattern is disposed on a substrate; A gate electrode, disposed on the active pattern; a first connection electrode disposed on the active pattern and connected to the active pattern; 1-1 electrode line, arranged on the first connecting electrode; The 2-1 electrode line is provided in the same layer as the 1-1 electrode line and forms a first capacitor with the 1-1 electrode line; A first data line, arranged on the 2-1 electrode line; 3-1 electrode line, arranged on the first data line; A 2-3 electrode line is provided in the same layer as the 3-1 electrode line and forms a second capacitor with the 3-1 electrode line; and The second data line is arranged on the 2-3 electrode line.

4. The display device according to claim 3, characterized in that: The display device further includes: A 1-2 electrode line, disposed on the 1-1 electrode line and electrically connected to the 1-1 electrode line; and The 2-2 electrode line is disposed on the 2-1 electrode line, is electrically connected to the 2-1 electrode line, and forms a third capacitor with the 1-2 electrode line. The third capacitor is connected in parallel with the first capacitor.

5. The display device according to claim 4, characterized in that: The first data line and the 2-2 electrode line are arranged in the same layer.

6. The display device according to claim 3, characterized in that: The display device further includes: A 3-2 electrode line, disposed on the 3-1 electrode line and electrically connected to the 3-1 electrode line; and The 2-4 electrode line is disposed on the 2-3 electrode line, is electrically connected to the 2-3 electrode line, and forms a fourth capacitor with the 3-2 electrode line, wherein the fourth capacitor is connected in parallel with the second capacitor.

7. A display device, characterized in that: The display device comprises: An active pattern is disposed on a substrate; A gate electrode, disposed on the active pattern; a first connection electrode disposed on the active pattern and connected to the active pattern; 1-1 electrode line, arranged on the first connecting electrode; A 2-1 electrode line is provided in the same layer as the 1-1 electrode line and forms a 1-1 capacitor with the 1-1 electrode line; 3-1 electrode line, arranged on the 1-1 electrode line; A 2-2 electrode line is provided in the same layer as the 3-1 electrode line, is electrically connected to the 2-1 electrode line, and forms a 2-1 capacitor with the 3-1 electrode line; A first data line, arranged on the 3-1 electrode line; and The second data line is arranged separately from the first data line.

8. The display device according to claim 7, characterized in that: The first data line and the second data line are in different layers.

9. The display device according to claim 7, characterized in that: The display device further includes: A 1-2 electrode line, disposed on the 1-1 electrode line and electrically connected to the 1-1 electrode line; and 2-3 electrode line, arranged on the 2-1 electrode line and electrically connected to the 2-1 electrode line, Wherein, the 1-2 electrode line and the 2-3 electrode line form a 1-2 capacitor.

10. The display device according to claim 9, characterized in that: The first data line and the 1-2 electrode line are formed in the same layer.

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