Electronic package
By reducing the difference in thermal expansion coefficient between the heat dissipation structure and the core layer of the load-bearing structure, making the deformation trends the same, the stress problem caused by the difference in thermal expansion coefficient of existing semiconductor packages is solved, and packaging substrate cracking and electrical test abnormalities are avoided.
Patent Information
- Application Number
- CN202421102629.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-10
- Filing Date
- 2024-05-20
- Publication Date
- 2025-01-24
- Estimated Expiration
- 2034-05-20
AI Technical Summary
Due to the large difference in thermal expansion coefficient between the heat dissipation parts and the package substrate, existing semiconductor packages cause stress pulling up and down after high and low temperature cycle tests, resulting in cracking and abnormal electrical performance tests of the package substrate.
By reducing the differences in thermal expansion coefficients of the core layer in the bearer structure, the deformation trend of the bearer structure and the heat dissipation structure is the same, thereby reducing the warning stress of the electronic packaging parts and avoiding the protection of the protective layer (green paint).
Effectively reduce the impact of electronic packaging parts due to warpan, avoid the insulation layer (green paint) cracking of the bearing structure, and ensure the normal nature of subsequent electrical tests.
Smart Images
Figure CN222394811U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a semiconductor packaging structure, in particular to an electronic packaging component with a heat dissipation structure. Background Art
[0002] As the demand for electronic products in terms of functions and processing speed increases, semiconductor chips, as the core components of electronic products, need to have higher density electronic components and electronic circuits. Therefore, semiconductor chips will generate more heat energy during operation.
[0003] In order to quickly dissipate heat to the outside, the industry usually configures a heat sink in the semiconductor package. The heat sink is usually combined with the back of the chip through a heat sink such as a thermal interface material (TIM) to dissipate the heat generated by the semiconductor chip through the heat sink and the heat sink.
[0004] like Figure 1 As shown, the manufacturing method of the conventional semiconductor package 1 is to first place a semiconductor chip 11 on a package substrate 10 with its active surface 11a by flip chip bonding (i.e., through conductive bumps 110 and bottom glue 111), and then place a heat sink 13 with its top sheet 130 on the inactive surface 11b of the semiconductor chip 11 through a heat sink 12, and the support legs 131 of the heat sink 13 are mounted on the package substrate 10 through an adhesive layer 14. During operation, the heat energy generated by the semiconductor chip 11 is conducted to the top sheet 130 of the heat sink 13 through the heat sink 12 to dissipate the heat to the outside of the semiconductor package 1.
[0005] However, due to the large difference in coefficient of thermal expansion (CTE) between the heat sink 13 and the package substrate 10 , the semiconductor package 1 generates stress and pulls up and down after the high and low temperature cycle test, causing the package substrate 10 to crack and even cause abnormalities in subsequent electrical tests.
[0006] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Utility Model Content
[0007] In view of the various deficiencies of the above-mentioned prior art, the present application provides an electronic package, comprising: a supporting structure, having a core layer and a circuit layer combined with the core layer; an electronic component, configured on the supporting structure and electrically connected to the circuit layer; and a heat dissipation structure, configured on the electronic component, wherein the heat dissipation structure has a first deformation trend, the supporting structure has a second deformation trend, and the first deformation trend is the same as the second deformation trend.
[0008] In the aforementioned electronic package, the supporting structure has an insulating layer covering the circuit layer; the insulating layer is green paint.
[0009] In the aforementioned electronic package, the supporting structure is a packaging substrate having the core layer; and the circuit layer is a redistribution circuit layer.
[0010] In the aforementioned electronic package, the electronic component is a semiconductor chip having an active surface and an inactive surface opposite to each other, and the active surface is electrically connected to the supporting structure and the circuit layer through a plurality of conductive bumps in a flip chip manner.
[0011] In the aforementioned electronic package, the heat dissipation structure has a top sheet and a support portion extending from the top sheet, wherein the top sheet is disposed on the electronic element through a heat conductor.
[0012] In the aforementioned electronic package, the difference in thermal expansion coefficient between the heat dissipation structure and the core layer is less than 7 ppm / °C. In addition, the first deformation trend is that the edge of the heat dissipation structure is higher than the center or the edge of the heat dissipation structure is lower than the center, and the second deformation trend is that the edge of the load-bearing structure is higher than the center or the edge of the load-bearing structure is lower than the center.
[0013] To summarize, the electronic package of the present application includes electronic components, a supporting structure and a heat dissipation structure, wherein the difference in thermal expansion coefficients between the heat dissipation structure and the core layer in the supporting structure is reduced so that the deformation trends of the supporting structure and the heat dissipation structure are the same, thereby reducing the warping stress of the electronic package and avoiding the problem of cracking of the protective layer (green paint). BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.
[0015] Figure 2 It is a cross-sectional schematic diagram of the electronic package of the present application.
[0016] Figure 3 This is a schematic diagram of the deformation of the electronic package of the present application.
[0017] Description of Reference Numerals
[0018] 1 Semiconductor Package
[0019] 10 Package substrate
[0020] 11. Semiconductor Chip
[0021] 11a Action surface
[0022] 11b Non-active surface
[0023] 110 Conductive bump
[0024] 111 Primer
[0025] 12 Heat sink
[0026] 13 Heat sink
[0027] 130 Top sheet
[0028] 131 Support feet
[0029] 14 Adhesive layer
[0030] 2 Electronic packaging
[0031] 21 Load-bearing structure
[0032] 21a First surface
[0033] 21b Second surface
[0034] 210 Core Layer
[0035] 211 Line Layer
[0036] 212 Insulation layer
[0037] 22 Electronic components
[0038] 22a Active surface
[0039] 22b Non-active surface
[0040] 220 Conductive bump
[0041] 221 Primer
[0042] 23. Heat dissipation structure
[0043] 231 Top sheet
[0044] 232 Support
[0045] 24 Heat Conductor
[0046] 25 Bonding layer
[0047] W1 First deformation trend
[0048] W2 Second deformation trend. DETAILED DESCRIPTION
[0049] The following describes the implementation methods of the present application through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification.
[0050] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings attached to this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application. At the same time, the terms such as "on", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of this application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of this application without substantially changing the technical contents.
[0051] Figure 2 It is a cross-sectional schematic diagram of the electronic package 2 of the present application, which mainly arranges at least one electronic component 22 on a supporting structure 21 , and connects a heat dissipation structure 23 to the electronic component 22 via a heat conductor 24 .
[0052] The supporting structure 21 is defined with a first surface 21 a and a second surface 21 b opposite to each other, and includes a core layer 210 , a circuit layer 211 combined with the core layer 210 , and an insulating layer 212 covering the circuit layer 211 .
[0053] In this embodiment, the supporting structure 21 is, for example, a package substrate having the core layer 210 , the circuit layer 211 is, for example, a redistribution layer (RDL for short), and the insulating layer 212 is, for example, a green paint (Solder Mask).
[0054] The electronic component 22 is, for example, an active component, a passive component, a package module or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.
[0055] In this embodiment, the electronic component 22 is a semiconductor chip having an active surface 22a and an inactive surface 22b opposite to each other, and the active surface 22a is electrically connected to the support structure 21 and the circuit layer 211 through a plurality of conductive bumps 220 in a flip chip manner, and a primer 221 is formed between the first surface 21a of the support structure 21 and the active surface 22a to cover each of the conductive bumps 220. However, there are many ways for the electronic component 22 to be electrically connected to the support structure 21, which are not limited to the above.
[0056] The heat dissipation structure 23 is, for example, a heat sink, a heat dissipation cover (Lid) or other components or structures with equivalent functions. In this embodiment, a heat dissipation cover is used as an example, wherein the heat dissipation structure 23 has a top sheet 231 and a support portion 232 extending from the top sheet 231. The support portion 232 is fixedly connected to the first surface 21a of the supporting structure 21 around the electronic component 22 through a bonding layer 25, so that the top sheet 231 is opposite to the non-active surface 22b of the electronic component 22.
[0057] The heat conductor 24 is disposed between the inactive surface 22b of the electronic component 22 and the top sheet 231 of the heat dissipation structure 23 to more efficiently conduct the heat generated by the electronic component 22 to the heat dissipation structure 23 and then dissipate it into the environment. In one embodiment, the heat conductor 24 is a thermal interface material (TIM) layer, the main material of which is metal indium (In) or indium silver (In / Ag) alloy.
[0058] The present application mainly makes the difference in the coefficient of thermal expansion (CTE) between the heat dissipation structure 23 and the core layer 210 of the supporting structure 21 less than 7ppm / °C, so that even if the electronic package 2 is subjected to thermal stress during the manufacturing process, the heat dissipation structure 23 has a first deformation trend W1 (the first deformation trend can be that the edge of the heat dissipation structure is higher than the center or the edge of the heat dissipation structure is lower than the center), and the supporting structure 21 has a second deformation trend W2 (the second deformation trend can be that the edge of the supporting structure is higher than the center or the edge of the supporting structure is lower than the center), but the first deformation trend W1 is the same as the second deformation trend W2 (such as Figure 3 As shown), the stress on the electronic package 2 due to warping is reduced to avoid cracking of the insulating layer 212 (ie, the green paint on the package substrate) of the supporting structure 21, which may even lead to abnormal conditions in subsequent electrical tests.
[0059] In summary, the electronic package of the present application includes electronic components, a supporting structure and a heat dissipation structure, wherein the difference in thermal expansion coefficients between the heat dissipation structure and the core layer of the supporting structure is reduced, and the deformation trends of the supporting structure and the heat dissipation structure are made the same, so as to reduce the stress on the electronic package due to warping and avoid the problem of cracking of the protective layer (green paint).
[0060] The above embodiments are used to illustrate the principles and effects of the present application, but are not used to limit the present application. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present application. Therefore, the scope of protection of the present application should be as listed in the claims.
Claims
1. An electronic package, characterized in that: include: A bearing structure comprising a core layer and a circuit layer combined with the core layer; An electronic component is disposed on the supporting structure and electrically connected to the circuit layer; as well as The heat dissipation structure is disposed on the electronic component, wherein the heat dissipation structure has a first deformation trend, the supporting structure has a second deformation trend, and the first deformation trend is the same as the second deformation trend.
2. The electronic package according to claim 1, wherein: The supporting structure has an insulating layer covering the circuit layer.
3. The electronic package as claimed in claim 2, characterized in that The insulating layer is green paint.
4. The electronic package according to claim 1, wherein: The bearing structure is a packaging substrate having the core layer.
5. The electronic package according to claim 1, wherein: This circuit layer is a redistribution circuit layer.
6. The electronic package according to claim 1, wherein: The electronic component is a semiconductor chip having an active surface and an inactive surface opposite to each other. The active surface is electrically connected to the supporting structure and the circuit layer through a plurality of conductive bumps in a flip chip manner.
7. The electronic package according to claim 1, wherein: The heat dissipation structure comprises a top sheet and a supporting portion extending from the top sheet.
8. The electronic package according to claim 7, wherein: The top sheet is arranged on the electronic element through a heat conductor.
9. The electronic package according to claim 1, wherein: The difference in thermal expansion coefficient between the heat dissipation structure and the core layer is less than 7 ppm / °C.
10. The electronic package according to claim 1, wherein: The first deformation trend is that the edge of the heat dissipation structure is higher than the center or the edge of the heat dissipation structure is lower than the center.
11. The electronic package according to claim 1, wherein: The second deformation trend is that the edge of the load-bearing structure is higher than the center or the edge of the load-bearing structure is lower than the center.