Power stage circuit

Abstract

The power level circuit comprises a switching circuit, a driving circuit and a current monitoring circuit. The driving circuit drives the switching circuit to generate an output current signal. The current monitoring circuit comprises a current sensing circuit, a virtual current signal generating circuit and a signal combining circuit. The virtual current signal generating circuit generates a low-side voltage signal according to the low-side current signal generated by the current sensing circuit, generates and adjusts a digital signal according to a comparison result of the low-side voltage signal and the virtual voltage signal, and adjusts the virtual voltage signal according to the digital signal to enable the virtual voltage signal to be close to the low-side voltage signal. And a virtual current signal is generated according to the virtual voltage signal. The signal combining circuit generates a current monitoring signal according to the low-side current signal and the virtual current signal. The current monitoring circuit digitally corrects the virtual current signal to generate a current monitoring signal, so that the power level circuit has the advantages of low cost, suitability for low duty cycle application, high stability and high accuracy current monitoring signal generation and the like.

Description

Technical Field

[0001] The utility model relates to a power level circuit, in particular to a power level circuit suitable for a power converter circuit. Background Art

[0002] In the related applications of smart power stage modules, the smart power stage modules are often required to provide a current monitoring signal proportional to the inductor current. Some related technologies will add various electronic components to the smart power stage modules to meet the above requirements. However, the above additional electronic components cause the cost of these related technologies to increase significantly. Therefore, it is necessary to propose a new circuit to solve the above problem. Utility Model Content

[0003] One aspect of the utility model is a power stage circuit. The power stage circuit includes a switch circuit, a drive circuit and a current monitoring circuit. The switch circuit is coupled to the output end of the power stage circuit to receive an input voltage signal, and includes a high-side switch and a low-side switch, wherein the output end is coupled to the load end via an inductor element. The drive circuit is coupled to the switch circuit and is used to drive the switch circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element. The current monitoring circuit includes a current sensing circuit, a virtual current signal generating circuit and a signal combining circuit. The current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal. The virtual current signal generating circuit is coupled to the current sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, and is used to generate a digital signal, and is used to adjust the digital signal according to the comparison result between the low-side voltage signal and the virtual voltage signal in the first mode or the second mode, and is used to adjust the virtual voltage signal according to the digital signal, so that the virtual voltage signal is close to the low-side voltage signal, and is used to generate a virtual current signal according to the virtual voltage signal. The signal combining circuit is coupled to the current sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the first mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude, and the first adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases. In the second mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude, and the second adjustment amplitude is a constant value.

[0004] In some embodiments, the virtual current signal generating circuit is used to adjust the bit value of the lowest bit of the digital signal with the first adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the change in the bit value of the lowest bit of the digital signal corresponds to the first adjustment amplitude.

[0005] In some embodiments, when the voltage level of the virtual voltage signal is less than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to add the first adjustment amplitude to the bit value of the least significant bit. When the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to subtract the first adjustment amplitude from the bit value of the least significant bit.

[0006] In some embodiments, in a binary mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a second time. In the binary mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the second adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases.

[0007] In some embodiments, the first time is longer than the second time.

[0008] In some embodiments, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal N times in the binary mode, where N is the number of bits of the digital signal. Before performing one of the N comparisons, the virtual current signal generating circuit is used to switch the corresponding one of the N bits of the digital signal from a first value to a second value to generate the virtual voltage signal for the one of the N comparisons, and to determine the bit value of the corresponding one of the N bits according to the comparison result of the one of the N comparisons.

[0009] In some embodiments, when the voltage level of the virtual voltage signal is less than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the second value. When the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the first value.

[0010] In some embodiments, the first time is at least two cycles of the control signal.

[0011] Another aspect of the utility model is a power stage circuit, wherein the power stage circuit includes a switch circuit, a drive circuit and a current monitoring circuit. The switch circuit is coupled to the output end of the power stage circuit to receive an input voltage signal, and includes a high-side switch and a low-side switch, wherein the output end is coupled to the load end via an inductor element. The drive circuit is coupled to the switch circuit and is used to drive the switch circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element. The current monitoring circuit includes a current sensing circuit, a virtual current signal generating circuit and a signal combining circuit. The current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal. The virtual current signal generating circuit is coupled to the current sensing circuit, and is used to generate a low-side voltage signal according to the low-side current signal, and is used to generate a digital signal, and is used to adjust the digital signal according to the comparison result between the low-side voltage signal and the virtual voltage signal, and is used to adjust the virtual voltage signal according to the digital signal, so that the virtual voltage signal is close to the low-side voltage signal, and is used to generate a virtual current signal according to the virtual voltage signal. The signal combining circuit is coupled to the current sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the linear mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to the first time. In the linear mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the first adjustment amplitude is a fixed value.

[0012] In some embodiments, the virtual current signal generating circuit includes a current-to-voltage circuit, a comparison circuit, a digital circuit and a signal conversion circuit. The current-to-voltage circuit is coupled to the current sensing circuit, and is used to convert the low-side current signal into the low-side voltage signal. The comparison circuit is coupled to the current-to-voltage circuit, and is used to compare the low-side voltage signal with the virtual voltage signal. The digital circuit is coupled to the comparison circuit, and is used to generate the digital signal, and is used to adjust the digital signal according to the comparison result of the low-side voltage signal and the virtual voltage signal in the first mode or the second mode. The signal conversion circuit is coupled to the digital circuit and the comparison circuit, and is used to receive the digital signal, the input voltage signal and the output voltage signal, and is used to generate the virtual voltage signal according to the digital signal, the input voltage signal and the output voltage signal to generate the virtual current signal.

[0013] In summary, by generating a virtual current signal that is proportional to the output current signal through a virtual current signal generating circuit, the power stage circuit of the utility model can complete current sensing during the conduction period of the low-side switch, and can combine the virtual current signal with the low-side current signal obtained by current sensing to generate a current monitoring signal. In addition, the current monitoring circuit of the utility model significantly saves the number of components, and can digitally adjust the virtual voltage signal to correct the virtual current signal and ensure the stability of the virtual current signal. Therefore, the power stage circuit and its current monitoring circuit of the utility model have the advantages of low cost, suitable for low duty cycle applications, and generating a current monitoring signal with high stability and high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The invention is a circuit block diagram of a power stage circuit and a controller according to some embodiments of the invention.

[0015] Figure 2 The waveform diagrams are of some signals related to the power stage circuit according to some embodiments of the present invention.

[0016] Figure 3 The figure is a circuit diagram of a virtual current signal generating circuit according to some embodiments of the present invention.

[0017] Figure 4 The present invention is a flowchart of a method for adjusting a digital signal according to some embodiments of the present invention.

[0018] Figure 5 The following is a timing diagram of some signals related to a virtual current signal generating circuit in a binary mode according to some embodiments of the present invention.

[0019] Figure 6 The following is a timing diagram of some signals related to a virtual current signal generating circuit in a linear mode according to some embodiments of the present invention.

[0020] Figure 7 The figure is a flow chart of a method for generating a virtual current signal according to some embodiments of the present invention. DETAILED DESCRIPTION

[0021] The following embodiments are described in detail with reference to the accompanying drawings, but the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of the structural operation is not used to limit the order of its execution. Any structure recombined by the elements to produce a device with equal functions is within the scope of the present invention.

[0022] The terms used throughout the specification and claims generally have the ordinary meanings of each term used in the art, in the context of this disclosure, and in the specific context, unless otherwise noted.

[0023] As used herein, “coupled” or “connected” may refer to direct physical or electrical contact between two or more elements, or indirect physical or electrical contact between two or more elements, or may refer to mutual operation or action between two or more elements.

[0024] See also Figure 1 , Figure 1 The power stage circuit 10 and the controller 20 are circuit block diagrams according to some embodiments of the present invention. In some embodiments, the power stage circuit 10 and the controller 20 can form a power converter circuit such as a DC / DC converter. The power stage circuit 10 can be coupled to the load terminal SL via an inductor element L, and the load terminal SL can be electrically coupled to a load device such as a central processing unit (CPU) (not shown). In this way, the power converter circuit composed of the power stage circuit 10 and the controller 20 can supply power to the load device.

[0025] In some embodiments, such as Figure 1 As shown, the power stage circuit 10 includes a switch circuit 11, a drive circuit 13 and a current monitoring circuit 15. In addition, the switch circuit 11 includes a high-side switch Q1 and a low-side switch Q2. The high-side switch Q1 is coupled to the input voltage signal VIN and the output terminal SW of the power stage circuit 10, and the low-side switch Q2 is coupled to the output terminal SW and the ground voltage GND. As can be seen from the above description, in some embodiments, the switch circuit 11 is coupled to the output terminal SW and is used to receive the input voltage signal VIN. In addition, the output terminal SW is coupled to the load terminal SL via the inductor element L. Specifically, the high-side switch Q1 and the low-side switch Q2 can each be implemented by a transistor (for example, a metal oxide semiconductor transistor, etc.), but the utility model is not limited thereto.

[0026] In some embodiments, such as Figure 1As shown, the driving circuit 13 is coupled to the high-side switch Q1, the low-side switch Q2 and the controller 20, and is used to receive the control signal PWM output by the controller 20, and is used to generate a high-side driving signal GH and a low-side driving signal GL to the high-side switch Q1 and the low-side switch Q2 respectively according to the control signal PWM. Specifically, the control signal PWM can be a periodic signal such as a pulse width modulation (PWM) signal, and the driving circuit 13 can be implemented by a gate driver. In other words, the high-side driving signal GH and the low-side driving signal GL can be output to the gate end of the transistor in the high-side switch Q1 and the gate end of the transistor in the low-side switch Q2 respectively.

[0027] See also Figure 2 , Figure 2 are waveform diagrams of some signals related to the power stage circuit 10. In some embodiments, Figure 2 As shown, the high-side driving signal GH and the low-side driving signal GL are also periodic signals. The high-side driving signal GH and the control signal PWM are substantially in phase with each other. For example, when the high-side driving signal GH is at an enable level (e.g. Figure 2 , the control signal PWM may also be at the enable level. The high-side drive signal GH and the low-side drive signal GL are substantially inversely proportional to each other. For example, when the high-side drive signal GH is at the disable level (e.g. Figure 2 The low-side driving signal GL is at the enable level when the high-side switch Q1 or the low-side switch Q2 is at the low voltage level shown in the figure. Specifically, the enable level may be a voltage level that enables the high-side switch Q1 or the low-side switch Q2 to be turned on, and the disable level may be a voltage level that enables the high-side switch Q1 or the low-side switch Q2 to be turned off. In this configuration, the high-side driving signal GH at the enable level corresponds to the on-period HON of the high-side switch Q1 (i.e., the off-period of the low-side switch Q2), and the low-side driving signal GL at the enable level corresponds to the on-period LON of the low-side switch Q2 (i.e., the off-period of the high-side switch Q1).

[0028] From the above description, it can be seen that through Figure 2 The high-side drive signal GH and the low-side drive signal GL, Figure 1 The high-side switch Q1 and the low-side switch Q2 in the circuit are turned on alternately, so that a square wave voltage signal (not shown) is generated at the output terminal SW. It should be understood that the voltage level of the square wave voltage signal will switch between the voltage level of the input voltage signal VIN and the voltage level of the ground voltage GND.

[0029] At Figure 1In the embodiment of the present invention, the capacitor element COUT is coupled between the load terminal SL and the ground voltage GND to form a circuit (e.g., a low-pass filter circuit) with the inductor element L. This circuit is used to process the aforementioned square wave voltage signal to generate an output voltage signal VOUT at the load terminal SL. It should be understood that the aforementioned power converter circuit can supply power to the load device through the output voltage signal VOUT.

[0030] Another example Figure 1 As shown in FIG. 1 , when the two ends of the inductor element L respectively generate the aforementioned square wave voltage signal and the output voltage signal VOUT, an output current signal IL will be generated and flow through the inductor element L. In some embodiments, as Figure 2 As shown, the output current signal IL is a triangular wave or ramp signal.

[0031] As can be seen from the above description, in some embodiments, the driving circuit 13 is coupled to the switch circuit 11 and is used to drive the switch circuit 11 according to the control signal PWM to generate an output voltage signal VOUT at the load end SL and generate an output current signal IL via the inductor L.

[0032] In addition, Figure 1 In the embodiment of the present invention, the controller 20 is used to receive and compare the output voltage signal VOUT and the reference voltage signal VREF, and to adjust the duty ratio of the control signal PWM according to the comparison result between the output voltage signal VOUT and the reference voltage signal VREF, thereby changing the switching frequency of the high-side switch Q1 and the switching frequency of the low-side switch Q2.

[0033] In some embodiments, the current monitoring circuit 15 includes a current sensing circuit 151, a virtual current signal generating circuit 153, and a signal combining circuit 155. Figure 1 As shown, the current sensing circuit 151 is coupled to the switch circuit 11, for example, coupled between the output terminal SW and the low-side switch Q2. The virtual current signal generating circuit 153 is coupled to the current sensing circuit 151. The signal combining circuit 155 is coupled to the current sensing circuit 151 and the virtual current signal generating circuit 153.

[0034] In some embodiments, the current sensing circuit 151 is used to sense the output current signal IL (i.e., sense the current signal flowing through the low-side switch Q2) during each conduction period LON of the low-side switch Q2 to generate the low-side current signal ILS. Figure 2As shown, the current sensing circuit 151 does not sense the output current signal IL during the first period P1 of each conduction period LON of the low-side switch Q2, and senses the output current signal IL during the second period P2 of each conduction period LON of the low-side switch Q2, thereby generating the low-side current signal ILS. As can be seen from the above description, the low-side current signal ILS is substantially the same as the output current signal IL during each second period P2.

[0035] In some embodiments, the virtual current signal generating circuit 153 is used to receive the low-side current signal ILS and to generate a low-side voltage signal VLS (not shown) according to the low-side current signal ILS. Figure 1 and Figure 2 ), for determining the output voltage according to the low-side voltage signal VLS and the virtual voltage signal VVR (not shown in FIG. Figure 1 and Figure 2 The virtual voltage signal VVR is adjusted based on the comparison result of the low-side voltage signal VLS, so that the virtual voltage signal VVR is close to the low-side voltage signal VLS, and is used to generate a virtual current signal IVR according to the virtual voltage signal VVR. By adjusting the virtual voltage signal VVR, the virtual current signal IVR can be corrected so that the virtual current signal IVR is substantially close to or equal to the output current signal IL. The generation of the low-side voltage signal VLS, the virtual voltage signal VVR and the virtual current signal IVR will be combined later. Figures 3 to 6 Further details are given. It is worth noting that Figure 2 As shown, the virtual current signal IVR generated according to the virtual voltage signal VVR close to the low-side voltage signal VLS is substantially the same as the output current signal IL.

[0036] In some embodiments, the signal combining circuit 155 is used to receive the low-side current signal ILS and the virtual current signal IVR, and to generate the current monitoring signal IMON according to the low-side current signal ILS and the virtual current signal IVR. Figure 2 As shown, the signal combining circuit 155 combines the virtual current signal IVR corresponding to the first period P1 of each conduction period HON of the high-side switch Q1 and each conduction period LON of the low-side switch Q2 with the low-side current signal ILS corresponding to the second period P2 of each conduction period LON of the low-side switch Q2 to generate a current monitoring signal IMON.

[0037] In the above embodiment, there are two main reasons why the current sensing circuit 151 performs current sensing only during the second period P2 in each conduction period LON of the low-side switch Q2. The first reason is that the conduction period HON of the high-side switch Q1 is too short, so that in some practical applications (e.g., applications with low duty cycles), it is impossible to provide the current sensing circuit 151 with enough time to complete current sensing. Compared with the conduction period HON of the high-side switch Q1, the conduction period LON of the low-side switch Q2 can provide the current sensing circuit 151 with enough time to complete current sensing. The second reason is that the output current signal IL may not be stable during the first period P1 in each conduction period LON of the low-side switch Q2, and may become stable during the second period P2 in each conduction period LON of the low-side switch Q2. By allowing the current sensing circuit 151 to sense the stable output current signal IL during the second period P2, the reliability of the low-side current signal ILS can be further ensured. It is worth noting that the accuracy of the virtual current signal IVR and the current monitoring signal IMON generated based on the low-side current signal ILS can also be ensured.

[0038] Then match Figure 3 The circuit structure of the virtual current signal generating circuit 153 is described. Figure 3 , Figure 3 FIG. 1 is a circuit diagram of a virtual current signal generating circuit 153 according to some embodiments of the present invention. In some embodiments, the virtual current signal generating circuit 153 includes a current-to-voltage conversion circuit 31 , a comparison circuit 33 , a digital circuit 35 and a signal conversion circuit 37 .

[0039] In some embodiments, the current-to-voltage circuit 31 is coupled to Figure 1 The current sensing circuit 151 in the embodiment receives the low-side current signal ILS. The current-to-voltage circuit 31 is also used to convert the low-side current signal ILS into a low-side voltage signal VLS. Figure 3 As shown, the current-to-voltage circuit 31 can be implemented by a resistor element R1. Specifically, one end of the resistor element R1 can be coupled to the ground voltage GND, and the other end of the resistor element R1 can be used for the low-side current signal ILS to flow in. In other words, the low-side current signal ILS can flow through the resistor element R1 and flow into the ground voltage GND, so that the low-side voltage signal VLS is generated at the other end of the resistor element R1.

[0040] In some embodiments, the comparison circuit 33 is coupled to the current-to-voltage circuit 31, the digital circuit 35 and the signal conversion circuit 37, and is used to compare the low-side voltage signal VLS with the virtual voltage signal VVR. Specifically, the first input terminal (e.g., non-inverting input terminal) of the comparison circuit 33 is coupled to the other end of the aforementioned resistor element R1 to receive the low-side voltage signal VLS. The second input terminal (e.g., inverting input terminal) of the comparison circuit 33 is coupled to the signal conversion circuit 37 to receive the virtual voltage signal VVR. The output terminal of the comparison circuit 33 is coupled to the digital circuit 35 to provide the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR to the digital circuit 35.

[0041] In some embodiments, the digital circuit 35 is coupled to the comparison circuit 33 and the signal conversion circuit 37, and is used to generate a digital signal DOUT to the signal conversion circuit 37. Figure 3 As shown, the digital signal DOUT may be an N-bit signal. In some further embodiments, the digital circuit 35 includes a clock control circuit 351 and a digital control circuit 353, and the digital control circuit 353 includes a sampling and holding circuit 531 and a logic control circuit 533. The clock control circuit 351 is coupled to the sampling and holding circuit 531 and the logic control circuit 533. The sampling and holding circuit 531 is also coupled to the comparison circuit 33 and the logic control circuit 533, and the logic control circuit 533 is also coupled to the signal conversion circuit 37.

[0042] Following the description of the above embodiment, the clock control circuit 351 is used to receive the control signal PWM, the power-on reset voltage signal POR and the reload signal RL, and is used to generate the clock signal CLK, the latch signal LATCH, the binary mode signal MBIN and the linear mode signal MLIN according to the control signal PWM, the power-on reset voltage signal POR and the reload signal RL. In addition, the digital control circuit 353 is used to receive the clock signal CLK, the latch signal LATCH, the binary mode signal MBIN, the linear mode signal MLIN and the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR to adjust and output the digital signal DOUT, which will be combined with the following. Figures 4 to 6 Detailed description.

[0043] In some embodiments, the signal conversion circuit 37 is coupled to the digital circuit 35 and the comparison circuit 33 to receive the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT, and to generate a virtual voltage signal VVR according to the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT to generate a virtual current signal IVR.

[0044] In some further embodiments, Figure 3As shown, the signal conversion circuit 37 includes a virtual voltage signal generating circuit 371, a voltage-to-current circuit 373 and a capacitor element C37. The virtual voltage signal generating circuit 371 includes a first digital-to-analog conversion circuit DAC1, a second digital-to-analog conversion circuit DAC2, a first switch S1 and a second switch S2. The first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can be coupled to the output terminal N1 of the virtual voltage signal generating circuit 371 through the first switch S1 and the second switch S2, respectively. The virtual voltage signal generating circuit 371 is coupled to the second input terminal of the comparison circuit 33, the input terminal of the voltage-to-current circuit 373 and one end of the capacitor element C37 via the output terminal N1. The other end of the capacitor element C37 is coupled to the ground voltage GND, and the output terminal of the voltage-to-current circuit 373 is coupled to the ground voltage GND. Figure 1 However, the present invention is not limited thereto. For example, in some embodiments, the capacitor element C37 may be included in the virtual voltage signal generating circuit 371 .

[0045] Following the description of the above embodiment, the first digital-to-analog conversion circuit DAC1 is used to receive the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT, and is used to perform voltage-to-current conversion on the input voltage signal VIN minus the output voltage signal VOUT according to the digital signal DOUT to generate a first current signal SA. Specifically, the first current signal SA can be the input voltage signal VIN minus the output voltage signal VOUT multiplied by the first parameter. The second digital-to-analog conversion circuit DAC2 is used to receive the digital signal DOUT and the output voltage signal VOUT, and is used to perform voltage-to-current conversion on the negative number of the output voltage signal VOUT according to the digital signal DOUT to generate a second current signal SB. Specifically, the second current signal SB can be the negative number of the output voltage signal VOUT multiplied by the second parameter.

[0046] In the above embodiments, the first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can each be implemented by a transconductance amplifier, wherein the digital signal DOUT is used to adjust the gain of the transconductance amplifier to control the first parameter and the second parameter. However, the present invention is not limited thereto. In some embodiments, the first digital-to-analog conversion circuit DAC1 and the second digital-to-analog conversion circuit DAC2 can each be implemented by a circuit consisting of a current source, a resistor, and a buffer, wherein the digital signal DOUT is used to adjust the resistance value of the resistor to control the first parameter and the second parameter.

[0047] Please also read Figure 2 and Figure 3In some embodiments, the first switch S1 is switched to the on state when the high-side driving signal GH is at the enabling level, and the second switch S2 is switched to the on state when the low-side driving signal GL is at the enabling level. That is, the first switch S1 and the second switch S2 are switched to the on state alternately. Under this configuration, the capacitor element C37 can be charged by the first current signal SA generated by the first digital-to-analog conversion circuit DAC1 when the first switch S1 is at the on state, and can be charged by the second current signal SB generated by the second digital-to-analog conversion circuit DAC2 when the second switch S2 is at the on state, thereby generating the virtual voltage signal VVR at the output terminal N1.

[0048] It can be seen from the above description that in some embodiments, the virtual voltage signal generating circuit 371 is used to convert the input voltage signal VIN minus the output voltage signal VOUT into the first current signal SA according to the digital signal DOUT during each conduction period HON of the high-side switch Q1, and is used to convert the negative of the output voltage signal VOUT into the second current signal SB according to the digital signal DOUT during each conduction period LON of the low-side switch Q2 to generate the virtual voltage signal VVR.

[0049] In some embodiments, the voltage-to-current circuit 373 is used to convert the virtual voltage signal VVR into a virtual current signal IVR. For example, the voltage-to-current circuit 373 can be implemented by a resistor and a current mirror. The resistor can be coupled between the output terminal N1 and the ground voltage GND to generate a current signal flowing through the resistor. In addition, the current mirror can generate the virtual current signal IVR by replicating the current signal.

[0050] See also Figure 4 , Figure 4 FIG. 4 is a flow chart of a method 400 for adjusting a digital signal DOUT that can be executed by a digital circuit 35 according to some embodiments of the present invention. In some embodiments, Figure 4 As shown, the adjustment method 400 includes a plurality of operations S401 to S410. Figure 5 and Figure 6 The adjustment method 400 is described in detail. Figure 5 It is a timing diagram of some signals related to the virtual current signal generating circuit 153 in a binary mode according to some embodiments of the present invention. Figure 6 It is a timing diagram of some signals related to the virtual current signal generating circuit 153 in a linear mode according to some embodiments of the present invention.

[0051] In some embodiments, the digital circuit 35 performs the adjustment method 400 after the power stage circuit 10 is turned on. Specifically, after the power stage circuit 10 is turned on, the power-on reset voltage signal POR switches from a disable level to an enable level to trigger the clock control circuit 351 to correspondingly generate the clock signal CLK, the latch signal LATCH, the binary mode signal MBIN, and the linear mode signal MLIN.

[0052] For example, if Figure 4 As shown in FIG. 1 , the clock control circuit 351 can switch the binary mode signal MBIN and the linear mode signal MLIN to an enable level and a disable level respectively. The clock control circuit 351 can invert the control signal PWM and perform a delay operation on the inverted control signal PWM to generate the following: Figure 5 Furthermore, the clock control circuit 351 can perform a secondary delay operation on the inverted control signal PWM to generate a clock signal CLK as shown in FIG. Figure 5 The latch signal LATCH is shown. Accordingly, operation S401 is performed.

[0053] In operation S401, the digital circuit 35 switches between two different modes according to the binary mode signal MBIN and the linear mode signal MLIN, that is, operates in the binary mode or the linear mode. Figure 5 As shown, the digital control circuit 353 in the digital circuit 35 controls the virtual current signal generating circuit 153 to operate in the binary mode according to the binary mode signal MBIN of the enable level and the linear mode signal MLIN of the disable level. In some embodiments, the binary mode is referred to as the first mode, the linear mode is referred to as the second mode, and the first mode is different from the second mode. The binary mode signal MBIN is referred to as the first mode signal, and the linear mode signal MLIN is referred to as the second mode signal.

[0054] In some embodiments, Figure 3 The comparison circuit 33 in the binary mode compares the low-side voltage signal VLS with the virtual voltage signal VVR N times. Figure 5 In the embodiment of the present invention, the digital signal DOUT is an 8-bit signal, that is, N is 8. In other words, the digital signal DOUT includes 8 bits DOUT[0] to DOUT[7]. In addition, Figure 5 The multiple time points T1-T8 in represent the execution time of 8 comparisons respectively. Before N comparisons are performed, operation S402 is performed.

[0055] In operation S402 , the logic control circuit 533 sets each of the bits of the digital signal DOUT to “0.” In an embodiment where the digital signal DOUT is an 8-bit signal, the digital signal DOUT will be set to “00000000.”

[0056] In operation S403, before performing the i-th comparison, the logic control circuit 533 sets the bit value of the bit corresponding to the i-th comparison among the multiple bits of the digital signal DOUT to "1" to generate the virtual voltage signal VVR for the i-th comparison. Figure 5 In the embodiment of the present invention, i can be any integer from 1 to 8.

[0057] For example, in the first comparison (corresponding to Figure 5 Before the time point T1 in FIG. 1 , the bit value of the first bit DOUT[7] (e.g., the highest bit) of the digital signal DOUT is set or switched to “1”. At this time, the digital signal DOUT is “10000000”. Figure 3 In the embodiment, the virtual voltage signal generating circuit 371 then performs voltage-to-current conversion according to the digital signal DOUT, the input voltage signal VIN and the output voltage signal VOUT to output a virtual voltage signal VVR for the first comparison.

[0058] In operation S404, the digital control circuit 353 obtains a comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. Figure 3 As shown, the sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP1 of the clock signal CLK (corresponding to the time point T1) to sample and hold the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR, and outputs the comparison signal CMP representing the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR to the logic control circuit 533. Figure 5 As shown, the disable level comparison signal CMP indicates that the voltage level of the virtual voltage signal VVR is greater than the voltage level of the low-side voltage signal VLS. In this case, operation S406 is performed.

[0059] In operation S406, the logic control circuit 533 determines that the bit value of the first bit of the digital signal DOUT (i.e., the bit corresponding to the first comparison among the plurality of bits) is "0". In some embodiments, the logic control circuit 533 is triggered by the rising edge of a pulse LP1 located after the time point T1 in the latch signal LATCH and sets the bit value of the first bit of the digital signal DOUT to "0" according to the comparison signal CMP of the disable level. Accordingly, operation S407 is performed.

[0060] In operation S407, the digital circuit 35 determines whether N judgments have been made. For example, the digital circuit 35 can count the number of pulses generated by the control signal PWM, the clock signal CLK, or the latch signal LATCH through a pulse counter (not shown) inside the clock control circuit 351, and can determine whether N judgments have been made based on the number of pulses generated. After the first comparison, the number of pulses counted by the clock control circuit 351 should be 1 (i.e., still not 8), so operations S403 and S404 are performed again.

[0061] like Figure 5 As shown, before the second comparison, the bit value of the second bit DOUT[6] in the digital signal DOUT is set or switched to "1". At this time, the digital signal DOUT is "01000000". It should be understood that the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the second comparison. The sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP2 of the clock signal CLK (corresponding to the time point T2) to output the comparison signal CMP of the disable level to the logic control circuit 533. In this case, operation S406 is performed again. Similarly, the logic control circuit 533 determines that the bit value of the second bit in the digital signal DOUT (i.e., the bit corresponding to the second comparison among the multiple bits) is "0", and is triggered by the rising edge of a pulse LP2 of the latch signal LATCH located after the time point T2 to set the bit value of the second bit in the digital signal DOUT to "0" according to the comparison signal CMP of the disable level. Accordingly, operation S407 is performed again. It should be understood that, since after the second comparison, the generated number counted by the clock control circuit 351 should be 2 (ie, still not 8), operations S403 and S404 are performed again.

[0062] Another example Figure 5 As shown, before the third comparison, the bit value of the third bit DOUT[5] in the digital signal DOUT is set or switched to "1". At this time, the digital signal DOUT is "00100000". It should be understood that the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the third comparison. The sampling and holding circuit 531 is triggered by the rising edge of one of the pulses CP3 of the clock signal CLK (corresponding to the time point T3) to output the comparison signal CMP of the enable level to the logic control circuit 533. Figure 5 As shown, the comparison signal CMP of the enable level indicates that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS. In this case, operation S405 is performed.

[0063] In operation S405, the logic control circuit 533 determines that the bit value of the third bit of the digital signal DOUT (i.e., the bit corresponding to the third comparison among the multiple bits) is "1", and is triggered by the rising edge of a pulse LP3 located after the time point T3 in the latch signal LATCH, and sets the bit value of the third bit of the digital signal DOUT to "1" according to the comparison signal CMP of the enable level. Accordingly, operation S407 is performed again. Similarly, after the third comparison, the generated number counted by the clock control circuit 351 should be 3 (i.e., still not 8), so operations S403 and S404 are performed again. It is noted that the digital signal DOUT is adjusted from "00000000" set in the second comparison to "00100000". Therefore, it can be seen that the adjustment amplitude is "00100000", which is "32" in decimal.

[0064] The 4th to 8th comparisons can be analogized based on the description of the 1st to 3rd comparisons, so only a brief description is given here. In the 4th comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated based on the digital signal DOUT set to "00110000") is less than the voltage level of the low-side voltage signal VLS at the time point T4 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the fourth bit DOUT[4] in the digital signal DOUT to "1" (corresponding to operation S405). It is noted that the digital signal DOUT is adjusted from "00100000" set in the 3rd comparison to "00110000". Therefore, it can be seen that the adjustment amplitude is "00010000", which is expressed as "16" in decimal.

[0065] In the fifth comparison, the digital control circuit 353 obtains a comparison result at time point T5 that the voltage level of the virtual voltage signal VVR (generated based on the digital signal DOUT set to "00111000") is greater than the voltage level of the low-side voltage signal VLS (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the fifth bit DOUT[3] in the digital signal DOUT to "0" (corresponding to operation S406).

[0066] In the sixth comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (generated according to the digital signal DOUT set to "00110100") is less than the voltage level of the low-side voltage signal VLS at the time point T6 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the sixth bit DOUT[2] in the digital signal DOUT to "1" (corresponding to operation S405). It is noted that the digital signal DOUT is adjusted from "00110000" set in the fifth comparison to "00110100". Therefore, it can be seen that the adjustment amplitude is "00000100", which is "4" in decimal.

[0067] In the 7th comparison, the digital control circuit 353 obtains a comparison result at time point T7 that the voltage level of the virtual voltage signal VVR (generated based on the digital signal DOUT set to "00110110") is greater than the voltage level of the low-side voltage signal VLS (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the seventh bit DOUT[1] in the digital signal DOUT to "0" (corresponding to operation S406).

[0068] In the 8th comparison, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR (which is generated according to the digital signal DOUT set to "00110101") is less than the voltage level of the low-side voltage signal VLS at the time point T8 (corresponding to operation S403 and operation S404), and accordingly sets or switches the bit value of the eighth bit DOUT[0] in the digital signal DOUT to "1" (corresponding to operation S405). Therefore, the digital signal DOUT is finally set to "00110101". It is noted that the digital signal DOUT is adjusted from "00110100" set in the 7th comparison to "00110101". Therefore, it can be seen that the adjustment amplitude is "00000001", which is expressed as "1" in decimal.

[0069] According to the above, in the binary mode, the digital signal DOUT is adjusted 4 times in total, and the adjustment amplitude of the digital signal DOUT is a non-constant value. For example, as the number of times the digital signal DOUT is adjusted increases, the adjustment amplitude changes from "32" to "16", from "16" to "4", and then from "4" to "1", that is, the adjustment amplitude gradually decreases.

[0070] According to the embodiment of the present case, the adjustment amplitude used by the digital circuit 35 to adjust or approximate the value of the digital signal DOUT in the binary mode gradually changes as the number of times the digital signal DOUT is adjusted increases. Specifically, in the binary mode, the adjustment amplitude used by the digital circuit 35 to adjust or approximate the digital signal DOUT can gradually decrease as the number of times the digital signal DOUT is adjusted increases.

[0071] In addition, after the 8th comparison, the digital circuit 35 determines that N comparisons have been performed (corresponding to operation S407). Figure 4 As shown, the clock control circuit 351 can switch the binary mode signal MBIN and the linear mode signal MLIN to the disable level and the enable level respectively, and the operation S401 is performed again.

[0072] In some embodiments of operation S401, Figure 6 As shown, the digital control circuit 353 in the digital circuit 35 controls the virtual current signal generating circuit 153 to operate in the linear mode according to the binary mode signal MBIN of the disable level and the linear mode signal MLIN of the enable level. In some embodiments, when the DC / DC converter of the present case is started, when the DC / DC converter of the present case wants to change the output voltage signal VOUT, or when the power stage circuit 10 is one of the phase circuits in the multi-phase DC voltage converter and is started, the digital control circuit 353 controls the virtual current signal generating circuit 153 to enter the linear mode and operate in the linear mode.

[0073] In accordance with the above description, in some embodiments, the clock control circuit 351 can count the number of pulses generated by the control signal PWM through another internal pulse counter (not shown in the figure), and judge whether the number of pulses generated reaches M (which is equivalent to judging whether M cycles CYC of the control signal PWM have passed). Specifically, M can be an integer greater than or equal to 2. Based on the above, if Figure 6 As shown, the clock control circuit 351 can control one of two adjacent pulses among multiple pulses of the clock signal CLK to be delayed by M cycles CYC compared to the other, and can control one of two adjacent pulses among multiple pulses of the latch signal LATCH to be delayed by M cycles CYC compared to the other.

[0074] Continue to explain Figure 4 Before operation S408 to operation S410 in the above, it should be noted that Figure 6 The multiple time points T9 to T12 in the figure respectively represent the execution time of comparing the low-side voltage signal VLS with the virtual voltage signal VVR. In addition, the digital signal DOUT set to "00110101" in the linear mode is Figure 6 It is represented in decimal as "53".

[0075] In some embodiments, operation S408 is responsive to Figure 6 The rising edge of a pulse in the clock signal CLK (corresponding to time point T9) is executed. In operation S408, Figure 3 The digital control circuit 353 in the embodiment obtains the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. For example, the digital control circuit 353 uses the sampling and holding circuit 531 to Figure 6 At time point T9 in the example, the comparison signal CMP of the enable level is generated (ie, indicating that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS). In this case, operation S409 is performed in response to Figure 6 The latch operation is performed at the rising edge of a pulse of the latch signal LATCH immediately following the time point T9.

[0076] In operation S409, the logic control circuit 533 adds "1" to the bit value of the lowest bit (i.e., the eighth bit) of the digital signal DOUT. It should be understood that adding "1" to the bit value of the lowest bit of the digital signal DOUT will cause the digital signal DOUT to change from "00110101" to "00110110", where "00110110" is "54" in decimal. Therefore, it can be seen that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is upward increase (+). Then, as described above, the virtual voltage signal generating circuit 371 uses this digital signal DOUT to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison.

[0077] After M cycles CYC, operation S408 responds to Figure 6 The rising edge of a pulse in the middle clock signal CLK (corresponding to the time point T10) is executed again. This time, the digital control circuit 353 still obtains the comparison result that the voltage level of the virtual voltage signal VVR is less than the voltage level of the low-side voltage signal VLS (corresponding to the comparison signal CMP of the enable level). Therefore, operation S409 is executed again. Accordingly, the digital signal DOUT changes from "00110110" to "00110111", where "00110111" is "55" in decimal. Therefore, it can be seen that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is upward increase (+). Then, the virtual voltage signal generating circuit 371 uses this digital signal DOUT again to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison.

[0078] After another M cycles CYC, operation S408 responds to Figure 6The rising edge of a pulse in the middle clock signal CLK (corresponding to the time point T11) is performed again. This time, the digital control circuit 353 obtains the comparison result that the voltage level of the virtual voltage signal VVR is greater than the voltage level of the low-side voltage signal VLS (corresponding to the comparison signal CMP of the disable level). Therefore, operation S410 is performed.

[0079] In operation S410, the logic control circuit 533 subtracts "1" from the bit value of the lowest bit of the digital signal DOUT, which changes the digital signal DOUT from "00110111" to "00110110", where "00110110" is "54" in decimal. Therefore, it can be seen that the adjustment amplitude is "00000001", which is "1" in decimal, and the adjustment direction is downward decrease (-). Then, the virtual voltage signal generating circuit 371 uses this digital signal DOUT again to output the virtual voltage signal VVR for the comparison circuit 33 to perform the next comparison. The operation of the virtual current signal generating circuit 153 after the time point T11 can be inferred based on the description of the aforementioned operations S408 to S410, so it is not repeated here.

[0080] According to the above, in the linear mode, the digital control circuit 353 adjusts the digital signal DOUT multiple times according to the comparison signal CMP, and the adjustment amplitude of the digital signal DOUT is a constant value, namely “1”, which does not change with the increase in the number of times the digital signal DOUT is adjusted.

[0081] At Figure 5 In the figure, trend line C1 is drawn by connecting multiple voltage levels of the low-side voltage signal VLS at multiple time points T1 to T8, and trend line C2 is drawn by connecting multiple voltage levels of the virtual voltage signal VVR at multiple time points T1 to T8. It can be seen from the trends of trend line C1 and trend line C2 that in binary mode, the digital circuit 35 sets the bit value of each bit of the digital signal DOUT through N comparisons of the virtual voltage signal VVR with the low-side voltage signal VLS (corresponding to the cycles CYC of the N control signals PWM), so that the virtual voltage signal VVR quickly approaches the low-side voltage signal VLS. Based on this, Figure 6As shown, in the linear mode, the comparison between the virtual voltage signal VVR and the low-side voltage signal VLS is only performed every M cycles CYC of the control signal PWM, so that the digital circuit 35 can fine-tune the digital signal DOUT according to the comparison result between the virtual voltage signal VVR and the low-side voltage signal VLS (i.e., only adjust the bit value of the lowest bit of the digital signal DOUT). This approach allows the virtual voltage signal VVR to remain close to the low-side voltage signal VLS in the linear mode, but will not change all the time (thus saving energy consumption). It can be seen that, regardless of whether in the binary mode or the linear mode, the digital circuit 35 is used to adjust the digital signal DOUT according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR.

[0082] In some embodiments, Figure 3 The clock control circuit 351 can determine whether to perform a reload operation according to the voltage level of the reload signal RL. For example, when the reload signal RL is at the enable level, the clock control circuit 351 will immediately switch the binary mode signal MBIN and the linear mode signal MLIN to the enable level and the disable level respectively, so that the virtual current signal generating circuit 153 re-enters the binary mode operation (i.e., operation S402 to operation S407). When the reload signal RL is at the disable level, the clock control circuit 351 does not change (or maintain) the current voltage levels of the binary mode signal MBIN and the linear mode signal MLIN, so that the virtual current signal generating circuit 153 maintains the operation in the current mode.

[0083] In the above embodiment, since M is an integer greater than or equal to 2, the comparison circuit 33 is equivalent to comparing the low-side voltage signal VLS with the virtual voltage signal VVR at intervals according to the time of at least two cycles CYC of the control signal PWM (also referred to as the first time) in the linear mode. Similarly, in the binary mode, the comparison circuit 33 compares the low-side voltage signal VLS with the virtual voltage signal VVR at intervals according to the time of at least one cycle CYC of the control signal PWM (also referred to as the second time). It can be seen that the first time is longer than the second time.

[0084] In the above embodiment, it can also be understood that the digital control circuit 353 is used to sample and hold the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR by being triggered by the clock signal CLK of the enable level, and is used to set the bit value of one of the multiple bits of the digital signal DOUT according to the comparison result of the low-side voltage signal VLS and the virtual voltage signal VVR by being triggered by the latch signal LATCH of the enable level.

[0085] In the above embodiment, if Figure 5 and Figure 6As shown, each cycle CYC of the control signal PWM includes an enabling period PON and a disabling period POFF. Figure 5 As shown, when the binary mode signal MBIN and the linear mode signal MLIN are at the enable level and the disable level respectively, the clock signal CLK and the latch signal LATCH are sequentially switched to the enable level during each disable period POFF of the control signal PWM.

[0086] In addition, in some embodiments, Figure 6 As shown, when the binary mode signal MBIN and the linear mode signal MLIN are at the disable level and the enable level respectively, after the clock signal CLK and the latch signal LATCH are sequentially switched to the enable level for the first time, they will be sequentially switched to the enable level again every at least two cycles CYC of the control signal PWM.

[0087] By the above Figures 4 to 6 As can be seen from the description of the embodiments, the present invention also provides a method for generating a virtual current signal IVR. Figure 7 , Figure 7 FIG. 7 is a flow chart of a method 700 for generating a virtual current signal according to some embodiments of the present invention. In some embodiments, Figure 7 As shown, the virtual current signal generating method 700 includes a plurality of operations S701-S705. Figure 1 to Figure 6 Description of the Embodiments The number of operations and / or the order of operations of the virtual current signal generating method 700 are increased, decreased and / or adjusted.

[0088] In some embodiments, such as Figure 7 As shown, operation S701 is performed after the power stage circuit 10 is turned on. In operation S701, the driving circuit 13 drives the switch circuit 11 according to the control signal PWM. The description of operation S701 is similar to Figure 1 The description of the embodiments is therefore omitted here.

[0089] In operation S702, the virtual current signal generating circuit 153 determines whether the power stage circuit 10 enters the binary mode or the linear mode according to the binary mode signal MBIN and the linear mode signal MLIN. The description of operation S701 is similar to Figure 4 The description of operation S401 is omitted here.

[0090] In some embodiments, the power stage circuit 10 enters the binary mode, and thus operation S703 is performed. In operation S703, the digital circuit 35 in the virtual current signal generating circuit 153 adjusts the digital signal DOUT multiple times with the first adjustment amplitude according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. The description of operation S703 is similar to Figure 5 In one embodiment, the first adjustment amplitude is variable (ie, non-fixed), and in detail, the first adjustment amplitude gradually changes, for example, gradually decreases, as the number of times the digital signal DOUT is adjusted increases.

[0091] In some embodiments, the power stage circuit 10 enters the linear mode, and thus operation S704 is performed. In operation S704, the digital circuit 35 in the virtual current signal generating circuit 153 adjusts the digital signal DOUT multiple times with the second adjustment amplitude according to the comparison result between the low-side voltage signal VLS and the virtual voltage signal VVR. The description of operation S704 is similar to Figure 6 The description of the embodiment is omitted here. In one embodiment, the second adjustment range is a constant value.

[0092] In operation S705, the signal conversion circuit 37 in the virtual current signal generating circuit 153 adjusts the virtual voltage signal VVR according to the adjusted digital signal DOUT, and generates a virtual current signal IVR according to the adjusted virtual voltage signal VVR. By adjusting the digital signal DOUT, the virtual voltage signal VVR is adjusted to gradually approach the low-side voltage signal VLS. In this way, based on the adjustment of the virtual voltage signal VVR, the virtual current signal IVR can be corrected to gradually approach the output current signal IL. The description of operation S705 is similar to Figure 5 and Figure 6 The description of the embodiments is therefore omitted here.

[0093] After operation S705 , the virtual current signal generating method 700 returns to operation S702 to continue adjusting the digital signal DOUT in the binary mode or the linear mode.

[0094] According to the above-mentioned virtual current signal generating method 700, by adjusting the digital signal DOUT and the virtual voltage signal VVR in the binary mode and / or the linear mode, the virtual current signal IVR can be further calibrated so that the virtual current signal IVR is substantially close to the output current signal IL, or substantially the same as the output current signal IL.

[0095] From the above embodiments of the present invention, it can be known that the virtual current signal IVR proportional to the output current signal IL is generated by the virtual current signal generating circuit 153, and the power stage circuit 10 of the present invention can complete current sensing during the conduction period LON of the low-side switch Q2, and can combine the virtual current signal IVR with the low-side current signal ILS obtained by current sensing to generate the current monitoring signal IMON. It is worth noting that the current monitoring signal IMON generated by this method can be suitable for applications with low duty cycles.

[0096] In addition, compared with some related technologies, the current monitoring circuit 15 of the present invention significantly saves the number of components, and can digitally adjust the virtual voltage signal VVR to correct the virtual current signal IVR and ensure the stability of the virtual current signal IVR. Therefore, the power stage circuit 10 and the current monitoring circuit 15 of the present invention have the advantages of low cost, suitable for low duty cycle applications, and generating a current monitoring signal with high stability and high accuracy.

[0097] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the attached claims.

[0098]

Explanation of symbols

[0099] 10: Power stage circuit

[0100] 11: Switching circuit

[0101] 13: Driving circuit

[0102] 15: Current monitoring circuit

[0103] 20: Controller

[0104] 31: Current to voltage circuit

[0105] 33: Comparison Circuit

[0106] 35: Digital Circuits

[0107] 37:Signal conversion circuit

[0108] 151: Current sensing circuit

[0109] 153: Virtual current signal generating circuit

[0110] 155:Signal combining circuit

[0111] 351: Clock control circuit

[0112] 353: Digital Control Circuit

[0113] 371: Virtual voltage signal generating circuit

[0114] 373: Voltage to Current Circuit

[0115] 400: Adjustment method

[0116] 531: Sample and hold circuit

[0117] 533:Logic control circuit

[0118] 700: Virtual current signal generation method

[0119] C37, COUT: capacitor element

[0120] CLK: Clock signal

[0121] CMP: Comparison signal

[0122] CP1,CP2,CP3,LP1,LP2,LP3:Pulse

[0123] CYC: Cycle

[0124] DAC1: The first digital-to-analog converter circuit

[0125] DAC2: Second digital-to-analog conversion circuit

[0126] DOUT: digital signal

[0127] DOUT[0]~DOUT[7]: bit

[0128] GH: High side drive signal

[0129] GL: low side drive signal

[0130] GND: Ground voltage

[0131] HON,LON: conduction period

[0132] IL: Output current signal

[0133] ILS: Low-side current signal

[0134] IMON: Current monitoring signal

[0135] IVR: Virtual Current Signal

[0136] L: Inductor

[0137] LATCH: latch signal

[0138] MBIN: Binary Mode Signal

[0139] MLIN: Linear Mode Signal

[0140] N1, SW: output terminal

[0141] P1: First period

[0142] P2: Second period

[0143] POFF: Disable period

[0144] PON: Enable Period

[0145] POR: Power-on reset voltage signal

[0146] PWM: control signal

[0147] Q1: High-side switch

[0148] Q2: Low-side switch

[0149] R1: Resistor

[0150] RL: Reload signal

[0151] S1: First switch

[0152] S2: Second switch

[0153] S401~S410, S701~S705: Operation

[0154] SA: First current signal

[0155] SB: Second current signal

[0156] SL: Load side

[0157] T1~T12: Time point

[0158] VIN: Input voltage signal

[0159] VLS: Low side voltage signal

[0160] VOUT: output voltage signal

[0161] VREF: reference voltage signal

[0162] VVR: virtual voltage signal.

Claims

1. A power stage circuit, characterized in that: Include: A switch circuit, coupled to the output end of the power stage circuit, for receiving an input voltage signal, and comprising a high-side switch and a low-side switch, wherein the output end is coupled to the load end via an inductor element; A driving circuit coupled to the switch circuit and used to drive the switch circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element; as well as Current monitoring circuit, including: A current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal; a virtual current signal generating circuit, coupled to the current sensing circuit, for generating a low-side voltage signal according to the low-side current signal, for generating a digital signal, for adjusting the digital signal according to a comparison result between the low-side voltage signal and the virtual voltage signal, for adjusting the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and for generating a virtual current signal according to the virtual voltage signal; as well as A signal combining circuit is coupled to the current sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the linear mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a first time. In the linear mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude according to a comparison result between the low-side voltage signal and the virtual voltage signal, and the first adjustment amplitude is a constant value.

2. The power stage circuit according to claim 1, characterized in that: The virtual current signal generating circuit is used to adjust the bit value of the least significant bit of the digital signal with the first adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the change amount of the bit value of the least significant bit of the digital signal corresponds to the first adjustment amplitude.

3. The power stage circuit according to claim 2, characterized in that: When the voltage level of the virtual voltage signal is lower than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to add the first adjustment amplitude to the bit value of the least significant bit. When the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to subtract the first adjustment amplitude from the bit value of the least significant bit.

4. The power stage circuit according to claim 1, characterized in that: In the binary mode, the virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal at intervals according to a second time. In the binary mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude according to the comparison result between the low-side voltage signal and the virtual voltage signal, and the second adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases.

5. The power stage circuit according to claim 4, characterized in that: The first time is longer than the second time.

6. The power stage circuit according to claim 4, characterized in that: The virtual current signal generating circuit is used to compare the low-side voltage signal with the virtual voltage signal N times in the binary mode, wherein N is the number of bits of the digital signal. Before performing one of the N comparisons, the virtual current signal generating circuit is used to switch the corresponding one of the N bits of the digital signal from a first value to a second value to generate the virtual voltage signal used for the one of the N comparisons, and to determine the bit value of the corresponding one of the N bits according to the comparison result of the one of the N comparisons.

7. The power stage circuit according to claim 6, characterized in that: When the voltage level of the virtual voltage signal is lower than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the second value. When the voltage level of the virtual voltage signal is greater than the voltage level of the low-side voltage signal, the virtual current signal generating circuit is used to determine that the bit value of the corresponding one of the N bits is the first value.

8. The power stage circuit according to claim 1, characterized in that: The first time is at least two cycles of the control signal.

9. A power stage circuit, characterized in that: Include: A switch circuit, coupled to the output end of the power stage circuit, for receiving an input voltage signal, and comprising a high-side switch and a low-side switch, wherein the output end is coupled to the load end via an inductor element; A driving circuit coupled to the switch circuit and used to drive the switch circuit according to a control signal to generate an output voltage signal at the load end and generate an output current signal via the inductor element; as well as Current monitoring circuit, including: A current sensing circuit is coupled to the switch circuit and is used to sense the output current signal during each conduction period of the low-side switch to generate a low-side current signal; a virtual current signal generating circuit, coupled to the current sensing circuit, for generating a low-side voltage signal according to the low-side current signal, for generating a digital signal, for adjusting the digital signal according to a comparison result between the low-side voltage signal and the virtual voltage signal in a first mode or a second mode, for adjusting the virtual voltage signal according to the digital signal so that the virtual voltage signal is close to the low-side voltage signal, and for generating a virtual current signal according to the virtual voltage signal; as well as A signal combining circuit is coupled to the current sensing circuit and the virtual current signal generating circuit, and is used to generate a current monitoring signal according to the low-side current signal and the virtual current signal. In the first mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a first adjustment amplitude, and the first adjustment amplitude gradually changes as the number of times the digital signal is adjusted increases. In the second mode, the virtual current signal generating circuit adjusts the digital signal multiple times with a second adjustment amplitude, and the second adjustment amplitude is a constant.

10. The power stage circuit according to claim 9, characterized in that: The virtual current signal generating circuit comprises: A current-to-voltage circuit is coupled to the current sensing circuit and is used to convert the low-side current signal into the low-side voltage signal; A comparison circuit, coupled to the current-to-voltage circuit, and used to compare the low-side voltage signal with the virtual voltage signal; A digital circuit, coupled to the comparison circuit, for generating the digital signal, and for adjusting the digital signal according to a comparison result between the low-side voltage signal and the virtual voltage signal in the first mode or the second mode; as well as The signal conversion circuit is coupled to the digital circuit and the comparison circuit, and is used to receive the digital signal, the input voltage signal and the output voltage signal, and to generate the virtual voltage signal according to the digital signal, the input voltage signal and the output voltage signal to generate the virtual current signal.

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