Novel LTPO-LCD array substrate structure

Abstract

The utility model provides a novel LTPO-LCD array substrate structure which comprises a GIP area and a display area, a first semiconductor layer and a pixel electrode layer are prepared on a buffer layer in a synchronous patterning mode, and the first semiconductor layer and the pixel electrode layer are both made of Poly-Si materials in a conductor mode. The display area further comprises a second gate metal layer, a second gate insulating layer, a second semiconductor layer, a second source drain electrode layer, a second insulating layer and a common electrode layer. The second gate metal layer and the pixel electrode layer are designed on the same layer, a second semiconductor layer and a second source and drain electrode layer are prepared on the second gate insulating layer in sequence, the second semiconductor layer is located above the second gate metal layer, and the second source and drain electrode layer is in lap joint with the second semiconductor layer and is in lap joint with the pixel electrode layer through a DC hole at the same time. The novel LTPO-LCD array substrate structure provided by the utility model has the advantages that the structure is simple, a mask process and a PVD (Physical Vapor Deposition) process of pixel electrode coating can be reduced, and an insulating layer can be reduced.

Description

Technical Field

[0001] The utility model relates to a TFT array substrate, in particular to a novel LTPO-LCD array substrate structure. Background Art

[0002] The LTPO substrate contains both metal oxide thin-film transistors and low-temperature polycrystalline silicon thin-film transistors, so the panel can have both strong driving capability and low power consumption, and has become a hot technology in display panels.

[0003] However, the structure of the GIP region of the existing array substrate is, from bottom to top, the first semiconductor layer, the first gate insulating layer, the first gate metal layer, the interlayer isolation layer, the first source-drain electrode layer and the first insulating layer, and the structure of the display region is, from bottom to top, the second gate metal layer, the second gate insulating layer, the second semiconductor layer, the second source-drain electrode layer and the second insulating layer, and a flat layer, a common electrode layer, a third insulating layer and a pixel electrode layer are prepared on the first insulating layer and the second insulating layer of the GIP region and the display region. In the LTPS process, the interlayer isolation layer ILD usually uses a SiNx structure, and the SiNx film has a high H ion content. In the subsequent annealing process, the movement of H ions can play a role in repairing the poly-Si channel lattice and improving the SS of the device; but IGZO-TFT is more sensitive to H ions, and the movement of a large number of H ions can easily cause the Vth drift and stability deterioration of the metal oxide semiconductor device. Therefore, it is necessary to reduce the influence of H ion diffusion on the electrical properties and stability of the metal oxide semiconductor device in the LTPS process.

[0004] At the same time, the existing LTPO process, which includes both metal oxide thin-film transistors and low-temperature polysilicon thin-film transistors, forms the required patterns on each film layer through a mask process. A large number of masks are required, which makes the process of preparing the array substrate too complicated, and the process cost and process complexity are very high. Summary of the invention

[0005] The technical problem to be solved by the utility model is to provide a new LTPO-LCD array substrate structure with a simple structure, which can reduce a mask plate process, a PVD process for pixel electrode coating and a insulating layer.

[0006] The utility model is implemented as follows: a novel LTPO-LCD array substrate structure, comprising a substrate, a buffer layer prepared on the substrate, a GIP region and a display region on the buffer layer, a first semiconductor layer and a pixel electrode layer are synchronously patterned on the buffer layer, the first semiconductor layer and the pixel electrode layer are respectively located on the GIP region and the display region, the first semiconductor layer and the pixel electrode layer are both made of a conductor made of Poly-Si material, and the display region also includes a second gate metal layer, a second gate insulating layer, a second semiconductor layer, a second source-drain electrode layer, a second insulating layer and a common electrode layer; the second gate The gate metal layer is located on the buffer layer on the display area and is designed in the same layer as the pixel electrode layer, the second gate insulating layer covers the pixel electrode layer and the second gate metal layer, and a DC hole is opened on the second gate insulating layer; the second semiconductor layer and the second source-drain electrode layer are sequentially prepared on the second gate insulating layer, the second semiconductor layer is located above the second gate metal layer, the second source-drain electrode layer overlaps the second semiconductor layer, and at the same time overlaps the pixel electrode layer through the DC hole; the second insulating layer covers the second gate insulating layer, the second source-drain electrode layer and the second semiconductor layer; the common electrode layer is located on the second insulating layer.

[0007] Furthermore, the first semiconductor layer located in the GIP area includes a channel area in the middle and conductive areas on both sides, and a first gate insulating layer and a first gate metal layer are sequentially prepared on the channel area, and the orthographic projections of the first gate insulating layer and the first gate metal layer on the substrate completely overlap with the orthographic projections of the channel area on the substrate; an interlayer isolation layer covering the first semiconductor layer, the first gate insulating layer and the first gate metal layer, the interlayer isolation layer having a first via and a second via exposing the conductive area of ​​the first semiconductor layer, a first source-drain electrode layer is prepared on the interlayer isolation layer, and the first source-drain electrode layer is connected to the conductive area of ​​the first semiconductor layer through the first via and the second via; a first insulating layer is made on the interlayer isolation layer, and the first insulating layer covers the interlayer isolation layer and the first source-drain electrode layer.

[0008] The advantages of the utility model are: the utility model uses Poly-Si material and the same mask plate to form the pixel electrode layer and the first semiconductor layer during film coating, so that it not only reduces one PVD process for pixel electrode coating, but also reduces one Mask process, saving costs, and compared with the prior art, there is no need to prepare a third insulating layer. The utility model provides a new LTPO-LCD array substrate structure with a simple structure, which can reduce one mask plate process, one PVD process for pixel electrode coating, and one insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0010] Figure 1 It is a structural schematic diagram of the utility model.

[0011] Figure 2 Schematic diagram of the structure after poly-Si film preparation.

[0012] Figure 3 This is a schematic diagram of the structure after the poly Si film layer is conductively treated.

[0013] Figure 4 Schematic diagram of the structure of printing a layer of high-temperature resistant polyimide film for the display area.

[0014] Figure 5 A schematic diagram of the structure was prepared for the GIP region.

[0015] Figure 6 Schematic diagram of the structure of the polyimide in the display area undergoing peeling treatment.

[0016] Figure 7 Schematic diagram of the structure in which the second semiconductor layer in the display area is prepared.

[0017] Figure 8 Schematic diagram of the structure in which the second source-drain electrode layer in the display area is prepared.

[0018] Explanation of the accompanying drawings: substrate 1, buffer layer 2, GIP region 3, first semiconductor layer 31, channel region 311, conductive region 312, first gate insulating layer 32, first gate metal layer 33, interlayer isolation layer 34, first via 341, second via 342, first source-drain electrode layer 35, first insulating layer 36, display region 4, pixel electrode layer 41, second gate metal layer 42, second gate insulating layer 43, DC hole 431, second semiconductor layer 44, second source-drain electrode layer 45, second insulating layer 46, common electrode layer 47, polyimide film 100. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0020] The technical solution in the embodiment of the utility model is to solve the above-mentioned shortcomings, and the overall idea is as follows: the utility model uses Poly-Si material and uses the same mask plate to form the pixel electrode layer 41 and the first semiconductor layer 31 during coating, so that it not only reduces one PVD process for pixel electrode coating, but also reduces one Mask process, saving costs. Compared with the prior art, there is no need to prepare a third insulating layer between the common electrode layer and the pixel electrode layer, thereby reducing the preparation of one insulating layer.

[0021] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0022] like Figure 1 As shown, a preferred embodiment of the utility model is a novel LTPO-LCD array substrate structure, including a substrate 1, a buffer layer 2 is prepared on the substrate 1, and the buffer layer 2 includes a GIP area 3 and a display area 4, and a first semiconductor layer 31 and a pixel electrode layer 41 are synchronously patterned on the buffer layer 2, and the first semiconductor layer 31 and the pixel electrode layer 41 are both made of conductive Poly-Si material, and the first semiconductor layer 31 and the pixel electrode layer 41 are respectively located on the GIP area 3 and the display area 4, and the first semiconductor layer 31 located in the GIP area 3 includes a channel area 311 in the middle and conductive areas 312 on both sides, and a first gate insulating layer 32 and a first gate metal layer 33 are sequentially prepared on the channel area 311, and the first gate The orthographic projections of the insulating layer 32 and the first gate metal layer 33 on the substrate 1 completely overlap with the orthographic projections of the channel region 311 on the substrate 1; an interlayer isolation layer 34 covering the first semiconductor layer 31, the first gate insulating layer 32 and the first gate metal layer 33, the interlayer isolation layer 34 having a first via 341 and a second via 342 exposing the conductive region 312 of the first semiconductor layer 31, a first source-drain electrode layer 35 prepared on the interlayer isolation layer 34, the first source-drain electrode layer 35 being connected to the conductive region 312 of the first semiconductor layer 31 through the first via 341 and the second via 342; a first insulating layer 36 is formed on the interlayer isolation layer 34, the first insulating layer 36 covers the interlayer isolation layer 34 and the first source-drain electrode layer 35.

[0023] The display area 4 also includes a second gate metal layer 42, a second gate insulating layer 43, a second semiconductor layer 44, a second source-drain electrode layer 45, a second insulating layer 46 and a common electrode layer 47; the second gate metal layer 42 is located on the buffer layer 2 of the display area 4 and is designed in the same layer as the pixel electrode layer 41, the second gate insulating layer 43 covers the pixel electrode layer 41 and the second gate metal layer 42, and a DC hole 431 is opened on the second gate insulating layer 43; the second semiconductor layer 44 and the second source-drain electrode layer 45 are sequentially prepared on the second gate insulating layer 43, the second semiconductor layer 44 is located above the second gate metal layer 42, the second source-drain electrode layer 45 overlaps the second semiconductor layer 44, and at the same time overlaps the pixel electrode layer 41 through the DC hole 431; the second insulating layer 46 covers the second gate insulating layer 43, the second source-drain electrode layer 45 and the second semiconductor layer 44; the common electrode layer 47 is located on the second insulating layer 46.

[0024] The preparation method comprises the following steps:

[0025] Step 1: Figure 2 As shown, a buffer layer 2 is prepared on a substrate 1, and the buffer layer 2 includes a GIP region 3 and a display region 4. The GIP region 3 is an LTPS type TFT, which adopts a top gate self-aligned structure; the display region 4 is a metal oxide semiconductor type TFT, which adopts a BCE structure; a poly Si film layer is deposited on the buffer layer 2 using a Poly-Si material, and the same photomask is used to develop on the GIP region 3 and the display region 4 to form a first poly Si film layer 31 and a second poly Si film layer 41;

[0026] Step 2: Figure 3 As shown, the Poly Si film layer is subjected to conductor processing: ① in the GIP region 3, the middle part of the first poly Si film layer 31 is subjected to non-laser annealing processing to form a channel region 311; ② the first poly Si film layer 31 located on both sides of the channel region 311 in the GIP region 3 is subjected to laser annealing processing to form a conductor region 312, so that the first poly Si film layer 31 forms a first semiconductor layer 31; ③ in the display region 4, the second poly Si film layer 41 is subjected to laser annealing processing to form a conductor region, so that the second poly Si film layer 41 forms a pixel electrode layer 41;

[0027] Step 3: Figure 4 As shown, a layer of high temperature resistant polyimide film 100 is prepared on the display area 4 by using printing technology;

[0028] Step 4: Figure 5As shown, a first gate insulating layer (GI) 32, a first gate metal layer 33 (GE), an interlayer isolation layer 34 (ILD), a first source-drain electrode layer (SD) 35 and a first insulating layer 36 (PV) are sequentially formed on the GIP region 3, and the above-mentioned film layers in the preparation of the GIP region 3 are plated on the polyimide film 100;

[0029] Step 5: Figure 6 As shown, after the film process of the GIP region 3 is completed, the polyimide film 100 is dry-etched or laser-processed to peel off the polyimide film 100 and the film layer above it, so that the LTPS-TFT H ion diffusion process is only completed in the GIP region 3, avoiding affecting the electrical properties and stability of the IGZO device in the display region 4;

[0030] Step 6: Figure 7 As shown, a second gate metal layer 42, a second gate insulating layer 43 and a second semiconductor layer 44 are sequentially completed on the display area 4;

[0031] Step 7: Figure 8 As shown, a DC hole 431 is opened on the second gate insulating layer 43, and the second semiconductor layer 44 and the second source-drain electrode layer 45 are sequentially prepared on the second gate insulating layer 43, and the second source-drain electrode layer 45 overlaps the second semiconductor layer 44, and overlaps the pixel electrode layer 41 through the DC hole 431;

[0032] Step 8: Figure 1 As shown, a second insulating layer 46 and a common electrode layer 47 are sequentially prepared on the second source-drain electrode layer 45 to complete the LTPO-LCD array substrate structure of the present invention.

[0033] The utility model uses Poly-Si material and the same mask plate to form the pixel electrode layer and the first semiconductor layer during film coating, thereby reducing not only one PVD process for pixel electrode film coating, but also one Mask process, saving costs, and compared with the prior art, there is no need to prepare a third insulating layer, reducing the thickness of the array substrate. The utility model provides a new LTPO-LCD array substrate structure with a simple structure, which can reduce one mask plate process, one PVD process for pixel electrode film coating, and one insulating layer.

[0034] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A novel LTPO-LCD array substrate structure, comprising a substrate, a buffer layer is prepared on the substrate, the buffer layer comprises a GIP area and a display area, characterized in that: A first semiconductor layer and a pixel electrode layer are simultaneously patterned on the buffer layer, the first semiconductor layer and the pixel electrode layer are respectively located on the GIP area and the display area, the first semiconductor layer and the pixel electrode layer are both made of conductive Poly-Si material, and a second gate metal layer, a second gate insulating layer, a second semiconductor layer, a second source-drain electrode layer, a second insulating layer and a common electrode layer are sequentially prepared in the display area; the second gate metal layer is located on the buffer layer in the display area and is designed in the same layer as the pixel electrode layer, the second gate insulating layer covers the pixel electrode layer and the second gate metal layer, and a DC hole is provided on the second gate insulating layer; the second semiconductor layer and the second source-drain electrode layer are sequentially prepared on the second gate insulating layer, the second semiconductor layer is located above the second gate metal layer, the second source-drain electrode layer overlaps the second semiconductor layer, and at the same time overlaps the pixel electrode layer through the DC hole; the second insulating layer covers the second gate insulating layer, the second source-drain electrode layer and the second semiconductor layer; the common electrode layer is located on the second insulating layer.

2. The novel LTPO-LCD array substrate structure according to claim 1, characterized in that: The first semiconductor layer located in the GIP region includes a channel region in the middle and conductive regions on both sides, a first gate insulating layer and a first gate metal layer are sequentially prepared on the channel region, and the orthographic projections of the first gate insulating layer and the first gate metal layer on the substrate completely overlap with the orthographic projections of the channel region on the substrate; an interlayer isolation layer covering the first semiconductor layer, the first gate insulating layer and the first gate metal layer, the interlayer isolation layer having a first via hole and a second via hole exposing the conductive region of the first semiconductor layer, a first source-drain electrode layer is prepared on the interlayer isolation layer, and the first source-drain electrode layer is connected to the conductive region of the first semiconductor layer through the first via hole and the second via hole; A first insulating layer is formed on the interlayer isolation layer, and the first insulating layer covers the interlayer isolation layer and the first source-drain electrode layer.

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