Device

Abstract

The present disclosure relates to a device. Various embodiments of a wafer include a polycrystalline silicon carbide (SiC) layer or a base substrate. The polycrystalline silicon carbide (SiC) layer may have a resistivity less than or equal to 2 mohm-cm (milliohm-cm) such that the polycrystalline silicon carbide layer is a low resistivity polycrystalline silicon carbide layer. The polycrystalline silicon carbide layer may have crystal grains having a grain size of less than or equal to 1 mm, and may have a non-columnar structure. The polycrystalline silicon carbide layer may have a warpage of less than or equal to 75 [mu] m ([mu] m). A single crystal silicon carbide (SiC) layer may be coupled to a polycrystalline silicon carbide (SiC) layer through a bonding layer. The monocrystalline silicon carbide layer may be thinner than the polycrystalline silicon carbide layer.

Description

Technical Field

[0001] The present disclosure relates to silicon carbide based substrates and wafers having low resistivity and low warpage. Background Art

[0002] The semiconductor industry has been showing considerable interest in silicon carbide (SiC), particularly for use in the manufacture of electronic devices or components (eg, diodes, transistors, or other similar power applications).

[0003] The development and manufacture of silicon carbide based electronic devices is limited by factors such as the electrical and mechanical properties when the silicon carbide wafer is formed. Many silicon carbide wafers are manufactured with a resistivity greater than what is beneficial for the final product. Another problem is the amount of warpage that stems from the manufacture of the wafer. The higher resistivity limits the ability of electrical signals to travel through the silicon carbide wafer. The higher amount of warpage leads to defects such as from the polishing process when the end electronic device is manufactured, or to an increased number of wafers or substrates that are cracked or broken during handling and manufacturing.

[0004] These polycrystalline SiC wafers can be manufactured by a method of bonding a single crystal wafer on a polycrystalline SiC wafer. For example, there is a wafer manufacturing method in which a polycrystalline SiC wafer is bonded and integrated with a single crystal SiC wafer by direct bonding. In power devices, these crystal defects, high resistivity, and high warpage may be problematic because these factors limit the function of the power device, causing the function of the power device to exceed the selected tolerance. In this case, these devices may be disposed of (e.g., thrown away), resulting in increased manufacturing costs due to reduced yield. Utility Model Content

[0005] One aspect of the present disclosure provides a device, comprising:

[0006] A polycrystalline silicon carbide (SiC) wafer having a resistivity of less than or equal to 2 mohm-cm (milliohm-cm), wherein the polycrystalline silicon carbide comprises a silicon carbide wafer having a resistivity of less than or equal to 20 angstroms and a single crystal silicon carbide (SiC) wafer coupled to the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0007] According to at least one embodiment of the present disclosure, the device further includes a bonding layer on the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0008] According to at least one embodiment of the present disclosure, the single crystal silicon carbide (SiC) wafer is located on the bonding layer on the surface of the polycrystalline silicon carbide (SiC) wafer and is coupled to the first surface of the polycrystalline silicon carbide (SiC) wafer through the bonding layer.

[0009] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) wafer includes: a second surface, the second surface is opposite to the first surface of the polycrystalline silicon carbide (SiC) layer; and a first size, the first size extending from the second surface to the first surface; the single crystal silicon carbide (SiC) wafer includes: a third surface, the third surface faces the first surface of the polycrystalline silicon carbide (SiC) wafer; a fourth surface, the fourth surface is away from the third surface and opposite to the third surface; and a second size, the second size extends from the third surface to the fourth surface, and the second size is different from the first size.

[0010] According to at least one embodiment of the present disclosure, the second size is smaller than the first size.

[0011] According to at least one embodiment of the present disclosure, the first size is less than 1000 μm (micrometer); and the second size is less than or equal to 1 μm (micrometer).

[0012] According to at least one embodiment of the present disclosure, the single crystal silicon carbide (SiC) wafer is physically bonded directly to the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0013] According to at least one embodiment of the present disclosure, the resistivity is less than or equal to 1 mohm-cm (milliohm-centimeter).

[0014] According to at least one embodiment of the present disclosure, the warpage of the polycrystalline silicon carbide (SiC) wafer is less than 75 μm (micrometers).

[0015] According to at least one embodiment of the present disclosure, the warpage of the polycrystalline silicon carbide (SiC) wafer is less than 45 μm (micrometers).

[0016] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) wafer has a non-columnar structure.

[0017] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) wafer includes grains less than or equal to 1 mm (millimeter).

[0018] Another aspect of the present disclosure provides a device, characterized in that the device includes: a substrate, the substrate includes: a polycrystalline silicon carbide (SiC) layer, the polycrystalline silicon carbide (SiC) layer includes: a first surface; a second surface, the second surface is opposite to the first surface; a first size, the first size extends from the first surface to the second surface; and a resistivity less than or equal to 2mohm-cm (milliohm-centimeter); a single crystal silicon carbide (SiC) layer, the single crystal silicon carbide (SiC) layer is coupled to the second surface of the polycrystalline silicon carbide (SiC) layer, including: a third surface, the third surface is located on the second surface of the polycrystalline silicon carbide (SiC) layer; a fourth surface, the fourth surface is opposite to the third surface; and a second size, the second size extends from the third surface to the fourth surface, the third surface of the single crystal silicon carbide (SiC) layer is located on the bonding layer and faces the first surface of the polycrystalline silicon carbide (SiC) layer, and the second size is smaller than the first size.

[0019] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) layer includes grains less than or equal to 1 mm (millimeter).

[0020] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) layer has a non-columnar structure.

[0021] Yet another aspect of the present disclosure provides a device, characterized in that the device comprises: a polycrystalline silicon carbide substrate, the polycrystalline silicon carbide substrate comprising: a first surface; a second surface, the second surface being opposite to the first surface; a thickness extending from the first surface to the second surface, the thickness being greater than or equal to 150 μm (micrometers); a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter); and a warpage less than 75 μm.

[0022] According to at least one embodiment of the present disclosure, the resistivity is less than or equal to 1 mohm-cm (milliohm-centimeter).

[0023] According to at least one embodiment of the present disclosure, the polycrystalline silicon carbide (SiC) substrate includes grains less than or equal to 1 mm (millimeter) and has a non-columnar structure.

[0024] According to at least one embodiment of the present disclosure, the warpage is less than or equal to 75 μm (micrometers).

[0025] According to at least one embodiment of the present disclosure, the thickness is at least one of the following: between 150-1000 μm (micrometers), equal to 150 μm (micrometers), and equal to 1000 μm (micrometers).

[0026] Polycrystalline SiC wafers with low resistivity are beneficial to the function of electronic devices in which the polycrystalline SiC wafers are present. The present disclosure is directed to providing at least one embodiment of a wafer including a polycrystalline silicon carbide wafer or substrate having low resistivity and low warpage. Electronic devices or components made from the wafer are further optimized when used and have few crystal defects. Compared to existing SiC wafers, wafers formed according to embodiments of the present disclosure have low or very low resistivity.

[0027] At least one embodiment includes a wafer including a polycrystalline silicon carbide (SiC) wafer or substrate having a resistivity less than or equal to 2 mohm-cm (milliohm-cm) and a warpage less than or equal to 75 μm (micrometers). In some embodiments, the wafer may include a bonding region between the polycrystalline silicon carbide (SiC) wafer and a single crystal silicon carbide (SiC) wafer, the single crystal silicon carbide (SiC) wafer being coupled to the polycrystalline silicon carbide (SiC) wafer through the bonding region. The low resistivity of the polycrystalline silicon carbide (SiC) wafer (e.g., 2 mohm-cm) allows an “on” resistance (R on ) is reduced, thereby improving the overall signal transmission function and efficiency of a power device including the wafer or a portion of the wafer. The low warpage of the polycrystalline SiC wafer (e.g., less than or equal to 75 μm) reduces the possibility of mechanical defects or electrical defects in the bonding layer, or prevents the defect. The low warpage of the polycrystalline SiC wafer also reduces the possibility of mechanical defects or electrical defects between the bonding layer, the single crystal silicon carbide layer, and the polycrystalline silicon carbide layer, or prevents the defect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to better understand the embodiments, reference will now be made to the accompanying drawings as examples. In the accompanying drawings, the same reference numerals identify the same or similar elements or actions, unless the context otherwise indicates. The sizes and relative proportions of the elements in the accompanying drawings are not necessarily drawn to scale. For example, some of these elements may be enlarged and positioned to improve the readability of the drawing.

[0029] Figure 1 a perspective side view of an embodiment of a wafer relating to the present disclosure;

[0030] Figure 2 a perspective side view of an alternative embodiment of a wafer relating to the present disclosure;

[0031] Figure 3 Involving such as Figure 1 In the embodiment of the wafer shown in FIG. Figure 2 A perspective side view of an embodiment of a polycrystalline layer or substrate utilized within an alternative embodiment of a wafer as shown in;

[0032] Figure 4The embodiment of the wafer of the present disclosure is as follows Figure 1 an enlarged enhanced view of section 4-4 shown in;

[0033] Figure 5A Yes Figure 1 A flow chart of a method for manufacturing an embodiment of a wafer of the present disclosure shown in;

[0034] Figure 5B Yes Figure 3 A flow chart of an embodiment of a method for manufacturing an embodiment of a polycrystalline substrate shown in;

[0035] Figure 5C Yes Figure 3 A flow chart of an alternative embodiment of a method of manufacturing an embodiment of a polycrystalline substrate shown in;

[0036] Figure 5D Yes Figure 3 A flowchart of another alternative embodiment of a method for manufacturing an embodiment of a polycrystalline substrate shown in ; and

[0037] FIG. 6A to FIG. 6C It is used to manufacture Figure 1 The embodiment of the wafer shown in FIG. Figure 5A 0014] Figure 2 is a side view of at least some steps of an embodiment of a manufacturing method shown in FIG. DETAILED DESCRIPTION

[0038] In the following description, certain details are set forth in order to provide a thorough understanding of various embodiments of the apparatus, methods, and articles. However, those skilled in the art will appreciate that other embodiments may be practiced without these details. In other cases, well-known structures and methods associated with, for example, silicon carbide substrates or silicon carbide layers (e.g., polycrystalline silicon carbide, single crystal silicon carbide, etc.), semiconductor manufacturing processes, etc., are not shown or described in detail in some of the drawings to avoid unnecessarily obscuring the description of the embodiments.

[0039] Unless the context requires otherwise, in the following description and claims, the word "comprise" and variations such as "including" and "comprising" are to be construed in an open, inclusive sense, ie, to mean "including, but not limited to."

[0040] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearance of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment or to all embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments to obtain additional embodiments.

[0041] Headings are provided for convenience only and do not interpret the scope or meaning of the disclosure or claims.

[0042] The sizes and relative positions of the elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and corners may not be drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawing.

[0043] The use of "transverse" means that a surface, sidewall, or similar or analogous structure or feature is at an angle relative to another corresponding surface, sidewall, or similar or analogous structure or feature. For example, if a first surface is transverse to a first sidewall, the first surface may be at an angle equal to 25 degrees, 35 degrees, 45 degrees, 75 degrees, 90 degrees, 120 degrees, etc.

[0044] Typically, polycrystalline silicon carbide (SiC) substrates, wafers, or layers have been utilized in various electronic devices and components (e.g., semiconductor dies, semiconductor packages, semiconductor transistors, etc.). The resistivity of these polycrystalline SiC substrates, wafers, or layers results in resistance in electrical paths through or along the polycrystalline silicon carbide (SiC) substrates. This resistance that impedes an electrical signal as it travels through or along an electrical path is referred to as on-resistance (R on The on-resistance (R on ) limits the efficiency or electrical characteristics of electronic devices made of polycrystalline SiC substrates. For example, if the on-resistance (R on ) is high, it may prevent the electrical signal from fully passing through the polycrystalline SiC substrate to its destination, thereby causing functional errors within the electronic device or component. Given that the polycrystalline silicon carbide (SiC) substrate, wafer or layer has at least this on-resistance (R on ) problem, the present disclosure is directed to providing a polycrystalline silicon carbide (SiC) substrate, wafer or layer having a resistivity lower than that of current polycrystalline silicon carbide (SiC) substrates. For example, polycrystalline silicon carbide (SiC) substrates, wafers or layers that have been utilized in these corresponding industries may have a resistivity in the range of 2mohm-cm (milliohm-centimeter) to 10mohm-cm (milliohm-centimeter).

[0045] Polycrystalline SiC wafers with low resistivity are beneficial to the function of electronic devices in which the polycrystalline SiC wafers are present. The present disclosure relates to providing at least one embodiment of a wafer including a polycrystalline silicon carbide wafer or substrate having low resistivity and low warpage. Electronic devices or components made from the wafer are further optimized when used and have few crystal defects. Compared to existing SiC wafers, the wafers formed according to the embodiments of the present disclosure have low or very low resistivity. The low warpage in at least one embodiment of the wafer of the present disclosure prevents or reduces the possibility of defects such as from the polishing process when manufacturing terminal electronic devices, or reduces the number of wafers or substrates that are broken or broken during processing and manufacturing.

[0046] At least one embodiment of the device of the present disclosure is summarized as follows. The device includes a polycrystalline silicon carbide (SiC) wafer having a resistivity less than or equal to 2 mohm-cm (milliohm-cm). The polycrystalline silicon carbide wafer includes a roughness less than or equal to 20 angstroms. A single crystal silicon carbide (SiC) wafer is coupled to a first surface of a polycrystalline silicon carbide (SiC) wafer.

[0047] At least one embodiment of the device of the present disclosure is summarized as follows. The device includes a substrate having a polycrystalline silicon carbide (SiC) layer. The polycrystalline silicon carbide (SiC) layer includes a first surface, a second surface opposite to the first surface, a first dimension extending from the first surface to the second surface, and a resistivity less than or equal to 2mohm-cm (milliohm-centimeter). The single-crystalline silicon carbide (SiC) layer is coupled to the second surface of the polycrystalline silicon carbide (SiC) layer. The single-crystalline silicon carbide layer includes a third surface on the second surface of the polycrystalline silicon carbide (SiC) layer, a fourth surface opposite to the third surface, and a second dimension extending from the third surface to the fourth surface, the third surface of the single-crystalline silicon carbide (SiC) layer being located on a bonding layer and facing the first surface of the polycrystalline silicon carbide (SiC) layer. The second dimension is smaller than the first dimension.

[0048] At least one embodiment of the device is summarized as follows. The device includes a polycrystalline silicon carbide substrate. The polycrystalline silicon carbide substrate includes a first surface, a second surface opposite to the first surface, a thickness extending from the first surface to the second surface (the thickness is greater than or equal to 150 μm (micrometers)), a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter), and a warpage less than 75 μm.

[0049] At least one embodiment of the method of the present disclosure is summarized as follows: The method includes forming a polycrystalline silicon carbide (SiC) substrate having a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter), forming a single crystal silicon carbide (SiC) substrate, and coupling the single crystal SiC substrate to a polycrystalline SiC substrate.

[0050] Figure 1 1 is a side view of an embodiment of a wafer 100 of the present disclosure. The wafer 100 includes a first side 102 and a second side 104 opposite the first side 102. The wafer 100 also includes a polycrystalline silicon carbide (SiC) layer 106, a bonding region 108, and a single crystal silicon carbide (SiC) layer 110 bonded to the polycrystalline silicon carbide layer 106 at the bonding region 108. The polycrystalline silicon carbide layer 106 may be referred to as a polycrystalline silicon carbide substrate, a polycrystalline silicon carbide wafer, a polycrystalline silicon carbide layer, or may be referred to in some other suitable manner. The single crystal silicon carbide (SiC) layer 110 may be referred to as a single crystal silicon carbide substrate, a single crystal silicon carbide wafer, a single crystal silicon carbide layer, or may be referred to in some other suitable manner. Within the present disclosure, the polycrystalline silicon carbide (SiC) layer 106 may be referred to herein as the polycrystalline layer 106, and within the present disclosure, the single crystal silicon carbide (SiC) layer 110 may be referred to herein as the single crystal layer 110. In at least one embodiment, the single crystal layer 110 has a relative humidity of 3.26 g / cm 3 In at least one embodiment, the density of the polycrystalline layer 106 is from 3.2 g / cm 3 Up to 3.3g / cm 3 In at least one embodiment, the density of the polycrystalline layer 106 is in the range of 3.25 g / cm 3 Up to 3.3g / cm 3 or the density is equal to the upper and lower ends of the range.

[0051] The polycrystalline layer 106 has a low resistivity, for example, a resistivity of less than or equal to 2 mohm-cm (milliohm-centimeter) or a resistivity of less than or equal to 1 mohm-cm (milliohm-centimeter). This low resistivity of the polycrystalline layer 106 enables electrical signals (e.g., electrons) to pass through the polycrystalline layer 106 without being blocked by the polycrystalline layer 106, so that the electrical signals can travel through the polycrystalline layer 106 faster and reach their destination with higher strength than when the polycrystalline layer 106 has a high resistivity. In other words, when the on-resistance (R on ) is low (i.e., low resistivity), electrical signals will more easily and efficiently pass through the polycrystalline layer 106 without being obstructed by the polycrystalline layer 106 when traveling to their destination within an electronic device (e.g., a semiconductor package, a semiconductor die, or some other similar or analogous electronic device in which the polycrystalline layer 106 may be present).

[0052] The polycrystalline layer 106 includes a first surface 112 and a second surface 114 opposite to the first surface 112. The first surface 112 of the polycrystalline layer 106 is located at the first side 104 of the wafer 100. The single crystal layer 110 includes a third surface 116 and a fourth surface 118 opposite to the third surface 116. The fourth surface 118 of the single crystal layer 110 is located at the second side 106 of the wafer 100.

[0053] The polycrystalline layer 106 has a first thickness T1, which may be referred to as a first dimension. The first thickness T1 extends from the first surface 112 of the polycrystalline layer 106 to the second surface 114 of the polycrystalline layer 106. In some embodiments, the first thickness T1 may be in the range of 150-1500 microns (μm), or equal to the upper and lower ends of the range (e.g., the first thickness T1 may be equal to 150 microns (μm) or may be equal to 1000 microns (μm)). In some embodiments, the first thickness may be less than or equal to 1 millimeter (mm).

[0054] The single crystal layer 110 has a second thickness T2, which may be referred to as a second dimension. The second thickness T2 extends from the third surface 116 of the single crystal layer 110 to the fourth surface 118 of the single crystal layer 110. The second thickness T2 of the single crystal layer 110 may be less than the first thickness T1 of the polycrystalline layer 106. The second thickness T2 of the single crystal layer 110 may be in the range of 0.3-2 micrometers (μm), or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 0.3 micrometers (μm) or may be equal to 2 micrometers (μm)). In some embodiments, the second thickness may be in the range of 0.3-1 micrometers (μm), or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 0.3 micrometers (μm) or may be equal to 1 micrometer (μm)). In some embodiments, the second thickness T2 of the single crystal layer 110 may be equal to 0.5 micrometers (μm). In some embodiments, the second thickness T2 may be less than or equal to 20-200 micrometers (μm), or equal to the upper and lower ends of the range (for example, the second thickness T2 may be equal to 20 micrometers (μm) or may be equal to 200 micrometers (μm)). In some embodiments, the second thickness T2 may be equal to 120 micrometers (μm).

[0055] In some embodiments, the sum of the first thickness T1 and the second thickness T2 may be in the range of 200 micrometers (μm) to 1500 micrometers (μm), or may be equal to the upper and lower ends of the range. For example, in some embodiments, the sum of the first thickness T1 and the second thickness T2 may be equal to 200 micrometers (μm), may be equal to 1500 micrometers (μm), or may be equal to some other thickness between 200 and 1500 micrometers (μm). In some embodiments, the sum of the first thickness T1 and the second thickness T2 may be equal to 250 micrometers (μm), may be equal to 500 micrometers (μm), or may be equal to some other thickness between 250 micrometers (μm) and 500 micrometers (μm). In some embodiments, the sum of the first thickness T1 and the second thickness T2 may be equal to 700 micrometers (μm), may be equal to 800 micrometers (μm), or may be equal to some other thickness between 700 micrometers (μm) and 800 micrometers (μm).

[0056] In at least one embodiment, the resistivity of the single crystal layer 110 can be less than 25 mohm-cm or preferably equal to 18 mohm-cm, or in the range of 15-20 mohm-cm, or equal to the upper and lower ends of the range. In at least one embodiment, the polycrystalline layer 106 has a void density less than or equal to 3%. Figure 1 In the embodiment of the wafer 100 shown in FIG. 1 , the bonding region 108 exists between the first surface 112 of the polycrystalline layer 106 and the second surface 114 of the single crystal layer 110, and the bonding region 108 is where the second surface 114 of the polycrystalline layer 106 is directly physically bonded to the single crystal layer 110. In some embodiments, the single crystal layer 110 is directly physically bonded to the polycrystalline layer 106 by utilizing a surface activated bonding (SAB) technique. For example, in the surface activated bonding technique, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer may be bombarded with argon (Ar) ions or neutral atoms (e.g., a particle beam that may be argon (Ar), may be neutral atoms, or may be some other similar or analogous type of particles or atoms that may be suitable) in an ultra-high vacuum to clean and activate the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110. After the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110 are cleaned and activated, the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110 are spontaneously bonded by contacting the second surface 114 of the polycrystalline layer 106 with the third surface 116 of the single crystal layer 106. Such contact of the second surface 114 of the polycrystalline layer 106 and the third surface 114 of the single crystal layer 110 may be performed without performing a heat treatment.

[0057] Wafer 100 also includes at least one sidewall 120 (e.g., Figure 110 is a circle in the embodiment shown in FIG. 10 ), along which at least one first sidewall 120a of the polycrystalline layer 106 and at least one second sidewall 120b of the single crystal layer 110 are respectively coplanar and flush with each other. In other words, at least one sidewall 120 includes and is defined by the respective sidewalls of the polycrystalline layer 106, the bonding layer 108, and the single crystal layer 110. The bonding layer 108 includes a sidewall 120c coplanar with the sidewall 120a of the polycrystalline layer 106 and the sidewall 120b of the single crystal layer 110.

[0058] As previously discussed herein, the polycrystalline layer 106 has a low resistivity, for example, a resistivity of less than or equal to 2 mohm-cm (milliohm-centimeter) or a resistivity of less than or equal to 1 mohm-cm (milliohm-centimeter). This low resistivity of the polycrystalline layer 106 enables electrical signals (e.g., electrons) to pass through the polycrystalline layer 106 without being blocked by the polycrystalline layer 106, such that the electrical signals can travel through the polycrystalline layer 106 faster and can reach their destination with greater strength than when the polycrystalline layer 106 has a high resistivity. In other words, when the on-resistance (R on ) is low (i.e., low resistivity), electrical signals will more easily and efficiently pass through the polycrystalline layer 106 without being obstructed by the polycrystalline layer 106 when traveling to their destination within an electronic device (e.g., a semiconductor package, a semiconductor die, or some other similar or analogous electronic device in which the polycrystalline layer 106 may be present).

[0059] Although in Figure 1 Not shown, but in some alternative embodiments of wafer 100 , a silicon oxide (eg, SiO 2 ) layer may be present at bonding region 108 , such that the silicon oxide layer is located between polycrystalline layer 106 and single crystal layer 110 .

[0060] Wafer 100 has a diameter D1 extending from opposite points along the perimeter of wafer 100. Diameter D1 may be in the range of 150 to 300 millimeters (mm) and may be equal to the upper and lower ends of the range. For example, diameter D1 may be equal to 150 mm, may be equal to 200 mm, and may be equal to 300 mm.

[0061] Embodiments of the wafer 100 may have some warp, which may be some bend or curvature within embodiments of the wafer 100 that may cause the second surface 114 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some warp may exist in the wafer 100, the warp in the wafer 100 is less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm). The warp may be measured as the distance from the center point of the wafer to a point at or near the edge of the wafer in a direction transverse to the second surface 114 of the wafer. The warp is relative to the flatness of the horizontality of the wafer 100, which may be easily seen at and along the respective surfaces 112, 114, 116, 118, respectively.

[0062] The second surface 114 of the polycrystalline layer 106 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 114 of the polycrystalline layer 106 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the second surface 114 can be obtained by polishing the second surface 114.

[0063] The third surface 116 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the third surface 116 of the single crystal layer 110 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the third surface 116 can be obtained by polishing the third surface 116.

[0064] The fourth surface 118 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the fourth surface 118 of the single crystal layer 110 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the fourth surface 118 may be obtained by polishing or planarizing the fourth surface 116. In some embodiments, the roughness of the first surface 104 of the polycrystalline layer 106 may be greater than or equal to the roughness of the second surface 114 of the polycrystalline layer 106. The roughness of the first surface 104 may be obtained by polishing or planarizing the first surface 104.

[0065] Wafer 100 or a portion of a corresponding wafer may exist within a semiconductor package formed using wafer 100. For example, wafer 100 may be used to form a vertical device including wafer 100 or a portion of wafer 100. For example, additional layers may be formed on single crystal layer 110.

[0066] Figure 2 Involving Figure 1 FIG. 1 is a perspective side view of an alternative embodiment of a wafer 200 having several features identical or similar to the embodiment of wafer 100 shown in FIG. 1 . Wafer 200 has identical or similar reference numerals relative to identical or similar features of wafer 100 . Therefore, the following description of the embodiment of wafer 100 is as follows: Figure 2 The discussion of the alternative embodiments of the wafer 200 shown in FIG. 2 will focus on the embodiment of the wafer 200 shown in FIG. Figure 1 The embodiment of wafer 100 shown in FIG. 1 may have different or additional features or details than those of the embodiment of wafer 100 shown in FIG.

[0067] In the embodiment in which the second surface 114 of the polycrystalline layer 106 is directly physically bonded to the third surface 116 of the single crystal layer 110 Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 In the embodiment of the wafer 200 shown in , the bonding layer 202 is present at the bonding region 108 and couples the polycrystalline layer 106 with the single crystal layer 110. For example, before performing the surface activated bonding (SAB) technique previously discussed herein, a first conductive layer can be formed on the second surface 114 of the polycrystalline layer 106 and a second conductive layer can be formed on the third surface 116 of the single crystal layer 110. The first conductive layer and the second conductive layer can be made of the same or different conductive materials suitable for being bonded together using the SAB technique. In some embodiments, the first conductive layer and the second conductive layer can be formed on the second surface 114 of the polycrystalline layer 112 and the third surface 116 of the single crystal layer 110, respectively, by sputtering techniques or by some other technique suitable for forming the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 112 and the third surface 116 of the single crystal layer 110, respectively.

[0068] After forming the first conductive layer and the second conductive layer on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110, respectively, a surface activation bonding technique is performed such that the first conductive layer and the second conductive layer are bombarded with argon (Ar) ions or neutral atoms (e.g., may be argon (Ar), may be neutral atoms, or may be a particle beam of some other similar or analogous type of particles or atoms that may be suitable) in an ultra-high vacuum to clean and activate the first conductive layer and the second conductive layer respectively located on the second surface 114 of the polycrystalline layer 106 and the third surface 116 of the single crystal layer 110. After the first conductive layer and the second conductive layer are cleaned and activated, the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 116 of the single crystal layer 110 are spontaneously bonded by bringing the first conductive layer on the second surface 114 of the polycrystalline layer 106 into contact with the second conductive layer on the third surface 116 of the single crystal layer 106. Such contact of the first conductive layer on the second surface 114 of the polycrystalline layer 106 and the second conductive layer on the third surface 114 of the single crystal layer 110 may be performed without heat treatment. Once the first conductive layer on the second surface 114 of the polycrystalline layer 106 is bonded to the second conductive layer on the third surface 116 of the single crystal layer 110, a bonding layer 202 is formed between the polycrystalline layer 106 and the single crystal layer 110. In other words, the bonding layer 202 may be a conductive layer formed by coupling the first conductive layer on the second surface 114 to the second conductive layer on the third surface 116.

[0069] In some alternative embodiments, instead of forming both the first conductive layer and the second conductive layer as discussed above, only one of the first conductive layer or the second conductive layer may be formed on only one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the single crystal layer 110. After forming only one of the first conductive layer or the second conductive layer, the SAB technique is similar to that previously described herein with respect to Figure 1 or Figure 2 The same or similar manner as discussed above is practiced, except that at least one of the second surface 114 of the polycrystalline layer 106 or the third surface 116 of the single crystal layer 110 remains uncovered and exposed to the argon beam or the neutral atom beam.

[0070] When the first material of polycrystalline layer 106 is not suitable for direct physical bonding to the second material of single crystal layer 110, both the first conductive layer and the second conductive layer or at least one of the first conductive layer or the second conductive layer may be formed. In other words, when the first material of polycrystalline layer 106 is incompatible with the second material of single crystal layer 110, both the first conductive layer and the second conductive layer or at least one of the first conductive layer or the second conductive layer may be formed to facilitate coupling polycrystalline layer 106 and single crystal layer 110 together.

[0071] When there is a bonding layer 202 between the second surface 114 of the polycrystalline layer 106 and the third surface of the single crystal layer 110, the bonding layer 202 has a third thickness T3, which can be referred to as a third size. The third thickness T3 extends from the second surface 114 of the polycrystalline layer 106 to the third surface 116 of the single crystal layer 110. The third thickness T3 can be less than the first thickness T1. The third thickness T3 of the bonding layer 108 can be in the range of 0.2-5 microns (μm) and can be equal to the upper and lower ends of the range (for example, the third thickness T3 can be equal to 0.2 microns (μm) or can be equal to 5 microns (μm)). In some embodiments, the third thickness can be equal to 0.5 microns (μm).

[0072] The alternative embodiment of the wafer 200 may have a certain warp, which may be a certain bend or curvature within the alternative embodiment of the wafer 200 that may cause the second surface 114 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while there may be a certain warp in the alternative embodiment of the wafer 200, the warp in the alternative embodiment of the wafer 200 may be less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm). The second surface 114 of the polycrystalline layer 106 may have a thickness of less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 114 of the polycrystalline layer 106 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the second surface 114 can be obtained by polishing the second surface 114.

[0073] The third surface 116 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the third surface 116 of the polycrystalline layer 106 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the third surface 116 can be obtained by polishing the third surface 116.

[0074] The fourth surface 118 of the single crystal layer 110 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the fourth surface 118 of the single crystal layer 110 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the fourth surface 118 can be obtained by polishing or planarizing the fourth surface 116.

[0075] In some embodiments, the roughness of the first surface 104 of the polycrystalline layer 106 may be greater than or equal to the roughness of the second surface 114 of the polycrystalline layer 106. The roughness of the first surface 104 may be obtained by polishing or planarizing the first surface 104.

[0076] In yet another alternative embodiment of the wafer 200, the bonding layer 202 is instead a single layer of silicon. The single layer of silicon includes Figure 2 The thickness T3 shown in . When the bonding layer 202 is a single layer of silicon, the thickness T3 of the single layer of silicon may be in the range of 0.2 nanometers (nm) to 0.7 nanometers (nm), or may be equal to the upper and lower ends of the range. When the single crystal layer 110 is not suitable for direct physical bonding to the second surface 114 of the polycrystalline layer 106, a single layer of silicon is formed on the second surface 114 of the polycrystalline layer 106. The single layer of silicon to be the bonding layer 202 may be formed by atomic layer deposition or sputtering, so that the single layer of silicon exists on the second surface 114 of the polycrystalline layer 106, so that the single layer of silicon 110 can be easily adhered to the polycrystalline layer 106 through the single layer of silicon, which is also the bonding layer 202. Alternatively, instead of a single layer of silicon, the bonding layer 202 may be a single layer of carbon, a double layer of carbon, or a silicon dioxide (SiO2) layer. The thickness of the single layer of carbon may be in the range of 0.4 nanometers (nm) to 2 nanometers (nm), or may be equal to the upper and lower ends of the range. The thickness of the double carbon layer may be in the range of 1 nm to 5 nm, or may be equal to the upper and lower ends of the range. The thickness of the SiO2 layer may be in the range of 2 nm to 7 nm, or may be equal to the upper and lower ends of the range.

[0077] Figure 31 is a perspective side view of an embodiment of a polycrystalline substrate 300, which may be a polycrystalline wafer before a single crystal substrate or wafer (e.g., single crystal layer 110) has been coupled or bonded to the polycrystalline substrate 300. The polycrystalline substrate 300 has a diameter D1. In the embodiment of the wafer 100 and the alternative embodiment of the wafer 200, the polycrystalline substrate 300 may be utilized when forming the polycrystalline layer 106. The polycrystalline substrate 300 includes a first surface 302, a second surface 304 opposite the first surface 302, and a sidewall 306 extending from the first surface 302 to the second surface 304 and transverse to the first surface 302 and the second surface 304. As in the embodiment of the wafer 100 and the alternative embodiment of the wafer 200, the second surface 304 of the polycrystalline substrate 300 may correspond to the second surface 114 of the polycrystalline layer 106. As in the embodiment of wafer 100 and the alternative embodiment of wafer 200 , the sidewall 306 of the polycrystalline substrate 300 may correspond to the at least one first sidewall 120 a of the polycrystalline layer 106 .

[0078] The fourth thickness T4 of the polycrystalline substrate 300 extends from the first surface 302 to the second surface 304 of the polycrystalline substrate 300. As in the embodiment of the wafer 100 and the alternative embodiment of the wafer 200, the fourth thickness T4 can be greater than or equal to the third thickness T3 of the polycrystalline layer 106. The fourth thickness T4 can be in the range of 150 micrometers (μm) to 1000 micrometers (μm), or can be equal to the lower end and the upper end of the range.

[0079] The polycrystalline substrate 300 has a low resistivity, for example, a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter), or a resistivity less than or equal to 1 mohm-cm (milliohm-centimeter).

[0080] Embodiments of the polycrystalline substrate 300 may have some warp, which may be some bend or curvature within embodiments of the polycrystalline substrate 300 that may cause the second surface 304 of the polycrystalline layer 106 to be slightly curved or have a slight curvature. However, while some warp may exist in the polycrystalline substrate 300, the warp in the polycrystalline substrate 300 may be less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm).

[0081] The second surface 304 of the polycrystalline substrate 300 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the second surface 304 of the polycrystalline substrate 300 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the second surface 304 can be obtained by polishing the second surface 304.

[0082] Figure 4 Yes Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 1 The polycrystalline layer 106 includes grains 402 of silicon carbide (e.g., SiC, SiC2, etc.) that may be bonded together (see the disclosure of Figure 5A ).like Figure 4 The enlarged enhanced view shown in FIG. Figure 2 The grain structure of the polycrystalline layer 106 in the alternative embodiment of the wafer 200 shown in FIG. Figure 3 The grain structure of the embodiment of the polycrystalline substrate 300 shown in . The polycrystalline layer 106 is a non-columnar polycrystalline, so that the polycrystalline layer 106 has disordered or amorphous oriented grains and does not have a columnar structure. Such disordered and amorphous oriented grains and non-columnar structures of the polycrystalline layer 106 may be referred to as a non-oriented grain structure. The non-oriented grain structure may help to reduce the total resistivity of the polycrystalline layer 106. The polycrystalline layer 106 may include micropores 404, which may exist along grain boundaries 406 located between the grains 402. The grain boundaries 406 are located between adjacent pairs of corresponding grains in the grains 402. Carbon may be present at the grain boundaries 406 to adhere the grains 402 in the polycrystalline layer 106 to each other. The particles 402 may have a size less than or equal to 1 millimeter (mm).

[0083] The size of the grains 402 is relatively uniform throughout the polycrystalline layer 106 from the first surface 112 to the second surface 114 of the polycrystalline layer 106. In other words, the size of the grains 402 remains relatively uniform throughout the entirety of the polycrystalline layer 106 regardless of the location along the polycrystalline layer 106 between the first surface 112 and the second surface 114. For example, the grain sizes of the grains 402 at the first surface 112 of the polycrystalline layer 106, at the second surface 114 of the polycrystalline layer 106, and at intermediate locations along the polycrystalline layer 106 between the first surface 112 and the second surface 114 are uniform and substantially equal to one another.

[0084] Given that the grain size is relatively uniform across the polycrystalline layer 106 , the corresponding densities of the polycrystalline layer 106 at these different locations are relatively uniform and equal to one another. In other words, the polycrystalline layer 106 has a relatively uniform density across the polycrystalline layer 106 .

[0085] As previously discussed herein, the polycrystalline layer 106 has a low resistivity that can be formed using the polycrystalline substrate 300. The polycrystalline layer 106 can have a low resistivity by reducing or limiting the number of micropores 404 between the grains 402 along the grain boundaries 406 so that the polycrystalline layer 106 has a resistivity of less than or equal to 2 mohm-cm (milliohm-cm), or by highly doping the polycrystalline layer 106 with nitrogen (N) to reduce and offset the effects of the presence of micropores 404 in the polycrystalline layer 106. For example, the polycrystalline layer 106 can be highly doped with nitrogen so that the nitrogen (N) concentration in the polycrystalline layer 106 is greater than or equal to 3E+19 atoms / cm 3 (i.e., 3×10 19 atoms / cm 3 ), or the nitrogen concentration in the polycrystalline layer 106 may be equal to the upper and lower ends of the range. In some embodiments, the concentration of nitrogen (N) doped in the polycrystalline layer 106 may be greater than or equal to 5E+19 atoms / cm 3 (i.e., 5×10 19 atoms / cm 3 ).

[0086] Figure 5A The present disclosure Figure 1 Flowchart 500 of an embodiment of a method of manufacturing an embodiment of wafer 100 is shown in FIG. FIG. 6A to FIG. 6C A side view of various steps 502, 504, 506, 508 in a flowchart 500 of an embodiment of a method for manufacturing an embodiment of a wafer 100 of the present disclosure.

[0087] In the polycrystalline substrate forming step 502, a polycrystalline substrate 300 having a low resistivity is formed. In the single crystal substrate forming step 504, a single crystal substrate 504 is formed. The polycrystalline substrate forming step 502 and the single crystal substrate forming step 504 may occur simultaneously within a semiconductor fabrication facility (FAB), or may occur at different times within the FAB. The polycrystalline substrate forming step 502 and the single crystal substrate forming step 504 may be practiced at different locations within the FAB.

[0088] The polycrystalline substrate forming step 502 for forming the polycrystalline substrate 300 having a low resistivity may be performed using Figure 5B The chemical vapor deposition (CVD) flow chart 502a shown in FIG. Figure 5C The sintering flow chart 502b shown in FIG. Figure 5C In other words, the polycrystalline substrate 300 may be formed using any one of the CVD flow chart 502a, the sintering flow chart 502b, and the sublimation flow chart 502c.

[0089] When using Figure 5B When forming the polycrystalline substrate 300 by the method in the CVD flow chart 502a shown in FIG. 5 , in a first step 510, a carrier is inserted or introduced into a chamber of a CVD tool configured to perform or practice a CVD process to form the polycrystalline substrate 300. The carrier may be a plate, may be a carrier substrate, or may be some other suitable type of carrier on which the polycrystalline substrate is formed. The carrier may be a polycrystalline carrier substrate or plate, may be a graphite carrier substrate or plate, or may be some other suitable type of carrier substrate or plate on which the polycrystalline substrate is formed.

[0090] After the first step 510 of inserting or introducing the carrier into the chamber of the CVD tool, in a second step 512, the chamber is sealed and a carrier gas is introduced into the chamber of the CVD tool. The carrier gas can be hydrogen, a hydrogen-based gas, argon, an argon-based gas, or can be some other suitable carrier gas or inert carrier gas. The carrier gas is configured to enhance the chemical reaction within the chamber of the CVD tool to grow polycrystalline silicon carbide (SiC) on the carrier within the chamber of the CVD tool. In some embodiments, during the second step 512, the chamber of the CVD tool can be heated in a range of 1500 degrees Celsius (°C) to 1700 degrees Celsius (°C), or can be heated to a temperature equal to the upper and lower ends of the range (e.g., a temperature equal to 1500 degrees Celsius (°C) or equal to 1700 degrees Celsius (°C)). In some alternative embodiments, during the second step 512, the chamber of the CVD tool may be heated within a range of 950 degrees Celsius (°C) to 1350 degrees Celsius (°C), or may be heated to a temperature equal to the upper and lower ends of the range (e.g., a temperature equal to 950 degrees Celsius (°C) or equal to 1350 degrees Celsius (°C)).

[0091] After the carrier gas has been introduced into the chamber of the CVD tool and the chamber of the CVD tool has been heated or heating has been initiated in the second step 512, a carbon gas or carbon-based gas, a silicon-containing gas or silicon-based gas (e.g., silane, trichlorosilane (TCS), or some other similar silicon-containing gas or silicon-based gas), and a nitrogen gas or nitrogen-based gas are introduced into the chamber of the CVD tool in a third step 514. For example, the carbon gas or carbon-based gas may be introduced into the chamber of the CVD tool by introducing a carbon source into the chamber of the CVD tool, the silicon-containing gas or silicon-based gas may be introduced into the chamber of the CVD tool by introducing a silicon-containing gas source or silicon-based gas source into the chamber of the CVD tool, and the nitrogen gas or nitrogen-based gas may be introduced into the chamber of the CVD tool by introducing a nitrogen source into the chamber of the CVD tool. Alternatively, corresponding fluid paths in fluid communication with the chamber of the CVD tool may be unblocked to introduce the carbon gas or carbon-based gas, the silicon-containing gas or silicon-based gas, and the nitrogen gas or nitrogen-based gas. When these corresponding gases are introduced into the chamber of the CVD tool at this stage, these corresponding gases chemically react with each other, so that silicon carbide (SiC) doped with nitrogen is formed and deposited on the carrier substrate, which causes polycrystalline silicon carbide to be formed on the carrier surface of the carrier. When the carrier is a polycrystalline silicon carbide carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the CVD tool is deposited on the polycrystalline silicon carbide carrier substrate or plate. When the carrier is a graphite carrier substrate or plate, the polycrystalline silicon carbide formed by the reaction in the chamber of the CVD tool is deposited on the graphite carrier substrate or plate. When polycrystalline silicon carbide is formed in the chamber of the CVD tool, the polycrystalline silicon carbide is doped with nitrogen, thereby forming polycrystalline silicon carbide doped with nitrogen on the carrier.

[0092] After the third step 514 in which the carbon gas or carbon-based gas, the silicon-containing gas or silicon-based gas, and the nitrogen gas or nitrogen-based gas are introduced into the chamber of the CVD tool while being heated to form polycrystalline silicon carbide doped with nitrogen on the carrier, in a fourth step 516, the chamber of the CVD tool and the polycrystalline substrate 300 formed on the carrier are allowed to cool to room temperature. As the polycrystalline substrate 300 cools on the carrier, the difference in thermal conductivity between the polycrystalline substrate 300 and the carrier may result in a certain warpage of the polycrystalline substrate 300. However, this warpage of the polycrystalline substrate is less than or equal to 75 micrometers (μm) or may be less than or equal to 45 micrometers (μm). Once cooled to room temperature, the carrier and the polycrystalline substrate 300 coupled to the carrier are removed from the chamber of the CVD tool. After the polycrystalline substrate 300 and the carrier are removed from the chamber, the polycrystalline substrate 300 can be removed from the carrier and then further processed (e.g., polishing techniques, planarization techniques, etc.), a portion of the polycrystalline substrate 300 can be cut out from the polycrystalline substrate 300 to form the polycrystalline layer 106 while the polycrystalline substrate 300 is coupled to the carrier or after being removed from the carrier or before or after further processing, or the polycrystalline substrate can undergo other suitable types of processing techniques to further refine or process the polycrystalline substrate 300 to form various electronic devices or components.

[0093] After the polycrystalline substrate 300 is formed, the polycrystalline substrate 300 may be used to form Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 For example, in at least one case, the second surface 304 of the polycrystalline layer 300 is polished or planarized so that the second surface 304 of the polycrystalline layer 300 has a surface area of ​​less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline layer 300 has a roughness of 1 to 5 angstroms. The roughness of the substrate may be within the range of , or may have a roughness equal to the lower or upper end of the range (e.g., the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms After the second surface 304 of the polycrystalline layer 300 is polished or planarized, the polycrystalline layer 300 may be used to form a Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 An alternative embodiment of wafer 200 is shown in FIG.

[0094] When using Figure 5C When forming a polycrystalline substrate 300 by the method in the sintering flow chart 502b shown in FIG. , in a first step 518, a doping powder (e.g., silicon carbide powder doped with nitrogen) is inserted or introduced into a container, which may be present in a sintering tool, or the container may be inserted or introduced into the sintering tool after being filled with the doping powder.

[0095] After the first step 518 in which the doped powder has been introduced into the container, in a second step 520, the container is then heated by a sintering tool, and pressure is applied to the doped powder in the container using the sintering tool. A temperature equal to or greater than 2000 degrees Celsius (°C) may be applied to the doped powder. In some embodiments, a pressure in the range of 300 mbar to 1 ATM (1013 mbar) or equal to the lower and upper ends of the range (e.g., equal to 300 mbar or equal to 1 ATM) may be applied to the doped powder. In some embodiments, a pressure in the range of 750 mbar to 950 mbar may be applied to the doped powder, or the pressure may be equal to the lower and upper ends of the range (e.g., equal to 750 mbar or equal to 950 mbar). The temperature and pressure are applied to the doped powder in the container using a sintering tool so that a polycrystalline silicon carbide body doped with nitrogen is formed in the container. The doped powder may be doped with a concentration of 3E+19 atoms / cm 3 (i.e., 3×10 19 atoms / cm 3 ) or may have a dopant greater than 3E+19 atoms / cm 3 (i.e., 3×10 19 atoms / cm 3 ). In some embodiments, the dopant may be nitrogen (N). For example, the doping powder may be doped with a concentration equal to 5E+19 atoms / cm 3 (i.e., 5×10 19 atoms / cm 3 ) of adulterants.

[0096] After the second step 520 of forming the polycrystalline body in the container by applying heat and pressure to the doped powder in the container, the polycrystalline body is removed from the container in a third step 522. The container and the polycrystalline body may be allowed to cool to room temperature before the polycrystalline body is removed from the container. After the polycrystalline body is removed from the container, the polycrystalline body may have a cylindrical shape or profile.

[0097] After the third step 522 of taking out the polycrystalline body from the container, in the fourth step 524, the polycrystalline body is further processed to form the polycrystalline substrate 300. For example, when the polycrystalline body taken out from the container has a cylindrical shape or profile as previously discussed herein, the polycrystalline body can be cut into a plurality of polycrystalline substrates 300 because the length of the cylindrical polycrystalline body between opposite ends of the cylindrical polycrystalline body can be greater than the fourth thickness T4, so that a plurality of polycrystalline substrates 300 can be formed.

[0098] After the polycrystalline substrate 300 is formed, the polycrystalline substrate 300 may be used to form Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 For example, in at least one case, the second surface 304 of the polycrystalline layer 300 is polished or planarized so that the second surface 304 of the polycrystalline layer 300 has a surface area of ​​less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline substrate 300 may have a roughness of 1 to 5 angstroms. The roughness of the substrate may be within the range of , or may have a roughness equal to the lower or upper end of the range (e.g., the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms After the second surface 304 of the polycrystalline layer 300 has been polished or planarized, the polycrystalline layer 300 may then be used to form a Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 An alternative embodiment of wafer 200 is shown in FIG.

[0099] When using Figure 5D When forming the polycrystalline substrate 300 according to the method in the sublimation flow chart 502c shown in FIG. 5 , in a first step 526 , sublimation powder, nitrogen or nitrogen-based gas, and carrier gas are introduced or inserted into a chamber of a sublimation growth tool.

[0100] After the first step 526 in which the sublimation powder, nitrogen or nitrogen-based gas, and carrier gas are inserted or introduced into the chamber of the sublimation tool, in a second step 528, heat is applied to the sublimation powder, nitrogen or nitrogen-based gas, and carrier gas in the chamber of the sublimation growth tool. The temperature of the sublimation tool chamber can be in the range of 2000-2500 degrees Celsius (°C), or can be equal to the lower and upper ends of the range (e.g., a temperature equal to 2000 degrees Celsius (°C) or equal to 2500 degrees Celsius (°C)). When heat is applied to the sublimation powder, sublimation gas is generated (e.g., sublimated) from the sublimation powder. The sublimation gas generated by heating the sublimation powder reacts with the carrier gas and the nitrogen or nitrogen-based gas to form and grow a polycrystalline body made of doped polycrystalline silicon carbide material in the chamber of the sublimation growth tool. For example, polycrystalline silicon carbide material can be deposited and grown on a surface within the sublimation growth tool.

[0101] After the second step 528 of applying heat to the sublimation powder, nitrogen or nitrogen-based gas, and carrier gas in the chamber of the sublimation growth tool, the polycrystalline body grown and formed in the chamber is removed from the chamber of the sublimation growth tool in a third step 530. The polycrystalline body may be allowed to cool to room temperature before being removed from the chamber of the sublimation growth tool.

[0102] After the third step 530 of removing the polycrystalline body from the chamber of the sublimation growth tool, in a fourth step 532, the polycrystalline body is further processed and refined to form the polycrystalline substrate 300. For example, in the fourth step 532 of the sublimation flow chart 502c, the polycrystalline body may be further refined or processed in the same or similar manner as previously discussed herein with respect to the further processing or refining of the polycrystalline body in the fourth step 524 of the sintering flow chart 502b. However, in some alternative embodiments, the polycrystalline body may already be in the form of the polycrystalline substrate 300, such that the polycrystalline body removed from the chamber of the sublimation growth tool is already in the form of the polycrystalline substrate 300.

[0103] After the polycrystalline substrate 300 is formed, the polycrystalline substrate 300 may be used to form Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 For example, in at least one case, the second surface 304 of the polycrystalline layer 300 is polished or planarized so that the second surface 304 of the polycrystalline layer 300 has a surface area of ​​less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline substrate 300 may have a roughness of 1 to 5 angstroms. The roughness of the substrate may be within the range of , or may have a roughness equal to the lower or upper end of the range (e.g., the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms After the second surface 304 of the polycrystalline layer 300 has been polished or planarized, the polycrystalline layer 300 may then be used to form a Figure 1 The embodiment of the wafer 100 shown in FIG. Figure 2 An alternative embodiment of wafer 200 is shown in FIG.

[0104] In the single crystal substrate forming step 504, a single crystal substrate 600 may be formed using a method known in the semiconductor industry (see Figure 6B ). For example, a single crystal substrate can be formed by melting high purity, semiconductor grade silicon and then initiating the formation of the single crystal substrate using a seed crystal.

[0105] Once the polycrystalline substrate 300 and the single crystal substrate 600 are formed, the second surface 304 of the polycrystalline substrate 300 is bonded to the third surface 602 of the single crystal substrate 600 using a surface activated bonding (SAB) technique in a coupling or bonding step 506 of the flowchart 500 of the embodiment of forming the wafer 100. The third surface 602 of the single crystal substrate 600 may correspond to the third surface 116 of the single crystal layer 110 of the wafer 100.

[0106] When the SAB technique is used, the second surface 304 of the polycrystalline substrate 300 is as shown in FIG. Fig. 6AThe second surface 304 of the polycrystalline substrate 300 is exposed to a neutral atom beam or an argon (Ar) atom beam as indicated by arrow 603 in the figure to activate and clean the second surface 304 of the polycrystalline substrate 300. The second surface 304 of the polycrystalline substrate 300 may have been planarized to be substantially flat and level, and polished to have a thickness of less than or equal to 20 angstroms. In some embodiments, the second surface 304 of the polycrystalline substrate 300 may have a roughness of 1 to 5 angstroms before being exposed to the neutral atom beam or the argon (Ar) atom beam. or equal to the lower and upper ends of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms ).

[0107] When the SAB technique is used, the third surface 602 of the single crystal substrate 600 is exposed to a neutral atom beam or an argon (Ar) atom beam (not shown) to activate and clean the third surface 602 of the single crystal substrate 600. The third surface 602 of the single crystal substrate 600 may have been planarized to be substantially flat and level, and polished to have a surface roughness less than or equal to 20 angstroms. In some embodiments, the third surface 602 of the single crystal substrate 600 may have a roughness of 1 to 5 angstroms before being exposed to the neutral atom beam or the argon (Ar) atom beam. or equal to the lower and upper ends of the range (for example, the roughness may be equal to 1 angstrom Or it can be equal to 5 angstroms ).

[0108] The fourth surface 610 of the second portion 602b of the single crystal substrate 600 may have a thickness less than or equal to 20 angstroms. In some embodiments, the roughness of the fourth surface 610 of the second portion 600b of the single crystal substrate 600 may be between 1 and 5 angstroms. and may be equal to the lower and upper ends of the range (e.g., the roughness may be equal to 1 angstrom). Or it can be equal to 5 angstroms ). The roughness of the fourth surface 610 may be obtained by polishing or planarizing the fourth surface 610.

[0109] In some embodiments, the roughness at the first surface 302 of the polycrystalline substrate 300 may be greater than or equal to the roughness of the second surface 304 of the polycrystalline substrate 300. The roughness of the first surface 302 may be obtained by polishing or planarizing the first surface 302.

[0110] After the second surface 304 of the polycrystalline substrate 300 and the third surface 602 of the single crystal substrate 600 are cleaned and activated, the single crystal substrate 600 is turned over, and the third surface 602 of the cleaned and activated single crystal substrate 600 is brought into contact with the second surface 304 of the cleaned and activated polycrystalline substrate 300, so that the cleaned and activated second surface 304 and the cleaned and activated third surface 602 are spontaneously bonded, thereby bonding the single crystal substrate 600 to the polycrystalline substrate 300 at the bonding region 604. When the single crystal substrate 600 is bonded to the polycrystalline substrate 300, the sidewall 606 of the single crystal substrate 600 is flush with the sidewall 306 of the polycrystalline substrate 300. The single crystal substrate 600 has a fifth thickness T5 extending from the third surface 602 of the single crystal substrate 600 to a fourth surface 608 of the single crystal substrate 600 opposite to the third surface 602 of the single crystal substrate 600.

[0111] After the bonding step 506 in which the single crystal substrate 600 is bonded to the polycrystalline substrate 300, the first portion 600a is removed from the second portion 600b of the single crystal substrate 600 in a removing step 508. The first portion 600a may be removed from the second portion 600b by slicing the single crystal substrate 600 to form the first portion 600a and the second portion 600b. After the second portion 600b is removed from the first portion 600a, the second portion 600b of the single crystal substrate 600 may be reused to form another wafer that is the same as or similar to the wafer 100, for example, by practicing the bonding step 506 and the removing step 508 of the manufacturing method in the flowchart 500. The removal of the first portion 600a from the second portion 600b causes the sidewall 606 to be divided into a first sidewall 606a of the first portion 600a and a second sidewall 606b of the second portion 600b. After removing the first portion 600a, the second sidewall 606b of the second portion 600b remains coplanar and flush with the sidewall 306 of the polycrystalline substrate 300. After removing the first portion 600a, the second portion 600b remains bonded to the polycrystalline substrate 300 at the bonding area 604. After removing the first portion 600a from the second portion 600b, the second portion 600b has a second thickness T2 extending between a third surface 602 of the second portion 600b and a fourth surface 610 of the second portion 600b formed by removing the first portion 600a from the second portion 600b. After removing the first portion 600a from the second portion 600b, the first portion has a sixth thickness T6 extending from the fourth surface 608 of the first portion 600a to a fifth surface 612 of the first portion 600a opposite the fourth surface of the first portion 600a. The sixth thickness T6 is less than the fifth thickness T5.

[0112] The second portion 600b of the single crystal substrate 600 may correspond to the single crystal layer 110 of the wafer 100, the polycrystalline substrate 300 may correspond to the polycrystalline layer 106 of the wafer 100, and the bonding region 604 may correspond to the bonding region 108 of the wafer 100. In other words, in some embodiments, after removing the first portion 600a from the second portion 600b, the wafer 100 is manufactured. In some alternative embodiments, some further processing steps such as grinding the first surface 302 of the polycrystalline substrate 300 may be performed to complete the manufacturing of the wafer 300.

[0113] Since the manufacture of the single crystal substrate 600 is generally more expensive relative to the polycrystalline substrate 300, bonding the single crystal substrate 600 to the low resistivity polycrystalline substrate 300 as a support and removing the first portion 600a from the second portion 600b reduces the manufacturing cost because a plurality of wafers 100 can be formed using the single crystal substrate 600. In other words, although the cost of manufacturing a single crystal substrate may be expensive, the expense of manufacturing the single crystal substrate 600 can be amortized over a plurality of wafers 100 manufactured using the manufacturing method as in the flowchart 500.

[0114] In an alternative embodiment of the manufacturing method in flowchart 500, before bonding the single crystal substrate 600 to the polycrystalline substrate 300, the first portion 600a of the single crystal substrate 600 may be removed from the second portion 600b of the single crystal substrate 600. After the first portion 600a is removed from the second portion 600b, the third surface 602 of the second portion 600b of the single crystal substrate 600 is bonded to the second surface 304 of the polycrystalline substrate 300. In other words, in this alternative embodiment of the manufacturing method of the wafer 100, the removing step 508 occurs before the bonding step 506.

[0115] Although for Figure 5A The above method discussed in detail in the flowchart 500 in FIG. 1 describes forming the wafer 100, but for Figure 5A The above method discussed in detail in the flowchart 500 in FIG. 5 can be modified by the following steps: forming a first conductive layer on the second surface 304 of the polycrystalline substrate 300 by sputtering technology, forming a second conductive layer on the third surface 602 of the single crystal substrate 600, or forming only one of the first conductive layer and the second conductive layer, and then coupling the polycrystalline substrate 300 to the single crystal substrate 600 using both the first conductive layer and the second conductive layer or only one of the first conductive layer or the second conductive layer. The sputtering step can be performed in the case of the method for Figure 5A The method discussed in detail in the flowchart 500 in FIG. 5 is performed or practiced between the first step 502 and the second step 504. When the sputtering step is performed or practiced, the sputtering step is formed. Figure 2 , thereby producing an alternative embodiment of the wafer 200 .

[0116] Although for Figure 5A The above method discussed in detail in the flowchart 500 in FIG. 1 describes forming the wafer 100, but for Figure 5A The above method discussed in detail in the flowchart 500 in FIG. 5 may be modified by the following steps: forming a single layer of silicon, a double layer of carbon, a single layer of carbon, or a silicon dioxide (SiO2) layer on the second surface 304 of the polycrystalline substrate 300. After forming one of these corresponding material layers on the second surface 304 of the polycrystalline substrate 300, in at least one embodiment, the corresponding material layer on the second surface 304 of the polycrystalline layer is exposed to a neutral atom beam or an argon (Ar) atom beam, as indicated by arrow 603.

[0117] Although not shown, Figure 6C The wafer 100 shown in FIG. 1 can be further processed and refined (e.g., forming other layers (e.g., conductive layers and non-conductive layers) on the single crystal layer 110, singulation of the wafer 100, back grinding the wafer 100, etc.) for forming electronic devices and components, such as semiconductor packages or semiconductor devices. For example, a first electrode can be formed on a first side 104 of the wafer 100 and a second electrode can be formed on a second side 106 of the wafer 100 so that current can pass through the wafer 100, and the wafer 100 having a low resistivity enables electrical signals to pass through the wafer 100 without being blocked.

[0118] At least one embodiment of the device of the present disclosure can be summarized as including: a polycrystalline silicon carbide (SiC) wafer having a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter).

[0119] The device may also include a bonding layer on the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0120] The device may also include a single crystal silicon carbide (SiC) wafer on the bonding layer on the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0121] A polycrystalline silicon carbide (SiC) wafer may include: a second surface opposite to a first surface of the polycrystalline silicon carbide (SiC) layer; and a first dimension extending from the second surface to the first surface. A single crystal silicon carbide (SiC) wafer may include: a third surface facing the first surface of the polycrystalline silicon carbide (SiC) wafer; a fourth surface facing away from and opposite to the third surface; and a second dimension extending from the third surface to the fourth surface, and the second dimension is different from the first dimension.

[0122] The second size may be smaller than the first size.

[0123] The first dimension may be less than or equal to 1000 μm (micrometers); and the second dimension may be less than or equal to 1 μm (micrometers).

[0124] The device may also include a single crystal wafer bonded directly to the first surface of the polycrystalline silicon carbide (SiC) wafer.

[0125] The resistivity may be less than or equal to 1 mohm-cm (milliohm-centimeter).

[0126] The warpage of a polycrystalline silicon carbide (SiC) wafer can be less than 75 μm (micrometers).

[0127] The warpage of a polycrystalline silicon carbide (SiC) wafer can be less than 45 μm (micrometers).

[0128] Polycrystalline silicon carbide (SiC) wafers may have a non-columnar structure.

[0129] Polycrystalline silicon carbide (SiC) wafers may include grains less than or equal to 1 mm (millimeter).

[0130] At least one embodiment of the device disclosed herein can be summarized as including: a substrate, the substrate including a polycrystalline silicon carbide (SiC) layer and a single crystal silicon carbide (SiC) layer, the polycrystalline silicon carbide (SiC) layer including: a first surface; a second surface opposite to the first surface; a first dimension extending from the first surface to the second surface; a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter), the single crystal silicon carbide (SiC) layer including: a third surface on the second surface of the polycrystalline silicon carbide (SiC) layer; a fourth surface opposite to the third surface; and a second dimension extending from the third surface to the fourth surface, the third surface of the single crystal silicon carbide (SiC) layer is located on a bonding layer and faces the first surface of the polycrystalline silicon carbide (SiC) layer, and the second dimension is smaller than the first dimension.

[0131] The polycrystalline silicon carbide (SiC) layer may include grains less than or equal to 1 mm (millimeter).

[0132] The polycrystalline silicon carbide (SiC) layer may have a non-columnar structure.

[0133] At least one embodiment of a device of the present disclosure can be summarized as including a polycrystalline silicon carbide substrate, comprising: a first surface; a second surface opposite to the first surface; a thickness extending from the first surface to the second surface, the thickness being greater than or equal to 150 μm (micrometers); a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter); and a warpage less than 75 μm.

[0134] The resistivity may be less than or equal to 1 mohm-cm (milliohm-centimeter).

[0135] A polycrystalline silicon carbide (SiC) substrate may include grains less than or equal to 1 mm (millimeter) and have a non-columnar structure.

[0136] The warpage may be less than or equal to 75 μm (micrometers).

[0137] The thickness may be at least one of: between 150-1000 μm (micrometers), equal to 150 μm (micrometers), and equal to 1000 μm (micrometers).

[0138] At least one embodiment of the method of the present disclosure can be summarized as including: forming a polycrystalline silicon carbide (SiC) substrate having a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter); forming a single crystal silicon carbide (SiC) substrate; and coupling the single crystal SiC substrate to a polycrystalline SiC substrate.

[0139] The method may further include removing a first portion of the single crystal SiC substrate from the single crystal SiC substrate, thereby leaving a second portion of the single crystal SiC substrate coupled to the polycrystalline SiC substrate.

[0140] The second portion of the single crystal SiC substrate may have a thickness in the range of 0.3-2 micrometers (μm), equal to 0.3 micrometers (μm), or equal to 2 micrometers (μm).

[0141] A polycrystalline SiC substrate may be formed on a carrier within a chemical vapor deposition (CVD) chamber of a CVD tool by introducing a silicon-containing gas.

[0142] By introducing carbon gas and nitrogen gas, a polycrystalline SiC substrate may be formed on a carrier within a CVD chamber of a CVD tool.

[0143] The polycrystalline SiC substrate may be formed by introducing a doped powder into a container of a sintering tool and sintering the doped powder within the container with the sintering tool.

[0144] Sintering the doped powder may include exposing the doped powder to a temperature greater than or equal to 2000 degrees Celsius (C).

[0145] A polycrystalline SiC substrate can be formed using a sublimation process.

[0146] The various embodiments described above can be combined to provide other embodiments. Aspects of the embodiments can be modified, if necessary, to employ the concepts of the various patents, applications and publications to provide other embodiments.

[0147] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be understood to limit the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments within the entire equivalent scope of these claims that are authorized. Accordingly, the claims are not limited by the present disclosure.

[0148] Yet another aspect of the present disclosure provides a method comprising: forming a polycrystalline silicon carbide (SiC) substrate having a resistivity less than or equal to 2 mohm-cm (milliohm-centimeter); forming a single crystal silicon carbide (SiC) substrate; and coupling the single crystal SiC substrate to the polycrystalline SiC substrate.

[0149] According to at least one embodiment of the present disclosure, the method further includes:

[0150] A first portion of the single crystal SiC substrate is removed from the single crystal SiC substrate, thereby leaving a second portion of the single crystal SiC substrate coupled to the polycrystalline SiC substrate.

[0151] According to at least one embodiment of the present disclosure, the second portion of the single crystal SiC substrate has a thickness in the range of 0.3-2 micrometers (μm), equal to 0.3 micrometers (μm), or equal to 2 micrometers (μm).

[0152] According to at least one embodiment of the present disclosure, the polycrystalline SiC substrate is formed on a carrier within a CVD chamber of a chemical vapor deposition (CVD) tool by introducing a silicon-containing gas.

[0153] According to at least one embodiment of the present disclosure, the polycrystalline SiC substrate is formed on the carrier within the CVD chamber of the CVD tool by introducing carbon gas and nitrogen gas.

[0154] According to at least one embodiment of the present disclosure, the polycrystalline SiC substrate is formed by introducing doping powder into a container of a sintering tool and sintering the doping powder in the container with the sintering tool.

[0155] According to at least one embodiment of the present disclosure, sintering the doped powder includes exposing the doped powder to a temperature greater than or equal to 2000 degrees Celsius (C).

[0156] According to at least one embodiment of the present disclosure, the polycrystalline SiC substrate is formed by a sublimation process.

[0157] According to at least one embodiment of the present disclosure, bonding the single crystal SiC substrate to the polycrystalline SiC substrate further includes physically coupling a first surface of the single crystal SiC substrate directly to a second surface of the polycrystalline SiC substrate.

Claims

1. A device, characterized in that The device comprises: A polycrystalline silicon carbide (SiC) wafer, wherein the resistivity of the polycrystalline silicon carbide (SiC) wafer is less than or equal to 2 mohm-cm (milliohm-centimeter), and the polycrystalline silicon carbide comprises a silicon carbide wafer having a resistivity of less than or equal to 2 mohm-cm (milliohm-centimeter). a first surface having a roughness of A single crystal silicon carbide (SiC) wafer is coupled to the first surface of the polycrystalline silicon carbide (SiC) wafer.

2. The device according to claim 1, characterized in that The device also includes a bonding layer on the first surface of the polycrystalline silicon carbide (SiC) wafer.

3. The device according to claim 2, characterized in that The single crystal silicon carbide (SiC) wafer is located on the bonding layer on the surface of the polycrystalline silicon carbide (SiC) wafer and is coupled to the first surface of the polycrystalline silicon carbide (SiC) wafer through the bonding layer.

4. The device according to claim 3, characterized in that: The polycrystalline silicon carbide (SiC) wafer comprises: a second surface opposite the first surface of the polycrystalline silicon carbide (SiC) layer; and a first dimension extending from the second surface to the first surface; the single crystal silicon carbide (SiC) wafer comprising: a third surface, the third surface facing the first surface of the polycrystalline silicon carbide (SiC) wafer; a fourth surface facing away from the third surface and opposite to the third surface; and A second dimension extends from the third surface to the fourth surface and is different from the first dimension.

5. The device according to claim 4, characterized in that The second size is smaller than the first size.

6. The device according to claim 5, characterized in that: The first dimension is less than 1000 μm (micrometers); and The second dimension is less than or equal to 1 μm (micrometer).

7. The device according to claim 1, characterized in that The single crystal silicon carbide (SiC) wafer is physically bonded directly to the first surface of the polycrystalline silicon carbide (SiC) wafer.

8. The device according to claim 1, characterized in that The resistivity is less than or equal to 1 mohm-cm (milliohm-centimeter).

9. The device according to claim 1, characterized in that The polycrystalline silicon carbide (SiC) wafer has a warpage of less than 75 μm (micrometers).

10. The device according to claim 8, characterized in that The polycrystalline silicon carbide (SiC) wafer has a warpage of less than 45 μm (micrometers).

11. The device according to claim 1, characterized in that The polycrystalline silicon carbide (SiC) wafer has a non-columnar structure.

12. The device according to claim 1, characterized in that The polycrystalline silicon carbide (SiC) wafer includes grains less than or equal to 1 mm (millimeter).

13. A device, characterized in that The device comprises: A substrate, comprising: A polycrystalline silicon carbide (SiC) layer, the polycrystalline silicon carbide (SiC) layer comprising: a first surface; a second surface, the second surface being opposite to the first surface; a first dimension extending from the first surface to the second surface; and Resistivity less than or equal to 2mohm-cm (milliohm-centimeter); a single crystal silicon carbide (SiC) layer coupled to the second surface of the polycrystalline silicon carbide (SiC) layer, comprising: a third surface, the third surface being located on the second surface of the polycrystalline silicon carbide (SiC) layer; a fourth surface, the fourth surface being opposite to the third surface; and A second size extends from the third surface to the fourth surface, the third surface of the single-crystal silicon carbide (SiC) layer is located on the bonding layer and faces the first surface of the polycrystalline silicon carbide (SiC) layer, and the second size is smaller than the first size.

14. The device according to claim 13, characterized in that The polycrystalline silicon carbide (SiC) layer includes grains less than or equal to 1 mm (millimeter).

15. The device according to claim 13, characterized in that The polycrystalline silicon carbide (SiC) layer has a non-columnar structure.

16. A device, characterized in that The device comprises: A polycrystalline silicon carbide substrate, comprising: a first surface; a second surface, the second surface being opposite to the first surface; a thickness extending from the first surface to the second surface, the thickness being greater than or equal to 150 μm (micrometers); A resistivity of less than or equal to 2 mohm-cm (milliohm-centimeter); and Warpage less than 75μm.

17. The device according to claim 16, characterized in that The resistivity is less than or equal to 1 mohm-cm (milliohm-centimeter).

18. The device according to claim 16, characterized in that The polycrystalline silicon carbide (SiC) substrate includes grains less than or equal to 1 mm (millimeter) and has a non-columnar structure.

19. The device according to claim 16, characterized in that The warpage is less than or equal to 75 μm (micrometers).

20. The device according to claim 16, characterized in that The thickness is at least one of: between 150-1000 μm (micrometers), equal to 150 μm (micrometers), and equal to 1000 μm (micrometers).

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