Timer circuit, complex programmable logic device and server power supply circuit

Abstract

The utility model provides a timer circuit, a complex programmable logic device and a server power supply circuit, and belongs to the field of servers, the timer circuit comprises a monitoring control circuit and a timer main circuit; the monitoring control circuit is used for monitoring heartbeat signals; the timer main circuit is used for outputting an enable signal; and the monitoring control circuit is used for controlling the timer main circuit to work normally when the heartbeat signal is monitored, and is also used for outputting a high level to the reset signal input end of the timer main circuit and lasting for a preset time length when the heartbeat signal is not monitored. The output end of the timer main circuit is used for connecting a power supply chip; and the trigger end of the timer main circuit is used for receiving a power supply reset trigger signal to perform power-on and power-off control of the power supply chip. The complex programmable logic device and the server power supply circuit are respectively provided with the timer circuit. When the CPLD code is abnormal, the mainboard power supply is ensured to be normally powered on, so that the CPLD code can be re-burnt.

Description

Technical Field

[0001] The utility model relates to the field of servers, and in particular to a timer circuit, a complex programmable logic device and a server power supply circuit. Background Art

[0002] In current storage products, a timer circuit (such as a 555 timer circuit) is required to perform a power cycle test on the entire machine or to power on and off the 3.3V of the entire machine when a motherboard fails.

[0003] Specifically, the 3.3V power supply of the mainboard is controlled by setting the delay time of the timer circuit (usually 5 seconds for storage products). The trigger signal of the timer is sent by the CPLD, and the low level triggers the reset. The CPLD gives this signal a high level by default when powered on to ensure that the mainboard is powered on normally. After normal power-on, the CPLD puts the control signal in the register, which is managed by the BMC to perform the Power cycle test of the whole machine or complete the 3.3V power-on and power-off operation of the whole machine when the mainboard fails.

[0004] In the early stage of testing, if the CPLD code is abnormal (i.e., faulty), the CPLD code needs to be updated and improved, and it is often necessary to use online upgrades or use a JTAG burner to upgrade the CPLD code. When upgrading and burning the CPLD code, there is a phenomenon of unsuccessful burning, which causes the pin that controls the 3.3V power reset of the motherboard to be in an unknown state. If the pin is in a low level state, the 3.3V power supply will always be in a reset state, causing the motherboard 3.3V power supply to be unable to power on normally, and then causing the CPLD to be unable to power on. When the CPLD has no power, the 3.3V power enable signal will be powered on again by external pull-up. At this time, the CPLD starts to power on again. After the CPLD is powered on, because the code is not burned successfully, the reset signal of the 3.3V power supply will be pulled low again, causing the 3.3V power enable signal to be low, and the motherboard is powered off again. After that, it is in a power-on and power-off cycle state, and the CPLD code cannot be burned again. Utility Model Content

[0005] In order to solve the above problems, the utility model provides a timer circuit, a complex programmable logic device and a server power supply circuit to ensure that the 3.3V power supply of the mainboard can be powered on normally when the CPLD code is abnormal, so as to ensure that the CPLD code can be re-burned successfully.

[0006] In a first aspect, the technical solution of the utility model provides a timer circuit, which includes a monitoring control circuit and a timer main circuit;

[0007] The input end of the monitoring control circuit is used to monitor the heartbeat signal;

[0008] The timer main circuit is the main control circuit of the timer circuit;

[0009] The output terminal of the timer main circuit is used to output an enable signal;

[0010] The monitoring control circuit is connected to the reset signal input terminal of the timer main circuit, and is used to control the reset signal of the timer main circuit to be high level when a heartbeat signal is detected, so that the timer main circuit can work normally; it is also used to output a high level to the reset signal input terminal of the timer main circuit and maintain the high level for a preset time length t1 when no heartbeat signal is detected, so as to control the output terminal of the timer main circuit to output a high level and maintain the high level for a preset time length t1.

[0011] Furthermore, the output terminal of the timer main circuit is used to connect to a power chip;

[0012] The trigger end of the timer main circuit is used to receive a power reset trigger signal so as to control the power on and off of the power chip based on the power reset trigger signal.

[0013] Further, the monitoring control circuit includes a first monitoring controller U1, a first transistor Q1, a second transistor Q2, a second monitoring controller U2, a first capacitor C1, a second capacitor C2, a third transistor Q3 and a 12V power supply, wherein:

[0014] The input end of the monitoring and control circuit corresponds to the WD I pin of the first monitoring controller U1, and the WD I pin of the first monitoring controller U1 is used to receive the heartbeat signal; the output pin OUT1 of the first monitoring controller U1 is connected to the base of the first transistor Q1, and is connected to the first end of the first resistor R1; the second end of the first resistor R1 and the power pin VCC1 of the first monitoring controller U1 are both connected to the P3V3_WD I power supply; the GND pin of the first monitoring controller U1 is grounded;

[0015] The collector of the first transistor Q1 is connected to the first end of the second resistor R2 and the base of the second transistor Q2; the second end of the second resistor R2, the first end of the third resistor R3 and the first end of the fourth resistor are all connected to the 12V power supply;

[0016] The second end of the third resistor R3 is connected to the collector of the second triode Q2 and the trigger pin TRI G1 of the second monitoring controller U2; the emitter of the second triode Q2 and the emitter of the first triode Q1 are both grounded;

[0017] The second end of the fourth resistor is connected to the reset pin RESET1 of the second monitoring controller U2;

[0018] The GND pin of the second monitoring controller U2 is grounded;

[0019] The power pin VCC2 of the second monitoring controller U2 is connected to the 12V power supply and the first end of the fifth resistor R5; the second end of the fifth resistor R5 is connected to the first end of the second capacitor C2, and is connected to the DI SCH1 pin and the THRES1 pin of the second monitoring controller U2; the CONT1 pin of the second monitoring controller U2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are both grounded;

[0020] The output pin OUT2 of the second monitoring controller U2 is connected to the base of the third transistor Q3; the emitter of the third transistor Q3 is grounded; and the collector of the third transistor Q3 is connected to the reset signal input terminal of the timer main circuit.

[0021] Further, the timer main circuit includes a timer chip U3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a third capacitor C3, a fourth capacitor, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11, wherein:

[0022] The reset pin RESET2 of the timer chip U3 is the reset signal input terminal of the timer main circuit;

[0023] The reset pin RESET2 of the timer chip U3 is connected to the collector of the third transistor Q3;

[0024] The base of the fourth transistor Q4 is used to be connected to the second GPIO pin of the complex programmable logic device;

[0025] The collector of the fourth transistor Q4 is connected to the first end of the sixth resistor R6 and the base of the fifth transistor Q5; the second end of the sixth resistor R6, the first end of the seventh resistor R7 and the first end of the eighth resistor R8 are all connected to the 12V power supply;

[0026] The second end of the seventh resistor R7 and the trigger pin TRI G2 of the timer chip U3 are both connected to the collector of the fifth transistor Q5; the emitter of the fifth transistor Q5 and the emitter of the fourth transistor Q4 are both grounded;

[0027] The second end of the eighth resistor R8 is connected to the reset pin RESET2 of the timer chip U3;

[0028] The power pin VCC3 of the timer chip U3 is connected to the 12V power supply and the first end of the ninth resistor R9; the second end of the ninth resistor R9 is connected to the first end of the fourth capacitor C4, and is connected to the DI SCH2 pin and the THRES2 pin of the timer chip U3;

[0029] The CONT2 pin of the timer chip U3 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are both grounded;

[0030] The GND pin of the timer chip U3 is grounded;

[0031] The output pin OUT3 of the timer chip U3 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is grounded, the collector of the sixth transistor Q6, the first end of the tenth resistor R10 and the first end of the eleventh resistor R11 are all used to be connected to the enable terminal EN of the power chip; the second end of the tenth resistor R10 is connected to the 12V power supply; the second end of the eleventh resistor R11 is grounded.

[0032] Furthermore, the timer chip U3 adopts a 555 timer; the first monitoring controller U1 adopts a watchdog chip; and the second monitoring controller U2 adopts a timer chip.

[0033] In a second aspect, the utility model further provides a complex programmable logic device, which is equipped with the timer circuit described in the above aspects;

[0034] The complex programmable logic device has a first GPIO pin for outputting a heartbeat signal of the complex programmable logic device;

[0035] In the timer circuit, the input end of the monitoring control circuit is connected to the first GPIO pin of the complex programmable logic device to monitor the heartbeat signal of the complex programmable logic device.

[0036] Furthermore, the complex programmable logic device also has a second GPIO pin for outputting a power reset trigger signal;

[0037] The second GPIO pin of the complex programmable logic device is connected to the timer main circuit of the timer circuit to control the power-on and power-off operations of the 3.3V power chip based on the output power reset trigger signal.

[0038] Further, when the monitoring control circuit of the timer circuit includes a first monitoring controller U1, a first GPIO pin of the complex programmable logic device is connected to a WD I pin of the first monitoring controller U1, so that the first monitoring controller U1 receives a heartbeat signal of the complex programmable logic device through the WD I pin.

[0039] Further, when the timer main circuit of the timer circuit includes the fourth transistor Q4, the second GPIO pin of the complex programmable logic device is connected to the base of the fourth transistor Q4 for sending a power reset trigger signal to the base of the fourth transistor Q4.

[0040] In a third aspect, the utility model further provides a server power supply circuit, the server power supply circuit comprising a 3.3V power supply chip and also comprising the timer circuit described in the above aspects;

[0041] The output end of the 3.3V power chip is used to connect to the power pin of the server BMC and the power pin of the server CPLD; the server CPLD has a first GPIO pin and a second GPIO pin, the first GPIO pin is used to output the heartbeat signal of the CPLD, and the second GPIO pin is used to output the power reset trigger signal;

[0042] In the timer circuit, the output end of the timer main circuit is connected to the enable end EN of the 3.3V power chip, the input end of the monitoring control circuit is used to be connected to the first GPIO pin of the CPLD, and the trigger end of the timer main circuit is used to be connected to the second GPIO pin of the CPLD.

[0043] Compared with the prior art, the utility model has the following beneficial effects:

[0044] When the utility model is used, the CPLD can be connected to the input end of the monitoring control circuit to monitor the heartbeat signal of the CPLD through the monitoring control circuit, and the 3.3V power chip can be connected to the output end of the timer main circuit. When the heartbeat signal of the CPLD is normal, the reset signal of the timer main circuit can be released to make the timer main circuit work normally, which is then helpful to realize the power-off and power-on process of the main board power supply through the timer main circuit, so that the device executes the power cycle. In addition, it is also helpful to make the timer main circuit in a reset state through the monitoring control circuit when the CPLD code fails, so that the power supply of the CPLD is powered on, which is helpful to provide convenience for re-burning the CPLD code.

[0045] The utility model has reliable design principle, simple structure and very broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the utility model or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 It is a schematic principle block diagram of a timer circuit of an embodiment of the utility model;

[0048] Figure 2 yes Figure 1A schematic diagram of a usage state of the timer circuit;

[0049] Figure 3 is a schematic circuit diagram of a monitoring control circuit described in one embodiment of the utility model;

[0050] Figure 4 It is a schematic connection circuit diagram of the timer main circuit and the 3.3V power chip in one embodiment of the utility model;

[0051] Figure 5 A schematic diagram of the structure of a server power supply circuit provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0052] The core of the utility model is to provide a timer circuit, a complex programmable logic device and a server power supply circuit, so as to ensure that the 3.3V power supply of the mainboard can be powered on normally when the CPLD code is abnormal, and then ensure that the CPLD code can be re-burned.

[0053] In order to make the technical solution and advantages of the utility model clearer, the technical solution of the utility model will be described clearly and completely in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments.

[0054] The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0056] It should be noted that the present invention uses the words "first", "second" and the like to limit the corresponding parts only for the convenience of distinguishing the corresponding parts. If not otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0057] CPLD: The full name is Complex Programmable Logic Device. When CPLD works normally, the heartbeat signal frequency is 1Hz. When CPLD works abnormally (for example, the code runs abnormally), the heartbeat signal frequency is 0Hz.

[0058] BMC: Baseboard Management Controller, baseboard management controller.

[0059] Power cycle test: Power cycle test, the mainboard is powered on, off, and then powered on again.

[0060] Please refer to Figure 1 , which shows a schematic diagram of a timer circuit provided by an embodiment of the utility model.

[0061] like Figure 1 As shown, the timer circuit in this embodiment includes a monitoring control circuit and a timer main circuit.

[0062] The input end of the monitoring control circuit is used to monitor the heartbeat signal.

[0063] In this embodiment, the complex programmable logic device (i.e. Figure 2 Specifically, the complex programmable logic device has a first GPIO pin, and the first GPIO pin is used for the complex programmable logic device to output a heartbeat signal. Figure 2 shown.

[0064] In this embodiment, the first GPIO pin of the complex programmable logic device corresponds to Figure 2 GPIO1 in.

[0065] When in use, the input end of the monitoring control circuit is connected to the first GPIO pin of the complex programmable logic device CPLD to monitor the heartbeat signal of the complex programmable logic device.

[0066] The timer main circuit is the main control circuit of the timer circuit.

[0067] The output terminal of the timer main circuit is used to output an enable signal.

[0068] In this embodiment, the output end of the timer main circuit is used to connect to the power chip of the server, and the power chip adopts a 3.3V power chip. When in use, the output end of the timer main circuit is connected to the enable end EN of the 3.3V power chip. Figure 2 shown.

[0069] It should be noted that the power pin of the complex programmable logic device is electrically connected to the output end of the 3.3V power chip. The 3.3V power chip provides power for the complex programmable logic device.

[0070] In a specific implementation, the BMC of the server is electrically connected to the output end of the 3.3V power chip, and the 3.3V power chip provides power to the BMC.

[0071] Figure 2 FIG. 1 only shows an example in which a 3.3V power chip provides power to a complex programmable logic device CPLD. In fact, in a server, a 3.3V power chip also provides power to a BMC of the server.

[0072] When in use, if the output end of the timer main circuit outputs a high level to the enable end EN of the 3.3V power chip, the 3.3V power chip can be enabled and powered on. At this time, the 3.3V power chip can provide power to the complex programmable logic device. If the output end of the timer main circuit outputs a low level to the enable end EN of the 3.3V power chip, the 3.3V power chip is powered off.

[0073] In this embodiment, the monitoring control circuit is connected to the reset signal input terminal of the timer main circuit, and is used to control the reset signal of the timer main circuit to a high level when the heartbeat signal of the complex programmable logic device is monitored, that is, to release the reset signal of the timer main circuit so that the timer main circuit can work normally.

[0074] The monitoring control circuit is also used to output a high level to the reset signal input terminal of the timer main circuit and maintain the high level for a preset time length t1 when the heartbeat signal of the complex programmable logic device cannot be detected, so as to control the output terminal of the timer main circuit to output a high level to the enable terminal EN of the 3.3V power supply chip and maintain the high level for a time length t1, so that the 3.3V power supply chip can output 3.3V power normally within the time length t1.

[0075] It should be noted that those skilled in the art can set the specific value of the preset time length t1 according to actual needs. In this embodiment, t1 is greater than the time length required for the complex programmable logic device to re-burn the code. In this embodiment, under the premise of ensuring that t1 is greater than the time length required for the complex programmable logic device to re-burn the code, those skilled in the art can set the specific value of t1 according to actual conditions.

[0076] In this embodiment, the complex programmable logic device further has a second GPIO pin (corresponding to Figure 2 The second GPIO pin is used for complex programmable logic devices to output power reset trigger signals (i.e. Figure 2 3.3V power supply reset signal in the power supply).

[0077] The trigger end of the timer main circuit is used to be connected to the second GPIO pin of the complex programmable logic device, so that the complex programmable logic device can realize power on and off control of the 3.3V power chip based on the power reset trigger signal.

[0078] The utility model realizes the power on and off control of the 3.3V power chip based on the power reset trigger signal. Specifically, when the timer main circuit of the utility model works normally, the power reset trigger signal output by the second GPIO pin of the complex programmable logic device can realize the power on and off control of the 3.3V power chip.

[0079] The reset signal of the timer main circuit is controlled by the monitoring control circuit. That is, the monitoring control circuit is used for the reset control of the timer main circuit.

[0080] When in use, the trigger end of the timer main circuit is connected to the second GPIO pin of the complex programmable logic device. When the 3.3V power chip needs to be powered on and off, the complex programmable logic device can be controlled to send a power reset trigger signal to the trigger end of the timer main circuit through the second GPIO pin.

[0081] In this embodiment, Figure 3 As shown, the monitoring control circuit includes a first monitoring controller U1, a first transistor Q1, a second transistor Q2, a second monitoring controller U2, a first capacitor C1, a second capacitor C2, a third transistor Q3 and a 12V power supply, wherein:

[0082] The first monitoring controller U1 is used to be connected to the first GPIO pin of the complex programmable logic device through the WD I pin (i.e., the watchdog input pin) to receive the heartbeat signal of the complex programmable logic device; the output pin OUT1 of the first monitoring controller U1 is connected to the base of the first transistor Q1, and is connected to the first end of the first resistor R1; the second end of the first resistor R1 and the power pin VCC1 of the first monitoring controller U1 are both connected to the P3V3_WD I power supply; the GND pin of the first monitoring controller U1 is grounded;

[0083] The collector of the first transistor Q1 is connected to the first end of the second resistor R2 and the base of the second transistor Q2; the second end of the second resistor R2, the first end of the third resistor R3 and the first end of the fourth resistor are all connected to the 12V power supply;

[0084] The second end of the third resistor R3 is connected to the collector of the second triode Q2 and the trigger pin TRI G1 of the second monitoring controller U2; the emitter of the second triode Q2 and the emitter of the first triode Q1 are both grounded;

[0085] The second end of the fourth resistor is connected to the reset pin RESET1 of the second monitoring controller U2;

[0086] The GND pin of the second monitoring controller U2 is grounded;

[0087] The power supply pin VCC2 of the second monitoring controller U2 is connected to the 12V power supply and the first end of the fifth resistor R5; the second end of the fifth resistor R5 is connected to the first end of the second capacitor C2, and is connected to the DI SCH1 pin (i.e., the discharge pin) and the THRES1 pin (i.e., the threshold pin) of the second monitoring controller U2; the CONT1 pin of the second monitoring controller U2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are both grounded;

[0088] The output pin OUT2 of the second monitoring controller U2 is connected to the base of the third transistor Q3; the emitter of the third transistor Q3 is grounded; and the collector of the third transistor Q3 is connected to the reset signal input terminal of the timer main circuit.

[0089] The input end of the monitoring control circuit corresponds to the WD I pin of the first monitoring controller U1. In this embodiment, the WD I pin of the first monitoring controller U1 is connected to the first GPIO pin of the complex programmable logic device.

[0090] In this implementation, if Figure 4 As shown, the timer main circuit includes a timer chip U3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a third capacitor C3, a fourth capacitor, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11. Among them:

[0091] The reset pin RESET2 of the timer chip U3 is the reset signal input terminal of the timer main circuit;

[0092] The reset pin RESET2 of the timer chip U3 is connected to the collector of the third transistor Q3;

[0093] The base of the fourth transistor Q4 is used to be connected to the second GPIO pin of the complex programmable logic device;

[0094] The collector of the fourth transistor Q4 is connected to the first end of the sixth resistor R6 and the base of the fifth transistor Q5; the second end of the sixth resistor R6, the first end of the seventh resistor R7 and the first end of the eighth resistor R8 are all connected to the 12V power supply;

[0095] The second end of the seventh resistor R7 and the trigger pin TRI G2 of the timer chip U3 are both connected to the collector of the fifth transistor Q5; the emitter of the fifth transistor Q5 and the emitter of the fourth transistor Q4 are both grounded;

[0096] The second end of the eighth resistor R8 is connected to the reset pin RESET2 of the timer chip U3;

[0097] The power pin VCC3 of the timer chip U3 is connected to the 12V power supply and the first end of the ninth resistor R9; the second end of the ninth resistor R9 is connected to the first end of the fourth capacitor C4, and is connected to the DI SCH2 pin and the THRES2 pin of the timer chip U3;

[0098] The CONT2 pin of the timer chip U3 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are both grounded;

[0099] The GND pin of the timer chip U3 is grounded;

[0100] The output pin OUT3 of the timer chip U3 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is grounded, the collector of the sixth transistor Q6, the first end of the tenth resistor R10 and the first end of the eleventh resistor R11 are all used to be connected to the enable terminal EN of the 3.3V power chip; the second end of the tenth resistor R10 is connected to the 12V power supply; the second end of the eleventh resistor R11 is grounded.

[0101] In this embodiment, the timer chip U3 adopts a 555 timer; the first monitoring controller U1 adopts a watchdog chip; and the second monitoring controller U2 adopts a timer chip.

[0102] The above 3.3V power chip is a 3.3V power chip on the server motherboard. The power output end of the 3.3V power chip is also used to be electrically connected to the BMC of the server to provide power to the BMC.

[0103] When using:

[0104] 1. When the complex programmable logic device (CPLD) is powered on and operates normally, the CPLD can normally send a heartbeat signal through the first GPIO pin. In this case:

[0105] The first monitoring controller U1 can receive the CPLD heartbeat signal through the WD I pin, the dog feeding signal is normal, the output pin OUT1 of the first monitoring controller U1 does not output the reset signal, the signal of the base of the third transistor Q3 is high level, the signal of the base of the second transistor Q2 is low level, the trigger pin TRI G1 of the second monitoring controller U2 is high level, the output pin OUT2 of the second monitoring controller U2 has no output, the reset signal of the reset pin RESET2 of the timer chip U3 is high level, the timer main circuit works normally, and the CPLD can execute the power cycle command normally. Specifically, when the power cycle command is executed:

[0106] The GPIO2 pin of the CPLD outputs a mainboard 3.3V power reset signal (i.e., the power reset trigger signal). If a low-level 3.3V power reset signal is output, the fifth transistor Q5 is turned on, and the signal of the trigger pin TRI G2 of the timer chip U3 is low. The output pin OUT3 of the timer chip U3 outputs a high level for t2 seconds (t2 can be set by a person skilled in the art according to actual conditions, and is set to 5 seconds in this embodiment). At this time, the enable signal of the enable terminal EN of the 3.3V power chip is pulled low for 5 seconds through the sixth transistor Q6, and the 3.3V power chip is powered off. At this time, the mainboard 3.3V power supply modules in the server that are powered by the 3.3V power supply chip are all powered off (for example, the CPLD and BMC in the server that are powered by the 3.3V power supply chip are all powered off). 5 seconds after power failure, the output pin OUT3 of the timer chip U3 outputs a low level, the EN enable signal of the 3.3V power chip becomes a high level, and the 3.3V power chip is powered on normally again (that is, the 3.3V power chip is restored to provide 3.3V power to the outside). At this time, the components in the server that are powered by the 3.3V power chip (such as CPLD and BMC) are all powered and operate normally. The CPLD normally sends a heartbeat signal through the first GPIO pin, and the first monitoring controller U1 can normally receive the CPLD heartbeat signal through the WDI pin.

[0107] 2. When the complex programmable logic device (CPLD) fails to operate:

[0108] The first monitoring controller U1 cannot receive the heartbeat signal of the CPLD, and the dog feeding signal is abnormal. The output pin OUT1 of the first monitoring controller U1 sends a reset signal and outputs a low level. The reset signal of the timer chip (corresponding to the reset signal of the timer main circuit described in this specification) is a low level. After passing through transistors Q1 and Q2, the signal of the trigger pin TR I G1 of the second monitoring controller U2 is a low level. The output pin OUT2 of the second monitoring controller U2 outputs a high level for a time length of t1 (this time length t1 can be set by those skilled in the art according to actual conditions. t1 is greater than the time for the CPLD to re-burn the code. In this embodiment, it is set to 3 minutes). After passing through transistor Q3, the reset signal of the timer chip U3 is pulled low;

[0109] The reset signal of the timer chip U3 is pulled low, the timer chip U3 cannot work, the output pin OUT3 of the timer chip U3 has no output, the 3.3V power chip supplies power normally, the CPLD is powered, and the BMC powered by the 3.3V power chip is also powered;

[0110] The BMC cannot receive the CPLD heartbeat, so the CPLD code is re-burned. After the code is successfully burned (that is, the CPLD code is restored), the CPLD works normally and sends out a heartbeat signal.

[0111] The utility model can monitor the heartbeat signal of CPLD through the monitoring control circuit, and when the heartbeat signal of CPLD is normal, the reset signal of the timer main circuit is released, and the timer main circuit works normally at this time, and CPLD can realize the power-off and power-on process of the mainboard power supply through the timer main circuit, so that the device executes the power cycle.

[0112] When the heartbeat signal of the CPLD is abnormal, the utility model can pull up the reset signal of the timer main circuit. At this time, the timer main circuit is in a reset state and does not work. The corresponding enable signal of the mainboard power supply (i.e., the 3.3V power supply chip) is in a default state (i.e., a high level), and the mainboard power supply works normally. At this time, the BMC and the CPLD power supplies are normally supplied, and the CPLD code can be re-burned through the BMC or a burner.

[0113] After the CPLD code is restored, a 1Hz heartbeat signal is normally sent out. After the monitoring control circuit detects that the heartbeat signal of the CPLD is normal, the reset signal of the timer main circuit is released to make the timer main circuit work normally.

[0114] The utility model helps to reset the timer main circuit through the monitoring control circuit when the CPLD code fails to operate normally, so that the mainboard is powered on normally, and then helps to re-burn the CPLD code by using the BMC or the burner.

[0115] The utility model also provides a complex programmable logic device, which is equipped with the timer circuit described in any one of the above embodiments.

[0116] The complex programmable logic device has a first GPIO pin for outputting a heartbeat signal of the complex programmable logic device;

[0117] In the timer circuit, the input end of the monitoring control circuit is connected to the first GPIO pin of the complex programmable logic device to monitor the heartbeat signal of the complex programmable logic device.

[0118] Exemplarily, the complex programmable logic device also has a second GPIO pin for outputting a power reset trigger signal; the second GPIO pin of the complex programmable logic device is connected to the timer main circuit of the timer circuit to control the power-on and power-off operations of the 3.3V power chip based on the output power reset trigger signal.

[0119] Exemplarily, when the monitoring control circuit of the timer circuit includes a first monitoring controller U1, a first GPIO pin of the complex programmable logic device is connected to a WD I pin of the first monitoring controller U1, so that the first monitoring controller U1 receives a heartbeat signal of the complex programmable logic device through the WD I pin.

[0120] Exemplarily, when the timer main circuit of the timer circuit includes the fourth transistor Q4, the second GPIO pin of the complex programmable logic device is connected to the base of the fourth transistor Q4 for sending a power reset trigger signal to the base of the fourth transistor Q4.

[0121] The circuits of the above-mentioned complex programmable logic devices are not given in the specification drawings. Those skilled in the art can easily implement them based on the text records of this specification and the relevant drawings corresponding to the timer circuit.

[0122] The utility model also provides a server power supply circuit, such as Figure 5 As shown, the server power supply circuit includes a 3.3V power supply chip and also includes the timer circuit described in any one of the above embodiments. The output end of the 3.3V power supply chip is used to be connected to the power pin of the server BMC and the power pin of the server CPLD; the server CPLD has a first GPIO pin and a second GPIO pin, the first GPIO pin is used to output the heartbeat signal of the CPLD, and the second GPIO pin is used to output the power reset trigger signal;

[0123] In the timer circuit, the output end of the timer main circuit is connected to the enable end EN of the 3.3V power chip, the input end of the monitoring control circuit is used to connect to the first GPIO pin of the server CPLD, and the trigger end of the timer main circuit is used to connect to the second GPIO pin of the server CPLD.

[0124] When in use, the output end of the 3.3V power chip can be directly connected to the power pin of the server BMC and the power pin of the server CPLD respectively, the input end of the monitoring control circuit can be connected to the first GPIO pin of the server CPLD, and the trigger end of the timer main circuit can be connected to the second GPIO pin of the server CPLD.

[0125] The same and similar parts between the various embodiments in this specification can be referenced to each other.

[0126] The first monitoring controller U1, the second monitoring controller U2 and the timer chip U3 involved in the present invention can adopt the circuit forms and common models commonly used in the field. The present invention does not limit the specific models. Based on the knowledge scope of technical personnel in this field, the corresponding circuit forms and specific models can be anticipated to realize the functions of the present invention.

[0127] The hardware circuit structure of the utility model helps to capture the CPLD fault signal by real-time monitoring of the health status of the CPLD, so as to control the working status of the timer main circuit. In addition, when the CPLD code fails, the timer main circuit can be reset by monitoring the control circuit, so that the CPLD power supply is powered on, which provides convenience for R&D test personnel to re-burn the code, saves time and saves labor costs.

[0128] The hardware circuit structure of the utility model helps to ensure that the 3.3V power supply of the mainboard does not lose power when the CPLD code fails, which helps to provide the server with time to collect CPLD fault logs and provide a reliable basis for subsequent troubleshooting.

[0129] Although the utility model is described in detail by referring to the accompanying drawings and in combination with the preferred embodiments, the utility model is not limited thereto. Without departing from the spirit and essence of the utility model, ordinary technicians in the field can make various equivalent modifications or substitutions to the embodiments of the utility model, and these modifications or substitutions should be within the scope of the utility model / any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model shall be based on the protection scope of the claims.

Claims

1. A timer circuit, characterized in that: The timer circuit includes a monitoring control circuit and a timer main circuit; The input end of the monitoring control circuit is used to monitor the heartbeat signal; The timer main circuit is the main control circuit of the timer circuit; The output terminal of the timer main circuit is used to output an enable signal; The monitoring control circuit is connected to the reset signal input terminal of the timer main circuit, and is used to control the reset signal of the timer main circuit to be high level when a heartbeat signal is detected, so that the timer main circuit can work normally; it is also used to output a high level to the reset signal input terminal of the timer main circuit and maintain the high level for a preset time length t1 when no heartbeat signal is detected, so as to control the output terminal of the timer main circuit to output a high level and maintain the high level for a preset time length t1.

2. The timer circuit according to claim 1, characterized in that: The output end of the timer main circuit is used to connect the power chip; The trigger end of the timer main circuit is used to receive a power reset trigger signal so as to control the power on and off of the power chip based on the power reset trigger signal.

3. The timer circuit according to claim 2, characterized in that: The monitoring control circuit includes a first monitoring controller U1, a first transistor Q1, a second transistor Q2, a second monitoring controller U2, a first capacitor C1, a second capacitor C2, a third transistor Q3 and a 12V power supply, wherein: The input end of the monitoring and control circuit corresponds to the WD I pin of the first monitoring controller U1, and the WD I pin of the first monitoring controller U1 is used to receive the heartbeat signal; the output pin OUT1 of the first monitoring controller U1 is connected to the base of the first transistor Q1, and is connected to the first end of the first resistor R1; the second end of the first resistor R1 and the power pin VCC1 of the first monitoring controller U1 are both connected to the P3V3_WD I power supply; the GND pin of the first monitoring controller U1 is grounded; The collector of the first transistor Q1 is connected to the first end of the second resistor R2 and the base of the second transistor Q2; the second end of the second resistor R2, the first end of the third resistor R3 and the first end of the fourth resistor are all connected to the 12V power supply; The second end of the third resistor R3 is connected to the collector of the second triode Q2 and the trigger pin TRIG1 of the second monitoring controller U2; the emitter of the second triode Q2 and the emitter of the first triode Q1 are both grounded; The second end of the fourth resistor is connected to the reset pin RESET1 of the second monitoring controller U2; The GND pin of the second monitoring controller U2 is grounded; The power pin VCC2 of the second monitoring controller U2 is connected to the 12V power supply and the first end of the fifth resistor R5; the second end of the fifth resistor R5 is connected to the first end of the second capacitor C2, and is connected to the DISCH1 pin and the THRES1 pin of the second monitoring controller U2; the CONT1 pin of the second monitoring controller U2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 and the second end of the second capacitor C2 are both grounded; The output pin OUT2 of the second monitoring controller U2 is connected to the base of the third transistor Q3; the emitter of the third transistor Q3 is grounded; and the collector of the third transistor Q3 is connected to the reset signal input terminal of the timer main circuit.

4. The timer circuit according to claim 3, characterized in that: The timer main circuit includes a timer chip U3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a third capacitor C3, a fourth capacitor, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11, wherein: The reset pin RESET2 of the timer chip U3 is the reset signal input terminal of the timer main circuit; The reset pin RESET2 of the timer chip U3 is connected to the collector of the third transistor Q3; The base of the fourth transistor Q4 is used to be connected to the second GPIO pin of the complex programmable logic device; The collector of the fourth transistor Q4 is connected to the first end of the sixth resistor R6 and the base of the fifth transistor Q5; the second end of the sixth resistor R6, the first end of the seventh resistor R7 and the first end of the eighth resistor R8 are all connected to the 12V power supply; The second end of the seventh resistor R7 and the trigger pin TRIG2 of the timer chip U3 are both connected to the collector of the fifth transistor Q5; the emitter of the fifth transistor Q5 and the emitter of the fourth transistor Q4 are both grounded; The second end of the eighth resistor R8 is connected to the reset pin RESET2 of the timer chip U3; The power pin VCC3 of the timer chip U3 is connected to the 12V power supply and the first end of the ninth resistor R9; the second end of the ninth resistor R9 is connected to the first end of the fourth capacitor C4, and is connected to the DISCH2 pin and the THRES2 pin of the timer chip U3; The CONT2 pin of the timer chip U3 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 and the second end of the fourth capacitor C4 are both grounded; The GND pin of the timer chip U3 is grounded; The output pin OUT3 of the timer chip U3 is connected to the base of the sixth transistor Q6, the emitter of the sixth transistor Q6 is grounded, the collector of the sixth transistor Q6, the first end of the tenth resistor R10 and the first end of the eleventh resistor R11 are all used to be connected to the enable terminal EN of the power chip; the second end of the tenth resistor R10 is connected to the 12V power supply; the second end of the eleventh resistor R11 is grounded.

5. The timer circuit according to claim 4, characterized in that: The timer chip U3 adopts a 555 timer; the first monitoring controller U1 adopts a watchdog chip; and the second monitoring controller U2 adopts a timer chip.

6. A complex programmable logic device, characterized in that: The complex programmable logic device is provided with a timer circuit as described in any one of claims 1 to 5; The complex programmable logic device has a first GPIO pin for outputting a heartbeat signal of the complex programmable logic device; In the timer circuit, the input end of the monitoring control circuit is connected to the first GPIO pin of the complex programmable logic device to monitor the heartbeat signal of the complex programmable logic device.

7. The complex programmable logic device according to claim 6, characterized in that: The complex programmable logic device also has a second GPIO pin for outputting a power reset trigger signal; The second GPIO pin of the complex programmable logic device is connected to the timer main circuit of the timer circuit to control the power-on and power-off operations of the 3.3V power chip based on the output power reset trigger signal.

8. The complex programmable logic device according to claim 7, characterized in that: When the monitoring control circuit of the timer circuit includes the first monitoring controller U1, the first GPIO pin of the complex programmable logic device is connected to the WD I pin of the first monitoring controller U1, so that the first monitoring controller U1 receives the heartbeat signal of the complex programmable logic device through the WD I pin.

9. The complex programmable logic device according to claim 8, characterized in that: When the timer main circuit of the timer circuit includes the fourth transistor Q4, the second GPIO pin of the complex programmable logic device is connected to the base of the fourth transistor Q4 for sending a power reset trigger signal to the base of the fourth transistor Q4.

10. A server power circuit, comprising a 3.3V power chip, characterized in that: The server power supply circuit also includes a timer circuit as described in any one of claims 2 to 5; the output end of the 3.3V power supply chip is used to be connected to the power pin of the server BMC and the power pin of the server CPLD; the server CPLD has a first GPIO pin and a second GPIO pin, the first GPIO pin is used to output the heartbeat signal of the CPLD, and the second GPIO pin is used to output the power reset trigger signal; In the timer circuit, the output end of the timer main circuit is connected to the enable end EN of the 3.3V power chip, the input end of the monitoring control circuit is used to be connected to the first GPIO pin of the CPLD, and the trigger end of the timer main circuit is used to be connected to the second GPIO pin of the CPLD.

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