Display panel and display device

Abstract

The utility model discloses a display panel and a display device, and the display panel comprises a gate drive output line which is located in a non-display area and is connected with a gate drive circuit, and the gate drive output line is configured to transmit a to-be-detected gate signal in a preparation stage of the display panel; the plurality of first type power supply lines are located in the non-display area, and one first type power supply line is connected with one end, far away from the multiplexing circuit, of each data transmission line in the at least two data transmission lines; the first power line is located on the side, away from the display area, of the gate drive output line. Wherein the orthographic projection of the first type of power supply line on the substrate is a first projection area, and the orthographic projection of the gate drive output line and the first power line on the substrate is a second projection area; the first projection area is located in the second projection area. The grid driving output line and the first power line are stable signals, so that the first type of power supply line is not influenced by a jump signal, and the uniformity of the display image quality is further ensured.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display panels (backlight modules) are mainly used in various types of display devices, such as laptops, flat-panel TVs, mobile phones, car dashboards, billboards, airport terminal display screens, etc. In order to reduce the border of the display device, a multiplexing circuit is often used to reduce the number of data lines on the border, thereby achieving the purpose of reducing the border. However, the power supply line connected to the multiplexing circuit will pass over the jump signal line, which will cause the power supply line to be affected by the jump, and ultimately affect the uniformity of the display quality. Utility Model Content

[0003] The purpose of the present application is to provide a display panel and a display device.

[0004] According to a first aspect of an embodiment of the present application, a display panel is provided, the display panel comprising: a base substrate comprising a display area and a non-display area surrounding the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] a plurality of data lines, located in the display area and extending to the non-display area, the plurality of data lines being electrically connected to the plurality of sub-pixels;

[0007] A plurality of data transmission lines are located in the non-display area;

[0008] A plurality of multiplexing circuits, located in the non-display area, each of the multiplexing circuits comprising a plurality of multiplexing sub-units, one of the plurality of data transmission lines being electrically connected to at least two of the data lines via one of the plurality of multiplexing sub-units, the one multiplexing sub-unit being configured to transmit a data signal transmitted by one of the data transmission lines to the at least two data lines in different time periods in time-sharing manner;

[0009] a plurality of gate lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to transmit gate signals to the plurality of sub-pixels;

[0010] A gate driving circuit, located in the non-display area and electrically connected to the plurality of gate lines;

[0011] a gate drive output line, located in the non-display area and connected to the gate drive circuit, the gate drive output line being configured to transmit a gate signal to be detected during a display panel preparation stage;

[0012] a plurality of first-type power supply lines, located in the non-display area, and one of the first-type power supply lines is connected to an end of each of the at least two data transmission lines away from the multiplexing circuit;

[0013] A first power line, located at a side of the gate drive output line away from the display area;

[0014] The orthographic projection of the first type of power supply line on the base substrate is a first projection area, and the orthographic projection of the gate drive output line and the first power supply line on the base substrate is a second projection area;

[0015] The first projection area is located within the second projection area.

[0016] In some embodiments, the extension direction of the first type of power supply line coincides with the extension direction of some line segments in the gate drive output line, and in the direction perpendicular to the extension direction of the first type of power supply line, the orthographic projection of the first type of power supply line on the substrate and the orthographic projection of some line segments in the gate drive output line on the substrate at least partially overlap.

[0017] In some embodiments, the orthographic projection of the first-type power supply line on the substrate is located within the orthographic projection of a portion of the gate driving output line on the substrate.

[0018] In some embodiments, along a direction perpendicular to an extension direction of the first-type power supply line, a ratio of a width of the first-type power supply line to a width of a portion of line segments in the gate drive output line is less than or equal to 1.

[0019] In some embodiments, along a direction perpendicular to the extension direction of the first-type power supply line, opposite side boundaries of some line segments in the gate driving output line exceed opposite side boundaries of the corresponding first-type power supply line.

[0020] In some embodiments, the orthographic projection of the first-type power supply line on the substrate coincides with the orthographic projection of a portion of line segments in the gate driving output line on the substrate.

[0021] In some embodiments, the orthographic projection of the first-type power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments of the first power supply line on the substrate.

[0022] In some embodiments, the orthographic projection of the first-type power supply line on the substrate is located within the orthographic projection of the substrate.

[0023] In some embodiments, the multiple data transmission lines include multiple first data transmission lines and multiple second data transmission lines, the multiple first data transmission lines and the multiple second data transmission lines are respectively located on both sides of the multiple first-type power lines, and each second data transmission line is connected to at least two first data transmission lines through one of the first-type power lines.

[0024] In some embodiments, the plurality of multiplexing circuits include at least a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a plurality of the multiplexing subunits having the same number;

[0025] The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line;

[0026] The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line;

[0027] The length of the first line is greater than the length of the second line; and a ratio of a resistance of the first line to a resistance of the second line is used as a first ratio, a ratio of a length of the first line to a length of the second line is used as a second ratio, and a ratio of a length of the second line to a length of the first line is used as a third ratio;

[0028] The first ratio is smaller than the second ratio, and the first ratio is larger than the third ratio.

[0029] In some embodiments, the resistivity of the first wire is smaller than the resistivity of the second wire, and / or the cross-sectional area of ​​the first wire is smaller than the cross-sectional area of ​​the second wire.

[0030] In some embodiments, the orthographic projection of the second line on the substrate falls within the orthographic projection of the gate drive output line on the substrate, and the orthographic projection area of ​​the first line on the substrate is larger than the orthographic projection area of ​​the gate drive output line on the substrate.

[0031] In some embodiments, the first ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0032] In some embodiments, the gate driving circuit includes a plurality of gate driving sub-circuits, and at least one gate driving sub-circuit of the plurality of gate driving sub-circuits is disposed between two adjacent multiplexing sub-units in the first multiplexing circuit.

[0033] In some embodiments, the display panel further includes a compensation line, the multiple multiplexing circuits include at least a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a plurality of the multiplexing subunits having the same number;

[0034] The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line;

[0035] The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line;

[0036] The second line includes a first portion and a second portion;

[0037] The length of the first line is greater than that of the second line, and the compensation line is disposed between the first portion and the second portion and connected to the first portion and the second portion.

[0038] In some embodiments, the ratio of the sum of the length of the compensation line and the length of the second line to the length of the first line is taken as a fourth ratio, and the fourth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0039] In some embodiments, it further includes a plurality of light emitting control lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of light emitting control lines being configured to transmit light emitting control signals to the plurality of sub-pixels;

[0040] A light emitting control circuit, located in the non-display area and electrically connected to the plurality of light emitting control lines;

[0041] a light emitting control output line, located in the non-display area and connected to the light emitting control circuit, wherein the light emitting control output line is configured to transmit a light emitting control signal to be detected during a display panel preparation stage;

[0042] a plurality of second-type power supply lines, located in the non-display area, and one second-type power supply line is connected to an end of each of the at least two data transmission lines away from the multiplexing circuit;

[0043] A second power line, located at a side of the light emitting control output line away from the display area;

[0044] The orthographic projection of the second type power supply line on the base substrate is a third projection area, and the orthographic projection of the light emitting control output line and the second power supply line on the base substrate is a fourth projection area;

[0045] The third projection area is located within the fourth projection area.

[0046] In some embodiments, the extension direction of the second type of power supply line coincides with the extension direction of some line segments in the light-emitting control output line, and in the direction perpendicular to the extension direction of the second type of power supply line, the orthographic projection of the second type of power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments in the light-emitting control output line on the substrate.

[0047] In some embodiments, the orthographic projection of the second-type power supply line on the base substrate is located within the orthographic projection of a portion of the light-emitting control output line on the base substrate.

[0048] In some embodiments, along a direction perpendicular to an extending direction of the second-type power supply line, a ratio of a width of the second-type power supply line to a width of a portion of line segments in the light-emitting control output line is less than or equal to 1.

[0049] In some embodiments, along a direction perpendicular to the extension direction of the second-type power supply line, opposite side boundaries of some line segments in the light-emitting control output line exceed opposite side boundaries of the corresponding second-type power supply line.

[0050] In some embodiments, the orthographic projection of the second-type power supply line on the base substrate coincides with the orthographic projection of a portion of line segments in the light-emitting control output line on the base substrate.

[0051] In some embodiments, the orthographic projection of the second-type power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments of the second power supply line on the substrate.

[0052] In some embodiments, the orthographic projection of the second-type power supply line on the substrate is located within the orthographic projection of the substrate.

[0053] In some embodiments, each of the multiplexing circuits includes a first control unit and a second control unit, the first control unit and the second control unit are respectively connected to one of the data lines, and the first control unit and the second control unit share one of the data transmission lines.

[0054] In some embodiments, the multiplexing circuit further includes a third control unit, the first control unit, the second control unit and the third control unit are respectively connected to one of the data lines, and the first control unit, the second control unit and the third control unit share one of the data transmission lines.

[0055] In some embodiments, the plurality of multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a plurality of the multiplexing subunits having the same number;

[0056] The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line in the third multiplexing circuit is used as a third line;

[0057] The plurality of multiplexing subunits in the fourth multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line in the fourth multiplexing circuit is used as a fourth line;

[0058] The third line length is greater than the fourth line length; and a ratio of the third line resistance to the fourth line resistance is used as a fifth ratio, a ratio of the third line length to the fourth line length is used as a sixth ratio, and a ratio of the fourth line length to the third line length is used as a seventh ratio;

[0059] The fifth ratio is greater than the seventh ratio, and the fifth ratio is less than the sixth ratio.

[0060] In some embodiments, the resistivity of the third line is smaller than the resistivity of the fourth line, and / or the cross-sectional area of ​​the third line is smaller than the cross-sectional area of ​​the fourth line.

[0061] In some embodiments, the orthographic projection of the fourth line on the substrate falls within the orthographic projection of the light-emitting control output line on the substrate, and the orthographic projection area of ​​the third line on the substrate is larger than the orthographic projection area of ​​the light-emitting control output line on the substrate.

[0062] In some embodiments, the fifth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0063] In some embodiments, the display panel further includes a compensation line, the multiple multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a plurality of the multiplexing subunits having the same number;

[0064] The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line connected to the plurality of multiplexing subunits in the third multiplexing circuit is used as a third line;

[0065] The plurality of multiplexing subunits of the fourth multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line connected to the plurality of multiplexing subunits in the fourth multiplexing circuit is used as a fourth line;

[0066] The fourth line includes the third part and the fourth part;

[0067] The length of the third line is greater than that of the fourth line, and the compensation line is disposed between the third portion and the fourth portion and connected to the third portion and the fourth portion.

[0068] In some embodiments, the ratio of the sum of the length of the compensation line and the length of the fourth line to the length of the third line is taken as an eighth ratio, and the eighth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0069] According to a second aspect of an embodiment of the present application, a display device is provided, wherein the display device includes the display panel as described in the above embodiment.

[0070] The display panel of the present application arranges the first type of power supply line between the gate drive output line, the first power supply line and the part between the two along the orthographic projection of the substrate substrate. Since the gate drive output line and the first power supply line are stable signals, the first type of power supply line will not be affected by the jump signal, thereby ensuring the uniformity of the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0072] Figure 1 Schematic diagram of the structure of the display device according to the present application.

[0073] Figure 2 for Figure 1 A schematic diagram of the structure of an exemplary multiplexing circuit at C in FIG.

[0074] Figure 3 for Figure 1 A schematic diagram of the structure of a multiplexing circuit at C in the middle.

[0075] Figure 4 for Figure 1 Schematic diagram of the structure of another multiplexing circuit at C in the middle.

[0076] Figure 5 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the figure.

[0077] Figure 6 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0078] Figure 7 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0079] Figure 8 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0080] Fig. 9 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0081] Fig.10 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0082] Fig.11 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0083] Fig.12 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0084] Fig.13 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the middle.

[0085] Fig.14 for Figure 1 A schematic diagram of the structure of a multiplexing circuit at D in the figure.

[0086] Fig.15 for Figure 1 Schematic diagram of the structure of another multiplexing circuit at D in the figure.

[0087] Fig.16 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0088] Fig.17 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0089] Fig.18 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0090] Fig.19 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0091] Fig. 20 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0092] Fig.21 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0093] Fig. 22 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0094] Fig.23 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0095] Fig.24 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at F in the middle.

[0096] Fig.25 for Figure 1 A cross-sectional view of a sub-pixel S in the display area A taken along a-a'.

[0097] Fig.26 for Figure 1 A schematic diagram of the structure of another multiplexing circuit at E in the figure.

[0098] Fig. 27 for Fig.26 A schematic plan view of a semiconductor layer after forming a multiplexing circuit.

[0099] Fig.28 for Fig.26 A plan view of the circuit after the first gate metal layer of the multiplexing circuit is formed.

[0100] Fig.29 for Fig.26 A plan view of a circuit after forming a second gate metal layer of a multiplexing circuit.

[0101] Fig.30 for Fig.26 Schematic diagram of a plan view after forming an insulating layer between layers of a multiplexing circuit.

[0102] Fig.31 for Fig.26 A plan view of the multiplexing circuit after the first source and drain metal layer is formed. DETAILED DESCRIPTION

[0103] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0104] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and / or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0105] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0106] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0107] The use of "adapted to" or "configured to" in this specification is meant to be open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0108] The triangles, rectangles, trapezoids, pentagons or hexagons used in the specification and claims of this application are not in a strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0109] The term "about" as used in the specification and claims of this application refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0110] The transistors used in the present application can be triodes, thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present application, in order to distinguish the two electrodes of the transistor except the control electrode, one of the electrodes is called the first electrode and the other is called the second electrode.

[0111] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0112] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0113] In an exemplary embodiment, reference Figure 1 and Figure 2 As shown, Figure 1 This is the overall picture of the display panel. Figure 2 for Figure 1 An example diagram at C in the figure. In the design of narrow-border display panels, such as display panels on wearable products, multiplexing circuits 100 are often used to reduce the number of data lines 600 on the border, thereby achieving the purpose of reducing the border. The data lines 600 extend from the display area A to the multiplexing circuit 100 in the non-display area B. After passing through the multiplexing circuit 100, the number of the originally large number of data lines 600 is reduced, thereby achieving a smaller border. The data lines 600 are used to transmit data signals. The line segments of the data lines 600 located in the non-display area B after passing through the multiplexing circuit 100 can also be called data transmission lines (such as data transmission lines 112), which are used to transmit data signals. Reference Figure 2 As shown, the multiplexing circuit 100 generally includes a plurality of multiplexing subunits 110, each of the multiplexing subunits 110 is connected to a plurality of the data lines 600, and is used to control the pixel units located in the display area A, and the plurality of data transmission lines connected to the plurality of the multiplexing subunits 110 are interconnected via a first type power supply line 200.

[0114] The multiplexing subunit 110 includes multiple multiplexing control lines 111, a data transmission line 112 and multiple control units (for example, a first control unit 113, a second control unit 114 and a third control unit 115). The multiple data lines 600, the multiple multiplexing control lines 111 and the data transmission line 112 are electrically connected to a multiplexing subunit 110 respectively. The multiple control units and the multiple multiplexing control lines 111 in a multiplexing subunit 110 are arranged between the gate drive output line 310 and the display area A, and the multiple control units are located on the side of the multiple multiplexing control lines 111 close to the display area A and are located in the non-display area B. The data transmission line 112 is electrically connected to the first type power supply line 200 across the multiple multiplexing control lines 111, and one first type power supply line 200 is connected to the multiple data transmission lines 112.

[0115] like Figure 2 As shown, the multiplexing subunit 110 has a plurality of multiplexing control lines 111, wherein the first type of power supply line 200 connects the data transmission lines 112 corresponding to at least two adjacent multiplexing subunits 110. However, since the multiplexing control line 111 is a jump signal line, the first type of power supply line 200 passing over the multiplexing control line 111 may be affected by the jump signal, so it is necessary to minimize the overlap of the first type of power supply line 200 with the multiplexing control line 111. Furthermore, the first type of power supply line 200 is overlapped with the gate drive output line 310 and / or with the first power line 510, thereby preventing the first type of power supply line 200 from being affected by the jump signal.

[0116] The present application provides a display panel, including: a base substrate 10, multiple sub-pixels S, multiple data lines 600, multiple data transmission lines 112, multiple multiplexing circuits 100, multiple gate lines 1010, a gate driving circuit 1000, a gate driving output line 310, multiple first-class power supply lines 200 and a first power supply line 510. The substrate 10 includes a display area A and a non-display area B surrounding the display area A; a plurality of sub-pixels S are located in the display area A; a plurality of data lines 600 are located in the display area A and extend to the non-display area B, the plurality of data lines 600 are electrically connected to the plurality of sub-pixels S, and the plurality of data lines 600 are configured to provide data signals to the plurality of sub-pixels S; a plurality of data transmission lines 112 are located in the non-display area B; a plurality of multiplexing circuits 100 are located in the non-display area B, one of the plurality of data transmission lines 112 is electrically connected to at least two of the data lines 600 through a multiplexing sub-unit 110 in the multiplexing circuit 100, and the multiplexing sub-unit 110 is configured to transmit the data signal transmitted by one of the data transmission lines 112 to the at least two data lines 600 in different time periods in time-sharing manner; a plurality of gate lines 1010 are located in the display area A and are electrically connected to the plurality of sub-pixels S, and the plurality of gate lines 1010 are configured to transmit the data signals transmitted by the plurality of data transmission lines 112 to the at least two data lines 600 in different time periods; The gate drive circuit 1000 is located in the non-display area B and is electrically connected to the plurality of gate lines 1010; the gate drive output line 310 is located in the non-display area B and is connected to the gate drive circuit 1000, and the gate drive output line 310 is configured to transmit the gate signal to be detected to an external detection device during the display panel preparation stage; a plurality of first-class power supply lines 200 are located in the non-display area B, and one of the first-class power supply lines 200 is connected to an end of each of the at least two data transmission lines 112 away from the multiplexing sub-unit 110; the first power supply line 510 is located on the side of the gate drive output line 310 away from the display area A; wherein the orthographic projection of the first-class power supply line 200 on the base substrate 10 is a first projection area, and the orthographic projections of the gate drive output line 310 and the first power supply line 510 on the base substrate 10 are a second projection area; the first projection area is located within the second projection area.

[0117] refer to Figure 3 and Figure 4 As shown, the first projection area is the area from the side of the first type of power supply line 200 close to the display area A to the side of the first type of power supply line 200 away from the display area A, and the second projection area is the area from the end of the gate drive output line 310 close to the display area A to the first power line 510 away from the display area A.

[0118] Based on the above description, the first projection area overlaps with the second projection area, for example, the first projection area is located within the second projection area. Since the gate drive output line 310 and the first power line 510 are both stable signals, the first type of power supply line 200 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0119] Optional, reference Figure 4 As shown, the extension direction of the first type power supply line 200 coincides with the extension direction of some line segments in the gate drive output line 310, and in the direction perpendicular to the extension direction of the first type power supply line 200, the orthographic projection of the first type power supply line 200 on the base substrate 10 and the orthographic projection of some line segments in the gate drive output line 310 on the base substrate 10 at least partially overlap. It should be noted that the extension direction is Figure 3 or Figure 4 The direction of the gate drive output line 310 and the first type of power supply line 200, that is, the tracks of the two are substantially the same, and the two are substantially parallel. Based on the above description, since the orthographic projection of the first type of power supply line 200 on the base substrate 10 and the orthographic projection of some line segments in the gate drive output line 310 on the base substrate 10 at least partially overlap, when performing layout design, the first type of power supply line 200 can be arranged close to the gate drive output line 310, thereby reserving more space for other routing lines arranged on the first power line 510.

[0120] For further reference, Figure 6 As shown, the orthographic projection of the first type power supply line 200 on the base substrate 10 is located within the orthographic projection of the gate drive output line 310. The above statement means that along the direction perpendicular to the extension direction of the first type power supply line 200, the ratio of the width of the first type power supply line 200 to the width of the partial line segment of the gate drive output line 310 is less than or equal to 1.

[0121] Based on the above settings, the orthographic projection of the first type of power supply line 200 on the base substrate 10 is completely located within the orthographic projection of the gate drive output line 310. Since the gate drive output line 310 is a stable signal, the first type of power supply line 200 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0122] Continue to refer Figure 6As shown, along the direction perpendicular to the extension direction of the first type power supply line 200, the two opposite sides of the partial line segments in the gate drive output line 310 exceed the two opposite sides of the corresponding first type power supply line 200. In this way, the orthographic projection of the first type power supply line 200 on the base substrate 10 is completely located within the orthographic projection of the partial line segments in the gate drive output line 310 on the base substrate 10, which can prevent interference from the jump signal to the greatest extent.

[0123] refer to Figure 5 As shown, the orthographic projection of the first type power supply line 200 on the base substrate 10 coincides with the orthographic projection of a portion of the gate driving output line 310 on the base substrate 10 .

[0124] That is, the first type power supply line 200 is arranged above the gate driving output line 310 along the thickness direction. Such arrangement can free up more areas of the base substrate 10 for wiring.

[0125] refer to Figure 7 As shown, the orthographic projection of the first type power supply line 200 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the first power supply line 510 on the base substrate 10. Since the orthographic projection of the first type power supply line 200 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the first power supply line 510 on the base substrate 10, during layout design, the first type power supply line 200 can be arranged close to the first power supply line 510, thereby reserving more space for setting other routing lines.

[0126] refer to Figure 8 As shown, the orthographic projection of the first type power supply line 200 on the base substrate 10 is located within the orthographic projection of the first power line 510. That is, the first type power supply line 200 is arranged above the first power line 510 in the thickness direction, and such an arrangement can free up more areas of the base substrate 10 for wiring.

[0127] In one embodiment, reference Figure 3-Figure 7 As shown, the multiple data transmission lines 112 include multiple first data transmission lines 112a and multiple second data transmission lines 112b, and the multiple first data transmission lines 112a and the multiple second data transmission lines 112b are respectively located on both sides of the multiple first-type power supply lines 200, and each second data transmission line 112b is connected to at least two first data transmission lines 112a through one first-type power supply line 200, for example, one first-type power supply line 200 is connected to 2 or 3 first data transmission lines 112a.

[0128] Based on the above configuration, one second data transmission line 112b corresponds to multiple first data transmission lines 112a, and the first data transmission line 112a is connected to multiple data lines 600 through a multiplexing subunit 110. In this way, multiple data lines 600 can correspond to one first data transmission line 112a, and multiple first data transmission lines 112a correspond to one second data transmission line 112b, and thus the routing of the transmission data signal in the non-display area B can be reduced through this structure, that is, multiple data lines 600 are connected to one multiplexing subunit 110, one multiplexing subunit 110 is connected to one first data transmission line 112a, and the number of one first data transmission line 112a is reduced relative to the number of multiple data lines 600, thereby achieving a narrow frame. Multiple first data transmission lines 112a are connected to one first-type power supply line 200, and one first-type power supply line 200 is connected to one second data transmission line 112b, and the number of one second data transmission line 112b is reduced relative to the number of multiple first data transmission lines 112a, thereby achieving a narrow frame.

[0129] The ratio of the number of the first data transmission lines 112a corresponding to each multiplexing subunit 110 to the number of the plurality of data lines 600 may be 1 / n, where n is an integer greater than or equal to 2, for example, n may be 2, 3, 6, etc. The ratio of the number of the second data transmission lines 112b corresponding to each multiplexing subunit 110 to the number of the plurality of first data transmission lines 112a may be 1 / m, where m is an integer greater than or equal to 2, for example, m may be 2, 3, 4, 5, etc.

[0130] In one embodiment, reference Figure 5 and Fig. 9As shown, the multiplexing circuit 100 at least includes a first multiplexing circuit 410 and a second multiplexing circuit 420, and the first multiplexing circuit 410 and the second multiplexing circuit 420 both include a plurality of the multiplexing subunits 110 of the same number; the plurality of the multiplexing subunits 110 in the first multiplexing circuit 410 are connected through the first type of power supply line 200, and the first type of power supply line 200 connected to the plurality of the multiplexing subunits 110 in the first multiplexing circuit 410 is used as the first line 210; the plurality of the multiplexing subunits 110 in the second multiplexing circuit 420 are connected through the first type of power supply line 200, and the first type of power supply line 200 connected to the plurality of the multiplexing subunits 110 in the second multiplexing circuit 420 is used as the second line 220. The length L1 of the first line is greater than the length L2 of the second line. Furthermore, the resistance of the first line and the resistance of the second line are taken as a first ratio M1, the ratio of the length L1 of the first line and the length L2 of the second line are taken as a second ratio M2, and the ratio of the length L2 of the second line and the length L1 of the first line are taken as a third ratio M3. The first ratio M1 is greater than the third ratio M3, and the first ratio M1 is less than the second ratio M2.

[0131] It should be noted that the reference Figure 5 and Fig. 9As shown, when the first wire 210 and the second wire 220 are made of the same material and the cross-sectional area S of the first wire 210 and the second wire 220 are the same, the cross-sectional area S here is the cross-sectional area along the width direction H. The first ratio M1 should be equal to the second ratio M2. In this embodiment, the first ratio M1 is set to be greater than the third ratio M3, and the first ratio M1 is set to be less than the second ratio M2, which means that the values ​​of the first wire resistance R1 and the second wire resistance R2 become closer. For example: the length L1 of the first wire is set to 2, and the length L2 of the second wire is set to 1, so the corresponding value of the second ratio M2 is 2. The length L1 of the first wire and the length L2 of the second wire can be um or mm, which is not limited here. Under normal circumstances, the first ratio M1 is equal to the second ratio M2, so the value of the first ratio M1 is equal to 2, and the value of the third ratio M3 is equal to 1 / 2. Since the first ratio M1 is set to be less than the second ratio M2 in this embodiment, the value of the second ratio M2 in this embodiment should be less than 2. There are two ways to reduce the value of the second ratio M2: the first is to increase the value of the second line resistor R2; the second is to reduce the value of the first line resistor R1. Both of the above methods can reduce the gap between the first line resistor R1 and the second line resistor R2. However, if the value of the second line resistor R2 is increased too much, or the value of the first line resistor R1 is reduced too little, the gap between the first line resistor R1 and the second line resistor R2 may be larger, for example: the value of the original first line resistor R1 is set to 2, and the value of the original second line resistor R2 is set to 1. If the value of the second line resistor R2 is increased to 5, or the value of the first line resistor R1 is reduced to 0.1, although the first ratio M1 is smaller than the second ratio M2, the gap between the first line resistor R1 and the second line resistor R2 becomes larger. Therefore, the first ratio M1 is set to be greater than the third ratio M3, and the value of the second line resistor R2 increase and the value of the first line resistor R1 reduction can only be within the range of the reduction of the ratio of the two. For example: the value of the original first line resistor R1 is set to 2, and the value of the original second line resistor R2 is set to 1. Increasing the value of the second line resistance R2 to 2, or reducing the value of the first line resistance R1 to 1, can reduce the difference between the first line resistance R1 and the second line resistance R2. Since the difference between the first line resistance R1 and the second line resistance R2 is reduced, the inconsistency in transmission and loading speed between the two lines caused by the difference between the length L1 of the first line and the length L2 of the second line can be compensated, thereby improving the uniformity of image quality.

[0132] The inventor has found through a large number of experiments that when the first ratio M1 is too small or too large, the transmission and loading speeds between the first line 210 and the second line 220 differ greatly, resulting in inconsistent image quality, which in turn leads to a poor user experience. In this embodiment, the first ratio M1 is set to be greater than or equal to 0.8 and less than or equal to 1.2. Within this range, the transmission and loading speeds between the first line 210 and the second line 220 are basically the same, and the image quality is almost the same in visual experience, thereby improving the user experience.

[0133] It should be noted that the formula of resistance is R=ρL / S, where R is resistance, S is cross-sectional area, L is length, and ρ is resistivity. Under the premise that the length L1 of the first line is greater than the length L2 of the second line, in order to make the value of the first ratio M1 greater than or equal to 0.8 and less than or equal to 1.2, on the one hand, the resistivity of the first line 210 can be set to be smaller than the resistivity of the second line 220. On the other hand, the cross-sectional area of ​​the first line 210 can be set to be larger than the cross-sectional area of ​​the second line 220. According to the above formula, it can be known that under the premise that other conditions remain unchanged, setting the resistivity of the first line 210 to be smaller than the resistivity of the second line 220 can increase the resistance of the first line 210, thereby making the value of the first ratio M1 closer to 1, and thus making the transmission and loading speeds between the first line 210 and the second line 220 close. Similarly, according to the above formula, under the premise that other conditions remain unchanged, setting the cross-sectional area of ​​the first line 210 to be larger than the cross-sectional area of ​​the second line 220 can reduce the resistance of the first line 210, thereby making the value of the first ratio M1 closer to 1, and thus making the transmission and loading speeds between the first line 210 and the second line 220 close.

[0134] In order to achieve the above goals, refer to Figure 6 As shown, the orthographic projection of the second line 220 on the base substrate 10 can be set to fall within the orthographic projection of the gate drive output line 310 on the base substrate 10, referring to Fig. 9 As shown, the orthographic projection area of ​​the first line 210 on the base substrate 10 is set to be larger than the orthographic projection area of ​​a partial line segment of the gate driving output line 310 on the base substrate 10 .

[0135] Through the above settings, when the thickness of the first line 210 and the second line 220 are the same, it can be known that the cross-sectional area of ​​the first line 210 is larger than the cross-sectional area of ​​the second line 220. According to the formula R=ρL / S, the resistance R2 of the second line becomes larger than the resistance of the first line 210, so that the value of the first ratio M1 is closer to 1, and the transmission and loading speeds between the first line 210 and the second line 220 are close.

[0136] refer to Figure 1 and Fig. 9 As shown, the gate driving circuit 1000 includes a plurality of gate driving sub-circuits. Since the length L1 of the first line is greater than the length L2 of the second line, the display panel gate driving sub-circuit can be arranged between two adjacent multiplexing sub-units 110 in the first multiplexing circuit 410. Such an arrangement can make full use of the space between the multiplexing sub-units 110, thereby making the non-display area B of the display panel more compact, thereby making the display panel frame smaller and providing more functions for the display panel.

[0137] In one embodiment, reference Fig.10 , Fig.11 as well as Fig.12 As shown, the second line 220 includes a first portion 221 and a second portion 222; the length of the first line 210 is greater than the length of the second line 220, and the compensation line 700 is arranged between the first portion 221 and the second portion 222, and is connected to the first portion 221 and the second portion 222. Based on this, the transmission and loading speed of the connection between the multiplexing subunits 110 of the first multiplexing circuit 410 is slow, and the transmission and loading speed of the connection between the multiplexing subunits 110 of the second multiplexing circuit 420 is fast. Since the compensation line 700 has a certain resistance, the compensation line 700 can be arranged to slow down the transmission and loading speed of the connection between the multiplexing subunits 110 of the second multiplexing circuit 420, so that the transmission and loading speed of the connection between the multiplexing subunits 110 of the second multiplexing circuit 420 is close. Such a setting can change the transmission and loading speed of the connection between the multiplexing subunits 110 while basically not changing the original design of other parts.

[0138] In addition, refer to Fig.12 As shown, a virtual line 800 may be provided between the first line 210 and the second line 220, and the virtual line 800 is not connected to the first line 210 and the second line 220. The virtual line 800 may avoid the difference in reflectivity caused by the different densities between the first multiplexing circuit 410 and the second multiplexing circuit 420.

[0139] In this embodiment, when the ratio of the total length of the compensation line 700 and the second line 220 to the length of the first line 210 is too small or too large, the transmission and loading speeds between the first line 210 and the second line 220 differ greatly, resulting in inconsistent image quality, which in turn leads to a poor user experience. In this embodiment, the ratio of the total length of the compensation line 700 and the second line 220 to the length of the first line 210 is used as the fourth ratio M4, and the fourth ratio M4 is set to be greater than or equal to 0.8 and less than or equal to 1.2. When other conditions remain unchanged, within this range, the transmission and loading speeds between the first line 210 and the second line 220 are basically the same, and the image quality appears almost the same in visual experience, thereby improving the user experience.

[0140] In one embodiment, reference Figure 1 and Fig.14 As shown, the display panel further includes a plurality of light-emitting control lines 1100, a light-emitting control circuit 1200, a light-emitting control output line 320, a plurality of second-type power supply lines 900, and a second power supply line 520. The plurality of light-emitting control lines 1100 are located in the display area A and are electrically connected to the plurality of sub-pixels S, and the plurality of light-emitting control lines 1100 are configured to transmit light-emitting control signals to the plurality of sub-pixels S; the light-emitting control circuit 1200 is located in the non-display area B and is electrically connected to the plurality of light-emitting control lines 1100; the light-emitting control output line 320 is located in the non-display area B and is connected to the light-emitting control circuit 1200, and the light-emitting control output line 320 is configured to transmit light-emitting control signals to be detected during the display panel preparation stage; the plurality of second-type power supply lines 900 are located in the non-display area B , and a second type power supply line 900 is connected to one end of each of the at least two data transmission lines 112 away from the multiplexing circuit 100; the second power supply line 520 is located on the side of the light emitting control output line 320 away from the display area A; wherein the orthographic projection of the second type power supply line 900 on the base substrate 10 is the third projection area, and the orthographic projection of the light emitting control output line 320, the second power supply line 520 and the areas between the two on the base substrate 10 is the fourth projection area; the third projection area is located within the fourth projection area. It should be noted that, with reference to Figure 1 As shown, the first power line 510 and the second power line 520 are an integrated structure, and the signals of the first power line 510 and the second power line 520 are both negative power signal lines (ie, VSS signal lines).

[0141] refer to Fig.14As shown, the third projection area is the area from the side of the second type of power supply line 900 close to the display area A to the side of the second type of power supply line 900 away from the display area A, and the fourth projection area is the area from one end of the light-emitting control output line 320 close to the display area A to the second power line 520 away from the display area A.

[0142] Based on the above description, the third projection area overlaps with the fourth projection area, for example, the third projection area is located within the fourth projection area. Since the light-emitting control output line 320 and the second power line 520 are both stable signals, the second power line 520 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0143] refer to Fig.14 and Fig.15 As shown, the extension direction of the second type power supply line 900 coincides with the extension direction of some line segments in the light-emitting control output line 320, and in the direction perpendicular to the extension direction of the second type power supply line 900, the orthographic projection of the second type power supply line 900 on the base substrate 10 and the orthographic projection of some line segments in the light-emitting control output line 320 on the base substrate 10 at least partially overlap. It should be noted that the extension directions coincide, that is, the trajectories of the second type power supply line 900 and the light-emitting control output line 320 are substantially the same, and the two are substantially parallel.

[0144] Based on the above description, since the orthographic projection of the second-type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the light-emitting control output line 320 on the base substrate 10, when performing layout design, the second-type power supply line 900 can be arranged close to the light-emitting control output line 320, thereby reserving more space for other routing lines arranged on the second power supply line 520.

[0145] refer to Fig.17 As shown, the orthographic projection of the second type power supply line 900 on the base substrate 10 is located within the orthographic projection of the partial line segment of the light emitting control output line 320 on the base substrate 10. The above statement means that along the direction perpendicular to the extension direction of the second type power supply line 900, the ratio of the width of the second type power supply line 900 to the width of the partial line segment of the light emitting control output line 320 is less than or equal to 1.

[0146] Based on the above settings, the orthographic projection of the second type of power supply line 900 on the base substrate 10 is completely located within the orthographic projection of the light-emitting control output line 320. Since the light-emitting control output line 320 is a stable signal, the second type of power supply line 900 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0147] refer to Fig.17 As shown, along the direction perpendicular to the extension direction of the second type power supply line 900, the two opposite sides of the partial line segments in the light-emitting control output line 320 exceed the two opposite sides of the corresponding second type power supply line 900. In this way, the orthographic projection of the second type power supply line 900 on the base substrate 10 is completely located within the orthographic projection of the partial line segments in the light-emitting control output line 320 on the base substrate 10, which can prevent interference from the jump signal to the greatest extent.

[0148] refer to Fig.16 As shown, the orthographic projection of the second-type power supply line 900 on the base substrate 10 coincides with the orthographic projection of a portion of the line segments in the light-emitting control output line 320 on the base substrate 10 .

[0149] That is, the second type power supply line 900 is arranged above the light emitting control output line 320 along the thickness direction. Such arrangement can free up more areas of the base substrate 10 for wiring.

[0150] refer to Fig.18 As shown, the orthographic projection of the second type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the second power supply line 520 on the base substrate 10. Since the orthographic projection of the second type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the second power supply line 520 on the base substrate 10, during layout design, the second type power supply line 900 can be arranged close to the second power supply line 520, thereby reserving more space for other routing lines.

[0151] refer to Fig.19 As shown, the orthographic projection of the second type power supply line 900 on the base substrate 10 is located inside the orthographic projection of the second power supply line 520. That is, the second type power supply line 900 is arranged above the second power supply line 520 along the thickness direction, and such an arrangement can free up more areas of the base substrate for wiring.

[0152] refer to Figure 2-Figure 18 As shown, the multiplexing circuit 100 includes a first control unit 113 and a second control unit 114, the first control unit 113 and the second control unit 114 are respectively connected to one of the data lines 600, and the first control unit 113 and the second control unit 114 share one of the first data transmission lines 112a. It should be noted that the first control unit 113 and the second control unit 114 here can be semiconductor circuits. Under the above setting, one of the first data transmission lines 112a corresponds to two data lines 600, which can reduce the number of the first data transmission lines 112a to half of the number of the data lines 600.

[0153] Furthermore, the multiplexing circuit 100 further includes a third control unit 115, the first control unit 113, the second control unit 114, and the third control unit 115 are respectively connected to one data line 600, and the first control unit 113, the second control unit 114, and the third control unit 115 share one first data transmission line 112a. In this case, one first data transmission line 112a corresponds to three data lines 600, so that the number of first data transmission lines 112a can be reduced to one third of the number of data lines 600.

[0154] The above three data lines 600 can be respectively connected to at least three columns of sub-pixels in the display area A. For example, among the three data lines 600, the first data line 600 is connected to a column of red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels can be arranged alternately in the column direction, the second data line 600 is connected to a column of green sub-pixels, and the third data line 600 is connected to a column of red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels can be arranged alternately in the column direction.

[0155] It should be noted that the sub-pixels here can be white sub-pixels, red sub-pixels, blue sub-pixels, and green sub-pixels, and the multiplexing sub-unit 110 is connected to four data lines 600, and the four data lines 600 are connected to the red sub-pixels, blue sub-pixels, green sub-pixels, and white sub-pixels to control the red sub-pixels, blue sub-pixels, green sub-pixels, and white sub-pixels. In addition, the sub-pixels can also include any one or more of the red sub-pixels, blue sub-pixels, and green sub-pixels, and the multiplexing sub-unit 110 is connected to the data lines 600 that match them, so that one multiplexing sub-unit 110 controls one data line. The arrangement of this embodiment can be more convenient for corresponding connections, and more convenient for adjusting data and control.

[0156] In one embodiment, reference Fig.16 and Fig. 20As shown, the multiplexing circuit 100 at least includes a third multiplexing circuit 430 and a fourth multiplexing circuit 440, and the third multiplexing circuit 430 and the fourth multiplexing circuit 440 both include a plurality of the multiplexing subunits 110 of the same number; the plurality of the multiplexing subunits 110 in the third multiplexing circuit 430 are connected through the second type of power supply line 900, and the second type of power supply line 900 connected to the plurality of the multiplexing subunits 110 in the third multiplexing circuit 430 is used as a third line 910; the plurality of the multiplexing subunits 110 in the fourth multiplexing circuit 440 are connected through the second type of power supply line 900, and the second type of power supply line 900 connected to the plurality of the multiplexing subunits 110 in the fourth multiplexing circuit 430 is used as a fourth line 920. The length L3 of the third line is greater than the length L4 of the fourth line. Furthermore, the ratio of the third line resistance R3 to the fourth line resistance R4 is used as a fifth ratio M5, the ratio of the length L3 of the third line to the length L4 of the fourth line is used as a sixth ratio M6, and the ratio of the length L4 of the fourth line to the length L3 of the third line is used as a seventh ratio M7. The fifth ratio M5 is greater than the seventh ratio M7, and the fifth ratio M5 is less than the sixth ratio M6.

[0157] It should be noted that, when the third line 910 and the fourth line 920 are made of the same material and the cross-sectional area S of the third line 910 and the fourth line 920 are the same, the fifth ratio M5 should be equal to the sixth ratio M6. In this embodiment, the fifth ratio M5 is set to be greater than the seventh ratio M7, and the fifth ratio M5 is set to be less than the sixth ratio M6, which means that the value between the third line resistance R3 and the fourth line resistance R4 becomes closer. For example, the length L3 of the third line is set to 2, and the length L4 of the fourth line is set to 1, so the corresponding value of the sixth ratio M6 is 2. Under normal circumstances, the fifth ratio M5 is equal to the sixth ratio M6, so the value of the fifth ratio M5 is equal to 2, and the value of the seventh ratio M7 is equal to 1 / 2. Since the fifth ratio M5 is set to be less than the sixth ratio M6 in this embodiment, the value of the sixth ratio M6 should be less than 2 in this embodiment. There are two ways to reduce the value of the fifth ratio M5: the first is to increase the value of the fourth line resistor R4; the second is to reduce the value of the third line resistor R3. Both of the above methods can reduce the gap between the third line resistor R3 and the fourth line resistor R4. However, if the value of the fourth line resistor R4 is increased too much, or the value of the third line resistor R3 is reduced too little, the gap between the third line resistor R3 and the fourth line resistor R4 may be larger, for example: the value of the original third line resistor R3 is set to 2, and the value of the original fourth line resistor R4 is set to 1. If the value of the fourth line resistor R4 is increased to 5, or the value of the third line resistor R3 is reduced to 0.1, although the fifth ratio M5 is smaller than the sixth ratio M6, the gap between the third line resistor R3 and the fourth line resistor R4 becomes larger. Therefore, the fifth ratio M5 is set to be greater than the seventh ratio M7, and the value of the fourth line resistor R4 increased and the value of the third line resistor R3 reduced can only be within the range of the reduced ratio of the two. For example: the value of the original third line resistor R3 is set to 2, and the value of the original fourth line resistor R4 is set to 1. Increasing the value of the third line resistor R3 to 2, or reducing the value of the third line resistor R3 to 1, can reduce the difference between the third line resistor R3 and the fourth line resistor R4. Since the difference between the third line resistor R3 and the fourth line resistor R4 is reduced, the inconsistency in transmission and loading speed between the two lines caused by the difference between the length L3 of the third line and the length L4 of the fourth line can be compensated, thereby improving the uniformity of image quality.

[0158] The inventor has found through a large number of experiments that when the fifth ratio M5 is too small or too large, the transmission and loading speeds between the third line 910 and the fourth line 920 differ greatly, resulting in inconsistent image quality, which in turn leads to a poor user experience. In this embodiment, the fifth ratio M5 is set to be greater than or equal to 0.8 and less than or equal to 1.2. Within this range, the transmission and loading speeds between the third line 910 and the fourth line 920 are basically the same, and the image quality is almost the same in visual experience, thereby improving the user experience.

[0159] It should be noted that the formula of resistance is R=ρL / S, where R is resistance, S is cross-sectional area, L is length, and ρ is resistivity. Under the premise that the length L3 of the third line is greater than the length L4 of the fourth line, in order to make the value of the fifth ratio M5 greater than or equal to 0.8 and less than or equal to 1.2, on the one hand, the resistivity of the third line 910 can be set to be smaller than the resistivity of the fourth line 920. On the other hand, the cross-sectional area of ​​the third line 910 can be set to be larger than the cross-sectional area of ​​the fourth line 920. According to the above formula, it can be known that under the premise that other conditions remain unchanged, setting the resistivity of the third line 910 to be smaller than the resistivity of the fourth line 920 can increase the resistance of the third line 910, thereby making the value of the fifth ratio M5 closer to 1, and thus making the transmission and loading speeds between the third line 910 and the fourth line 920 close. Similarly, according to the above formula, under the premise that other conditions remain unchanged, setting the cross-sectional area of ​​the third line 910 to be larger than the cross-sectional area of ​​the fourth line 920 can reduce the resistance of the third line 910, thereby making the value of the fifth ratio M5 closer to 1, thereby making the transmission and loading speeds between the third line 910 and the fourth line 920 close.

[0160] In order to achieve the above goals, refer to Fig.17 As shown, the orthographic projection of the fourth line 920 on the base substrate 10 can be set to fall within the orthographic projection of the light emitting control output line 320 on the base substrate 10, referring to Fig. 20 As shown, the orthographic projection area of ​​the third line 910 on the base substrate 10 is set to be larger than the orthographic projection area of ​​a partial line segment of the light emitting control output line 320 on the base substrate 10 .

[0161] Through the above settings, when the third line 910 and the fourth line 920 have the same thickness, it can be known that the cross-sectional area of ​​the third line 910 is larger than the cross-sectional area of ​​the fourth line 920. According to the formula R=ρL / S, the resistance R4 of the fourth line is larger than the resistance of the third line 910, so that the value of the fifth ratio M5 is closer to 1, thereby making the transmission and loading speeds between the third line 910 and the fourth line 920 close.

[0162] refer to Figure 1 and Fig. 20As shown, the light control circuit 1200 includes a plurality of light control sub-circuits. Since the length L3 of the third line is greater than the length L4 of the fourth line, the light control sub-circuit can be arranged between two adjacent multiplexing sub-units 110 in the third multiplexing circuit 430. Such an arrangement can make full use of the space between the multiplexing sub-units 110, thereby making the non-display area B of the display panel more compact, thereby making the overall frame of the display panel smaller and providing more functions for the display panel.

[0163] In one embodiment, reference Fig.21 , Fig. 22 , Fig.23 as well as Fig.24 As shown, the fourth line 920 includes a third part 921 and a fourth part 922 and is connected to the third part 921 and the fourth part 922; the length of the third line 910 is greater than the length of the fourth line 920, and the compensation line 700 is arranged between the third part 921 and the fourth part 922. Based on this, the transmission and loading speed of the connection between the multiplexing subunits 110 of the third multiplexing circuit 430 is slow, and the transmission and loading speed of the connection between the multiplexing subunits 110 of the fourth multiplexing circuit 440 is fast. Since the compensation line 700 has a certain resistance, the compensation line 700 can be arranged to slow down the transmission and loading speed of the connection between the multiplexing subunits 110 of the fourth multiplexing circuit 440, so that the transmission and loading speed of the connection between the multiplexing subunits 110 of the fourth multiplexing circuit 440 is close. Such a setting can change the transmission and loading speed of the connection between the multiplexing subunits 110 while basically not changing the original design of other parts.

[0164] In addition, reference Fig.23 As shown, a virtual line 800 may be provided between the third line 910 and the fourth line 920, and the virtual line 800 is not connected to the third line 910 and the fourth line 920. The virtual line 800 may avoid the difference in reflectivity caused by the different densities between the third multiplexing circuit 430 and the fourth multiplexing circuit 440.

[0165] In this embodiment, when the ratio of the total length of the compensation line 700 and the fourth line 920 to the length of the third line 910 is too small or too large, the transmission and loading speeds between the third line 910 and the fourth line 920 differ greatly, resulting in inconsistent image quality, which in turn leads to a poor user experience. In this embodiment, the ratio of the total length of the compensation line 700 and the fourth line 920 to the length of the third line 910 is used as the eighth ratio M8, and the eighth ratio M8 is set to be greater than or equal to 0.8, and less than or equal to 1.2. When other conditions remain unchanged, within this range, the transmission and loading speeds between the third line 910 and the fourth line 920 are basically consistent, and the image quality appears almost consistent in visual experience, thereby improving the user experience.

[0166] Fig.25 FIG. 1 is a partial cross-sectional schematic diagram of a display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 1 In this example, multiple transistors in the sub-pixel circuit are of the same type. For example, multiple transistors in the pixel circuit can all be low-temperature polysilicon thin film transistors or oxide thin film transistors.

[0167] In some examples, such as Fig.25 As shown, in the direction perpendicular to the display panel, the display area of ​​the display panel may include: a base substrate 10, and a circuit structure layer 12, a light emitting structure layer 13, a packaging structure layer 14 and a touch structure layer 15 sequentially arranged on the base substrate 10. Among them, the display structure layer may at least include: a circuit structure layer 12 and a light emitting structure layer 13. The circuit structure layer 12 may at least include: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may at least include: a light emitting element of a plurality of sub-pixels.

[0168] In some examples, Fig.25In the figure, a thin film transistor 21 and a capacitor 22 included in a sub-pixel are used as an example for illustration. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer 25, a first gate metal layer 26, a second gate metal layer 27, a first source-drain metal layer 29, and a second source-drain metal layer 30 arranged on the base substrate 10. A first gate insulating layer 101 may be arranged between the semiconductor layer 25 and the first gate metal layer 26, a second gate insulating layer 102 may be arranged between the first gate metal layer 26 and the second gate metal layer 27, an interlayer insulating layer 103 may be arranged between the second gate metal layer 27 and the first source-drain metal layer 29, a passivation layer 104 and a first planar layer 105 may be arranged between the first source-drain metal layer 29 and the second source-drain metal layer 30, and a second planar layer 106 may be arranged on the side of the second source-drain metal layer 30 away from the base substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 can be inorganic insulating layers, and the first flat layer 105 and the second flat layer 106 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can also be provided on the side of the semiconductor layer 25 close to the substrate, and the buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel, and can also increase the adhesion of the film layer in the display panel on the substrate. In other examples, the passivation layer can be omitted between the first source and drain metal layer 29 and the second source and drain metal layer 30, and only the first flat layer is provided. In other examples, the second source and drain metal layer 30 and the second flat layer can be omitted.

[0169] In some examples, such as Fig.25As shown, the semiconductor layer 25 in the display area may include at least: an active layer 210a of the thin film transistor 21. The active layer 210a of the thin film transistor 21 may include: a first area 2101, a second area 2102, and a channel area 2100 located between the first area 2101 and the second area 2102. The first gate metal layer 26 may include at least: a gate 213 of the thin film transistor 21, and a first electrode 221a of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 10 may cover the orthographic projection of the channel area 2100 of the active layer 210a on the substrate 10. The second gate metal layer 27 may include at least: a second electrode 222a of the capacitor 22. The orthographic projections of the second electrode 222a and the first electrode 221a of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may overlap. The first source-drain metal layer 29 may include at least: a first electrode 211 and a second electrode 212 of the thin film transistor 21. The interlayer insulating layer 103 may be provided with a plurality of vias 28 (for example, including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the active layer 210a; the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101 in the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the active layer 210a. The first electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210a through the first pixel via, and the second electrode 212 may be electrically connected to the second region 2102 of the active layer 210a through the second pixel via. The second source-drain metal layer 30 may include at least: an anode connection electrode 23. The anode connection electrode 23 can be connected to the second electrode 212 of the thin film transistor 21 through the via hole opened in the passivation layer 104 and the first flat layer 105. In some examples, the gate line 1010 of the display area can be located in the first gate metal layer 26, and the data line and the high potential power line of the display area can be located in the second source and drain metal layer 30. However, this embodiment is not limited to this. In other examples, the second source and drain metal layer 30 can be omitted, and the data line and the high potential power line of the display area can be located in the first source and drain metal layer 29.

[0170] In some examples, such as Fig.25As shown, the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the second flat layer 106, and electrically connected to the anode connection electrode 23 through a pixel via hole provided in the second flat layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second flat layer 106, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light emitting layer 132 may be disposed in a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of a corresponding color under the drive of the first electrode 131 and the second electrode 133.

[0171] In some examples, the organic light-emitting layer 132 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more of the following film layers: a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole blocking layer (HBL, Hole Block Layer), an electron blocking layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0172] In some examples, the light-emitting layers of light-emitting elements emitting different colors of light may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, Fine Metal Mask) or an open mask (Open Mask), or by inkjet technology.

[0173] In some examples, such as Fig.25 As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, the second encapsulation layer 142 may be made of organic materials, and the second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0174] refer to Figure 26-Figure 31 As shown, Figure 27-Figure 31 is a diagram of the manufacturing process of the display panel, wherein Fig. 27 for Fig.26 A schematic plan view of a semiconductor layer 25 after forming a multiplexing circuit. Fig.28 for Fig.26 The first gate metal layer 26 may include at least: a gate electrode 213 of the thin film transistor 21 located in the sub-pixel S in the display area, and a first electrode plate 221a of the capacitor 22. Fig.29 for Fig.26 The second gate metal layer 27 of the multiplexing circuit 100 is formed in FIG. 1 . The second gate metal layer 27 may include at least: a second electrode plate 222 a of the capacitor 22 located in the sub-pixel S in the display area. Fig.30 for Fig.26 FIG. 1 is a plan view showing that a plurality of via holes 28 may be provided in the interlayer insulating layer 103 in the display area. Fig.31 for Fig.26 The schematic plan view of the multiplexing circuit 100 after the first source-drain metal layer 29 is formed, the first source-drain metal layer 29 may at least include: a first electrode 211 and a second electrode 212 of the thin film transistor 21 located in the sub-pixel S in the display area.

[0175] In some examples, such as Figure 26-Figure 31 As shown, the active layers of the nine multiplexing transistors of the multiplexing circuit 100 are located in the semiconductor layer 25. The active layer of each multiplexing transistor may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102, the channel region 2100 being a region blocked by the transistor gate, for example, the first active layer M10 of the first multiplexing transistor M1 includes the first region 2101, the second region 2102, and the channel region 2100 located between the first region 2101 and the second region 2102, the channel region 2100 being a region where the orthographic projection of the gate M13 of the first multiplexing transistor M1 on the substrate overlaps with the orthographic projection of the first active layer M10 on the substrate. The third active layer M30 of the third multiplexing transistor M3, the second active layer M20 of the second multiplexing transistor M2, the first active layer M10 of the first multiplexing transistor M1, the fourth active layer M40 of the fourth multiplexing transistor M4, the fifth active layer M50 of the fifth multiplexing transistor M5, the sixth active layer M60 of the sixth multiplexing transistor M6, the seventh active layer M70 of the seventh multiplexing transistor M7, the eighth active layer M80 of the eighth multiplexing transistor M8, and the ninth active layer M90 of the ninth multiplexing transistor M9 can be arranged in sequence along the first direction X. Among them, the second active layer M20 and the third active layer M30 can be an integrated structure connected to each other, the fifth active layer M50 and the sixth active layer M60 can be an integrated structure connected to each other, and the eighth active layer M80 and the ninth active layer M90 can be an integrated structure connected to each other, so that the occupied space of the multiplexing circuit 100 can be reduced. However, this embodiment is not limited to this. For example, the active layers of the nine multiplexing transistors can be independently arranged.

[0176] In some examples, such as Figure 25-Figure 30As shown, the gates of the nine multiplexing transistors of the multiplexing circuit 100 can be located at the first gate metal layer 26. The orthographic projection of the gate of each multiplexing transistor on the substrate can cover the orthographic projection of the channel region 2100 of the corresponding active layer on the substrate. The gate M13 of the first multiplexing transistor M1, the gate M23 of the second multiplexing transistor M2, the gate M33 of the third multiplexing transistor M3, the gate M43 of the fourth multiplexing transistor M4, the gate M53 of the fifth multiplexing transistor M5, the gate M63 of the sixth multiplexing transistor M6, the gate M73 of the seventh multiplexing transistor M7, the gate M83 of the eighth multiplexing transistor M8, and the gate M93 of the ninth multiplexing transistor M9 can all extend along the second direction Y and be arranged in sequence along the first direction X.

[0177] In some examples, such as Figure 26-Figure 31 As shown, the first and second electrodes of the nine multiplexing transistors of the multiplexing circuit 100 can be located at the first source-drain metal layer 29. The first electrode M21 of the second multiplexing transistor M2 can also serve as the first electrode M31 of the third multiplexing transistor M3. The first electrode M21 can be electrically connected to the data transmission line 112. The second electrode M22 of the second multiplexing transistor M2 and the second electrode M32 of the third multiplexing transistor M3 are respectively connected to different data lines 600. The first electrode M11 of the first multiplexing transistor M1 can be connected to the first region 2101 of the first active layer M10 of the first multiplexing transistor M1 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and the second electrode M12 of the first multiplexing transistor M1 can be connected to the second region 2102 of the first active layer M10 of the first multiplexing transistor M1 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101. The first electrode M11 of the first multiplexing transistor M1 can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through a via hole opened in the interlayer insulating layer 103. The second electrode M12 of the first multiplexing transistor M1 can also be electrically connected to the data line 600 located in the first gate metal layer 26 through a via hole opened in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0178] In some examples, the second electrode M12 of the first multiplexing transistor M1 can be connected to the second region 2102 of the first active layer M10 of the first multiplexing transistor M1 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through the via holes opened in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M22 of the second multiplexing transistor M2 can be connected to the second region 2102 of the second active layer M20 of the second multiplexing transistor M2 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through the via holes opened in the interlayer insulating layer 103. The second electrode M32 of the third multiplexing transistor M3 can be connected to the second region 2102 of the third active layer M30 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through vias opened in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0179] In some examples, the first electrode M51 of the fifth multiplexing transistor M5 can also serve as the first electrode M61 of the sixth multiplexing transistor M6. The first electrode M41 of the fourth multiplexing transistor M4 can be connected to the first region 2101 of the fourth active layer M40 of the fourth multiplexing transistor M4 through a plurality of vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through a via opened in the interlayer insulating layer 103.

[0180] In some examples, the second electrode M42 of the fourth multiplexing transistor M4 can be connected to the second region 2102 of the fourth active layer M40 of the fourth multiplexing transistor M4 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through the via hole opened in the interlayer insulating layer 103. The second electrode M52 of the fifth multiplexing transistor M5 can be connected to the second region 2102 of the fifth active layer M50 of the fifth multiplexing transistor M5 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through the via hole opened in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M62 of the sixth multiplexing transistor M6 can be connected to the second region 2102 of the sixth active layer M60 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through the vias opened in the interlayer insulating layer 103.

[0181] In some examples, the first electrode M81 of the eighth multiplexing transistor M8 can also serve as the first electrode of the ninth multiplexing transistor M9. The first electrode M71 of the seventh multiplexing transistor M7 can be connected to the first region 2101 of the seventh active layer M70 of the seventh multiplexing transistor M7 through a plurality of vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101. It can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through the vias opened in the interlayer insulating layer 103.

[0182] In some examples, the second electrode M72 of the seventh multiplexing transistor M7 can be connected to the second region 2102 of the first active layer M70 of the seventh multiplexing transistor M7 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through the via holes opened in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M82 of the eighth multiplexing transistor M8 can be connected to the second region 2102 of the eighth active layer M80 of the eighth multiplexing transistor M8 through a plurality of via holes 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through the via holes opened in the interlayer insulating layer 103. The second electrode M92 of the ninth multiplexing transistor M9 can be connected to the second region 2102 of the ninth active layer M90 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through vias opened in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0183] In some examples, such as Figure 25-Figure 30 As shown, the plurality of data lines 600 may be alternately disposed in the first gate metal layer 26 and the second gate metal layer 27. The plurality of data transmission lines 112 may be alternately disposed in the first gate metal layer 26 and the second gate metal layer 27. This embodiment is not limited thereto.

[0184] In some examples, such as Figure 26-Figure 31 As shown, the gate M13 of the first multiplexing transistor M1 can be electrically connected to the first multiplexing control line 1111 through the via hole opened in the interlayer insulating layer 103 and the second gate insulating layer 102. The gate M23 of the second multiplexing transistor M2 can be electrically connected to the second multiplexing control line 1112. The gate M33 of the third multiplexing transistor M3 can be electrically connected to the third multiplexing control line 1113. The gate M43 of the fourth multiplexing transistor M4 can be electrically connected to the fourth multiplexing control line 1114. The gate M53 of the fifth multiplexing transistor M5 can be electrically connected to the fifth multiplexing control line 1115. The gate M63 of the sixth multiplexing transistor M6 can be electrically connected to the sixth multiplexing control line 1116. The gate M73 of the seventh multiplexing transistor M7 can be electrically connected to the seventh multiplexing control line 1117. The gate M83 of the eighth multiplexing transistor M8 can be electrically connected to the eighth multiplexing control line 1118. The gate M93 of the ninth multiplexing transistor M9 may be electrically connected to a ninth multiplexing control line 1119 .

[0185] In some examples, the ninth multiplexing control line 1119, the eighth multiplexing control line 1118, the seventh multiplexing control line 1117, the sixth multiplexing control line 1116, the fifth multiplexing control line 1115, the fourth multiplexing control line 1114, the third multiplexing control line 1113, the second multiplexing control line 1112, and the first multiplexing control line 1111 may be located at the first source-drain metal layer 29. A third low-voltage lead line 577, a second scan clock second lead line 834, a first scan clock second lead line 824, and a third high-voltage lead line 587 may be disposed on one side of a group of multiplexing control lines 111 close to the multiplexing circuit 100; the third low-voltage lead line 577, the second scan clock second lead line 834, the first scan clock second lead line 824, and the third high-voltage lead line 587 may be disposed in sequence in a direction away from the multiplexing circuit 100. A gate driving output line 310 may be disposed on a side of the group of multiplexing control lines 111 away from the multiplexing circuit 100 .

[0186] In some examples, the third low voltage lead 577 can be electrically connected to the first low voltage lead, and the third low voltage lead 577 can provide a first voltage signal to the gate drive circuit in the left frame area. The third high voltage lead 587 can be electrically connected to the first high voltage lead, and the third high voltage lead 587 can provide a second voltage signal to the gate drive circuit in the left frame area. The first scan clock second lead 824 can be electrically connected to the first scan clock lead, and the second scan clock second lead 834 can be electrically connected to the second scan clock lead. The first scan clock second lead 824 and the second scan clock second lead 834 can provide a scan clock signal to the gate drive circuit. The gate drive output line 310 can be electrically connected to the first scan output lead.

[0187] The structure of the multiplexing circuit 100 disposed in the right area of ​​the first power line 510 is similar to the structure of the multiplexing circuit 100 disposed in the left area, and thus will not be described in detail herein.

[0188] The present application also provides a display device, which includes the display panel described in the above embodiment. Since the display device includes the display panel described in the above embodiment, the display device also has the functions and advantages of the display panel. The display device can be an electronic device with a display function, such as a mobile phone, a computer, or a tablet computer.

[0189] In the present application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0190] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, those of ordinary skill in the art can use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the application. This should not be interpreted as a feature of an application that does not require protection being necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of the embodiments of a specific application. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently used as a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the full scope of the equivalent forms of the attached claims and these claims.

[0191] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the present application, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0192] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0193] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.

[0194] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure of the present application. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0195] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display panel, characterized in that: include: A substrate, comprising a display area and a non-display area surrounding the display area; A plurality of sub-pixels are located in the display area; a plurality of data lines, located in the display area and extending to the non-display area, the plurality of data lines being electrically connected to the plurality of sub-pixels; A plurality of data transmission lines are located in the non-display area; A plurality of multiplexing circuits, located in the non-display area, each of the multiplexing circuits comprising a plurality of multiplexing sub-units, one of the plurality of data transmission lines being electrically connected to at least two of the data lines via one of the plurality of multiplexing sub-units, the one multiplexing sub-unit being configured to transmit a data signal transmitted by one of the data transmission lines to the at least two data lines in different time periods in time-sharing manner; a plurality of gate lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to transmit gate signals to the plurality of sub-pixels; A gate driving circuit, located in the non-display area and electrically connected to the plurality of gate lines; a gate drive output line, located in the non-display area and connected to the gate drive circuit, the gate drive output line being configured to transmit a gate signal to be detected during a display panel preparation stage; a plurality of first-type power supply lines, located in the non-display area, and one of the first-type power supply lines is connected to an end of each of the at least two data transmission lines away from the multiplexing circuit; A first power line, located at a side of the gate drive output line away from the display area; The orthographic projection of the first type of power supply line on the base substrate is a first projection area, and the orthographic projection of the gate drive output line and the first power supply line on the base substrate is a second projection area; The first projection area is located within the second projection area.

2. The display panel according to claim 1, wherein: An extension direction of the first type of power supply line coincides with an extension direction of some line segments in the gate drive output line, and in a direction perpendicular to the extension direction of the first type of power supply line, an orthographic projection of the first type of power supply line on the substrate and an orthographic projection of some line segments in the gate drive output line on the substrate at least partially overlap.

3. The display panel according to claim 2, wherein: The orthographic projection of the first-type power supply line on the base substrate is located within the orthographic projection of a portion of the gate driving output line.

4. The display panel according to claim 2, wherein: Along a direction perpendicular to an extending direction of the first-type power supply line, a ratio of a width of the first-type power supply line to a width of a portion of line segments in the gate drive output line is less than or equal to 1.

5. The display panel according to claim 2, wherein: Along a direction perpendicular to the extending direction of the first-type power supply line, two opposite side boundaries of some line segments in the gate drive output line exceed two opposite side boundaries of the corresponding first-type power supply line.

6. The display panel according to claim 2, wherein: The orthographic projection of the first-type power supply line on the base substrate coincides with the orthographic projection of a portion of line segments in the gate drive output line on the base substrate.

7. The display panel according to claim 1, wherein: The orthographic projection of the first-type power supply line on the base substrate at least partially overlaps with the orthographic projection of some line segments of the first power supply line on the base substrate.

8. The display panel according to claim 7, wherein: The orthographic projection of the first-type power supply line on the base substrate is located within the orthographic projection of the base substrate.

9. The display panel according to claim 1, wherein: The multiple data transmission lines include multiple first data transmission lines and multiple second data transmission lines, the multiple first data transmission lines and the multiple second data transmission lines are respectively located on both sides of the multiple first-type power supply lines, and each second data transmission line is connected to at least two first data transmission lines through one of the first-type power supply lines.

10. The display panel according to claim 1, wherein: The multiple multiplexing circuits include at least a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a plurality of the multiplexing subunits having the same number; The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line; The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line; The length of the first line is greater than the length of the second line; and a ratio of a resistance of the first line to a resistance of the second line is used as a first ratio, a ratio of a length of the first line to a length of the second line is used as a second ratio, and a ratio of a length of the second line to a length of the first line is used as a third ratio; The first ratio is smaller than the second ratio, and the first ratio is larger than the third ratio.

11. The display panel according to claim 10, wherein: The resistivity of the first wire is smaller than the resistivity of the second wire, and / or the cross-sectional area of ​​the first wire is smaller than the cross-sectional area of ​​the second wire.

12. The display panel according to claim 10, wherein: The orthographic projection of the second line on the base substrate falls within the orthographic projection of the gate drive output line on the base substrate, and the orthographic projection area of ​​the first line on the base substrate is larger than the orthographic projection area of ​​the gate drive output line on the base substrate.

13. The display panel according to claim 10, wherein: The first ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

14. The display panel according to claim 10, wherein: The gate driving circuit includes a plurality of gate driving sub-circuits, and at least one gate driving sub-circuit of the plurality of gate driving sub-circuits is arranged between two adjacent multiplexing sub-units in the first multiplexing circuit.

15. The display panel according to claim 1, wherein: The display panel further includes a compensation line, the multiple multiplexing circuits include a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a plurality of the multiplexing subunits having the same number; The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line; The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line; The second line includes a first portion and a second portion; The length of the first line is greater than that of the second line, and the compensation line is disposed between the first portion and the second portion and connected to the first portion and the second portion.

16. The display panel according to claim 15, wherein: The ratio of the sum of the length of the compensation line and the length of the second line to the length of the first line is taken as a fourth ratio, and the fourth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

17. The display panel according to claim 1, wherein: Also included are a plurality of light emitting control lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of light emitting control lines being configured to transmit light emitting control signals to the plurality of sub-pixels; A light emitting control circuit, located in the non-display area and electrically connected to the plurality of light emitting control lines; a light emitting control output line, located in the non-display area and connected to the light emitting control circuit, wherein the light emitting control output line is configured to transmit a light emitting control signal to be detected during a display panel preparation stage; a plurality of second-type power supply lines, located in the non-display area, and one second-type power supply line is connected to an end of each of the at least two data transmission lines away from the multiplexing circuit; A second power line, located at a side of the light emitting control output line away from the display area; The orthographic projection of the second type power supply line on the base substrate is a third projection area, and the orthographic projection of the light emitting control output line and the second power supply line on the base substrate is a fourth projection area; The third projection area is located within the fourth projection area.

18. The display panel according to claim 17, wherein: The extension direction of the second type of power supply line coincides with the extension direction of some line segments in the light-emitting control output line, and in the direction perpendicular to the extension direction of the second type of power supply line, the orthographic projection of the second type of power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments in the light-emitting control output line on the substrate.

19. The display panel according to claim 17, wherein: The orthographic projection of the second-type power supply line on the base substrate is located within the orthographic projection of a portion of the light-emitting control output line.

20. The display panel according to claim 17, wherein: Along a direction perpendicular to the extending direction of the second-type power supply line, a ratio of a width of the second-type power supply line to a width of a portion of line segments in the light-emitting control output line is less than or equal to 1.

21. The display panel according to claim 17, wherein: Along a direction perpendicular to the extending direction of the second-type power supply line, two opposite side boundaries of some line segments in the light-emitting control output line exceed two opposite side boundaries of the corresponding second-type power supply line.

22. The display panel according to claim 17, wherein: The orthographic projection of the second-type power supply line on the base substrate coincides with the orthographic projection of a portion of line segments in the light-emitting control output line on the base substrate.

23. The display panel according to claim 17, wherein: The orthographic projection of the second-type power supply line on the base substrate at least partially overlaps with the orthographic projection of some line segments of the second power supply line on the base substrate.

24. The display panel according to claim 23, wherein: The orthographic projection of the second-type power supply line on the base substrate is located within the orthographic projection of the base substrate.

25. The display panel according to claim 1, wherein: Each of the multiplexing circuits includes a first control unit and a second control unit. The first control unit and the second control unit are respectively connected to one of the data lines, and the first control unit and the second control unit share one of the data transmission lines.

26. The display panel according to claim 25, characterized in that: The multiplexing circuit further includes a third control unit. The first control unit, the second control unit and the third control unit are respectively connected to one of the data lines. The first control unit, the second control unit and the third control unit share one of the data transmission lines.

27. The display panel according to claim 17, wherein: The multiple multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a plurality of the multiplexing subunits having the same number; The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line connected to the plurality of multiplexing subunits in the third multiplexing circuit is used as a third line; The plurality of multiplexing subunits in the fourth multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line in the fourth multiplexing circuit is used as a fourth line; The third line length is greater than the fourth line length; and a ratio of the third line resistance to the fourth line resistance is used as a fifth ratio, a ratio of the third line length to the fourth line length is used as a sixth ratio, and a ratio of the fourth line length to the third line length is used as a seventh ratio; The fifth ratio is greater than the seventh ratio, and the fifth ratio is less than the sixth ratio.

28. The display panel according to claim 27, wherein: The resistivity of the third line is smaller than the resistivity of the fourth line, and / or the cross-sectional area of ​​the third line is smaller than the cross-sectional area of ​​the fourth line.

29. The display panel according to claim 27, wherein: The orthographic projection of the fourth line on the base substrate falls within the orthographic projection of the light-emitting control output line on the base substrate, and the orthographic projection area of ​​the third line on the base substrate is larger than the orthographic projection area of ​​the light-emitting control output line on the base substrate.

30. The display panel according to claim 27, wherein: The fifth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

31. The display panel according to claim 17, wherein: The display panel further includes a compensation line, the multiple multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a plurality of the multiplexing subunits of the same number; The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line connected to the plurality of multiplexing subunits in the third multiplexing circuit is used as a third line; The plurality of multiplexing subunits of the fourth multiplexing circuit are connected via the second type of power supply line, and the second type of power supply line connected to the plurality of multiplexing subunits in the fourth multiplexing circuit is used as a fourth line; The fourth line includes the third part and the fourth part; The length of the third line is greater than that of the fourth line, and the compensation line is disposed between the third portion and the fourth portion and connected to the third portion and the fourth portion.

32. The display panel according to claim 31, wherein: The ratio of the sum of the length of the compensation line and the length of the fourth line to the length of the third line is taken as an eighth ratio, and the eighth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

33. A display device, characterized in that: The display device comprises a display panel as described in any one of claims 1-32.

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