Packaging structure

Abstract

Some embodiments of the present application provide a package structure comprising: a wire structure; the first electronic element is embedded in the lead structure; and a thermal through hole passing through the lead structure and contacting the first electronic component. The packaging structure provided by the utility model has good heat dissipation performance, and the heat through holes can be used for enhancing the high heat conduction performance in the packaging structure.

Description

Technical Field

[0001] An embodiment of the present application relates to a packaging structure. Background Art

[0002] In a 3D stacked structure, such as Figure 1 As shown, the top electronic component 16 of the stacked structure 10 is stacked on the bottom electronic component 12 in a face-to-face bonding manner (such as high temperature bonding) and sealed in a molding compound 15. In some embodiments, the top electronic component 16 is a functional chip and the bottom electronic component 12 is a VRM (voltage regulation module) / IVR (integrated voltage regulator). Figure 1 In the stacked structure 10 shown, the top electronic component 16 is bonded to the bottom electronic component 12 via the middle layer redistribution structure 13B, and the bottom electronic component 12 is bonded to the substrate 11 via the bottom redistribution structure (RDL) 13A. In a further embodiment, a thermally conductive column 14 (formed of a thermally conductive material) is disposed around the bottom electronic component 12. In addition, as shown in FIG. Figure 1 As shown, a heat sink 17 is disposed above and around the top electronic component 16 and the bottom electronic component 12 for heat dissipation. External connectors 18 are disposed on the side of the substrate 11 opposite to the heat sink 17 for external connection.

[0003] It can be seen that in the existing stacked structure 10, the bottom electronic component 12 is closer to the substrate 11. In order to reduce the heat generated by the bottom electronic component 12 affecting the metal circuit of the substrate 11 and causing the thermal resistance to increase, a heat conducting column 14 is currently provided to conduct the heat of the bottom electronic component 12 upward to the heat sink 17. However, Figure 1A As shown, this will result in a longer heat conduction path (i.e., the heat conduction path t long The following order is: bottom redistribution structure (RDL) 13A>heat-conducting pillar 14>middle layer redistribution structure 13B>upper molding compound 15), which results in poor heat transfer and affects the thermal conductivity efficiency.

[0004] In summary, in the case where the bottom electronic component 12 of the prior art is a VRM / IVR, although the heat sink 17 is also used to pass through the thick stacked structure 10 of the thick chip / wafer (top electronic component 16 and bottom electronic component 12), the heat diffusion is limited because the face-to-face functional bonding (one side (e.g., the back side) faces the outside) structure of the top electronic component 16 and the bottom electronic component 12 is prone to heat accumulation and higher temperature. Figure 1 In the stack structure 10 shown, poor electrical performance leads to higher resistance (such as longer thermal paths t longand thicker package thickness (e.g., higher thermal conductive housing 14). In addition, the use of thermal conductive housing 14 increases the cost required for the multi-layer redistribution structure 13A / 13B because of the longer tracks for the higher thermal conductive housing 14 on the redistribution structure 13A / 13B, which increases the cost. Therefore, a new package structure is urgently needed to solve the above problems. Utility Model Content

[0005] The packaging structure of the present application can directly connect the bottom electronic components by forming a vertical path to solve the problem that the bottom electronic components in the stacked structure above conduct heat upward to the heat sink through the heat conduction column. long , that is: bottom redistribution structure (RDL) 13A> thermal conductive pillar 14> middle layer redistribution structure 13B> upper molding compound 15) which affects the thermal conductivity efficiency.

[0006] Some embodiments of the present application provide a packaging structure, including: a wire structure; a first electronic component buried in the wire structure; and a thermal via passing through the wire structure and contacting the first electronic component.

[0007] In some embodiments, the packaging structure further includes: a second electronic component disposed on the conductive line structure, wherein the second electronic component overlaps with the thermal via in a horizontal direction.

[0008] In some embodiments, the conductive line structure includes a recess, and the second electronic component is disposed within the recess.

[0009] In some embodiments, the packaging structure further includes: a first heat conducting member, disposed below and around the first electronic component and in contact with the thermal via.

[0010] In some embodiments, the first heat conductor extends in a direction perpendicular to the thermal via.

[0011] In some embodiments, the packaging structure further includes: a second heat conducting member exposed outside the packaging structure, wherein the second heat conducting member is connected to the first heat conducting member through the thermal via.

[0012] In some embodiments, the first electronic component has an active surface facing the conductive line structure.

[0013] In some embodiments, the first electronic component further includes a lower surface opposite to the active surface and a side surface connecting the active surface and the lower surface, wherein the thermal via contacts the active surface and the side surface of the first electronic component.

[0014] In some embodiments, the first electronic component has a lower surface away from the wire structure, wherein the first heat conductor contacts the lower surface of the first electronic component.

[0015] In some embodiments, the thermal via has a tapered shape in a direction toward the first electronic component.

[0016] In some embodiments, the second heat conducting member is a continuously extending heat conducting member.

[0017] In some embodiments, the first heat conducting member includes a plurality of discretely distributed heat conducting sub-members.

[0018] In some embodiments, the plurality of heat conducting sub-elements are located at different levels.

[0019] In some embodiments, the packaging structure further includes: a molding compound, sealing the second electronic component and the thermal via, wherein a top surface of the molding compound is flush with a top surface of the second electronic component and the thermal via, and the top surfaces of the molding compound, the second electronic component, and the thermal via are surfaces away from the wire structure.

[0020] In some embodiments, the second heat conductor extends in the same direction as the first heat conductor.

[0021] In some embodiments, the thermal vias are made of graphene.

[0022] In some embodiments, the first heat conductor and the second heat conductor are both made of graphene.

[0023] Other embodiments of the present application also provide a packaging structure, characterized in that it includes: a wire structure; a first electronic component embedded in the wire structure; a thermal conductive structure extending through the wire structure and arranged around the first electronic component, wherein the thermal conductive structure is in contact with both the upper surface and the lower surface of the first electronic component, and the upper surface is opposite to the lower surface.

[0024] In some embodiments, the thermally conductive structure includes a thermal via extending through the conductive line structure and a first thermal conductor and a second thermal conductor in contact with the thermal via.

[0025] In some embodiments, the first heat conductor is disposed below and around the first electronic component, wherein the thermal via contacts the upper surface of the first electronic component, and the first heat conductor contacts the lower surface of the first electronic component.

[0026] The packaging structure provided in the present application has good heat dissipation performance, and the thermal vias made of graphene can be used to enhance the high thermal conductivity in the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0028] Figure 1 and Figure 1A The stacking structure in the prior art is shown.

[0029] Figure 2 and Figure 2A A packaging structure according to some embodiments of the present application is shown.

[0030] Figures 3 to 28 The diagram shows a process for forming a package structure according to some embodiments of the present application.

[0031] Fig.29A and Fig.29B The vector is shown. DETAILED DESCRIPTION

[0032] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. In addition, when "approximately", "about", "substantially", etc. are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0033] The present application provides a packaging structure 100, see Figure 2 The package structure 100 includes: a wire structure 101; a first electronic component 102 embedded in the wire structure 101; and a thermal via 103, the thermal via 103 passes through the wire structure 101 and contacts the first electronic component 102. In addition, see further Figure 2 The packaging structure 100 further includes: a second electronic component 104, which is arranged on the conductor structure 101, wherein Figure 2It can be seen from the cross-sectional view shown that the second electronic component 104 overlaps with the thermal via 103 in the horizontal direction L, that is, the projections in the horizontal direction L overlap. In addition, the conductor structure 101 includes a recess R, and the second electronic component 104 is arranged in the recess R, that is, the bottom of the conductor structure 101 is embedded in the second electronic component 104. In some embodiments, the conductor structure 101 can be a redistribution structure (RDL) such as a structure. In some embodiments, the first electronic component 102 can include but is not limited to an electronic integrated circuit (EIC), and the second electronic component 104 can include but is not limited to an integrated voltage regulator (IVR) chip, a VRM (voltage regulation module) chip, etc. In a further embodiment, there is no substrate in the conductor structure 101. In some specific embodiments, the conductor structure 101 includes a dielectric layer 101t and a metal layer 101l embedded in the dielectric layer 101t and a seed layer 101ls located below the corresponding metal layer 101l. In some embodiments, the dielectric layer 101t may include, but is not limited to, polyimide, PA (gallium nitride), etc., and the metal layer 101l and the seed layer 101ls may include, but is not limited to, a metal such as copper, etc.

[0034] See also Figure 2 , the package structure 100 further includes a first heat conducting member 105. In some embodiments, the first heat conducting member 105 includes a plurality of discretely distributed sub-heat conducting members 1051, 1052, 1053, ..., and the plurality of sub-heat conducting members 1051, 1052, 1053, ... are located at different horizontal planes L1, L2. . Further, the first heat conducting member 105 is disposed below and around the first electronic component 102, and the first heat conducting member 102 is in contact with the thermal via 103, such as Figure 2A In a further embodiment, the first heat conductor 105 extends in a direction perpendicular to the thermal via 103. Specifically, the thermal via 103 extends in a vertical direction D, while the first heat conductor 105 extends in a horizontal direction L. Figure 2 As shown, the package structure 100 further includes a second heat conducting member 106 exposed to the outside of the package structure 100, and Figure 2 As can be seen in FIG. 1 , the second heat conductor 106 is connected to the first heat conductor 105 through the thermal via 103. In a further embodiment, the second heat conductor 106 is a continuously extending heat conductor. In some embodiments, the second heat conductor 106 extends in the same direction as the first heat conductor 105, that is, both extend in the horizontal direction L. In some embodiments, the thermal via 103, the first heat conductor 105, and the second heat conductor 106 include graphene or are made of graphene.

[0035] like Figure 2As shown, the first electronic component 102 has an active surface 102a facing the conductor structure 101, and the first electronic component 102 also includes a lower surface 102d opposite to the active surface 102a and a side surface 102s connecting the active surface 102a and the lower surface 102d. Figure 2A As can be seen in FIG, the thermal via 103 contacts the active surface 102a and the side surface 102s of the first electronic component 102. In other embodiments, the lower surface 102d is farther away from the wire structure 101, and the first thermal conductor 105 contacts the lower surface 102d of the first electronic component 102, such as the sub-thermal conductors 1051, 1053 of the first thermal conductor 105 contact the lower surface 102d of the first electronic component 102, and some other sub-thermal conductors 1052 are arranged around the first electronic component 102. In a further embodiment, the thermal via 103 has a tapered shape in the direction toward the first electronic component 102, and the thermal via 103 extends through the first thermal conductor 105 to the lower surface 101d of the wire structure 101.

[0036] In addition, the package structure 100 further includes: a molding compound 107 for sealing the second electronic component 104 and the thermal via 103, and Figure 2 As can be seen in FIG. 1 , the top surface 107t of the mold compound 107 is flush with the top surface 104t of the second electronic component 104 and the top surface 103t of the thermal via 103. It should be noted that the top surface 107t of the mold compound 107, the top surface 104t of the second electronic component 104, and the top surface 103t of the thermal via 103 are all surfaces away from the conductor structure 101. In some embodiments, there is no distinguishable interface between the thermal via 103 and the second thermal conductor 106, in which case the top surface 103t of the thermal via 103 is a surface flush with the top surface 107t of the mold compound 107. In some embodiments, the mold compound 107 includes a molding compound, an underfill (such as epoxy resin), and the like.

[0037] In the package structure 100, a redistribution structure 109 is present at the lower surface 104d of the second electronic component 104 opposite to the top surface 104t, so as to connect the second electronic component 104 to other electronic components, such as to the first electronic component 102. In some embodiments, the redistribution structure 109 includes a dielectric layer 109t and a metal layer 109l embedded in the dielectric layer 109t, and the dielectric layer 109t may include but is not limited to polyimide, PA, etc., and the metal layer 109l may include but is not limited to metals such as copper, etc. In addition, the redistribution structure 109 at the lower surface 104d of the second electronic component 104 is sealed by a bottom filler 108. The bottom filler 108 may include epoxy resin, etc. Further, the corresponding metal layer 109l of the redistribution structure 109 at the lower surface 104d of the second electronic component 104 is connected to the metal layer 101l in the wire structure 101 through a microbump 110 (such as made of solder). In addition, at the lower surface 101d of the conductive line structure 101, there is a pad 111P for external connection and an external connector 112 connected to the pad 111P. In some embodiments, the external connector 112 may be a solder ball or the like, and the pad 111P may be a metal pad such as copper or the like. Figure 2 As shown, the pad 111P can be connected to the metal layer 1011 in the conductor structure 101 through a through hole 111V. In some specific embodiments, the through hole 111V includes but is not limited to metal such as copper. In some other embodiments, the first electronic component 102 includes a back side power supply element 102Pw commonly used in the art, such as Figure 2 As shown, the backside power supply element 102Pw is disposed on the lower surface 102 d of the first electronic component 102 .

[0038] In other embodiments, see Figure 2The present application also provides a packaging structure 100, which includes: a wire structure 101; a first electronic component 102, embedded in the wire structure 101; a heat-conducting structure, which includes a thermal via 103 extending through the wire structure 101 and a first heat-conducting member 105 and a second heat-conducting member 106 contacting the thermal via 103, and extending through the wire structure 101 and arranged around the first electronic component 102, wherein the heat-conducting structure 101 is in contact with both the upper surface (i.e., the active surface 102a) and the lower surface 102d of the first electronic component 102, and the upper surface (i.e., the active surface 102a) is opposite to the lower surface 102d. In some embodiments, the first heat conductor 105 is disposed below and around the first electronic component 102 , further, the thermal via 103 contacts the upper surface (i.e., the active surface 102a ) and the side surface 102s of the first electronic component 102 , and the first heat conductor 105 contacts the lower surface 102d of the first electronic component 102 .

[0039] See also Figure 2A , Figure 2A The heat conduction path t of the package structure 100 provided by the present application is shown. short , it can be seen that the shorter the thermal path t short Provides good performance for heat transfer diffusion of the package structure (for example, such as the first electronic component 102). Specifically, according to the law of heat transfer coefficient (k):

[0040]

[0041] The symbol Q represents the heat generated by the package structure 100 / stacked structure 10 (Q long represents the heat generated by the stack structure 10, Q short represents the heat generated by the package structure 100), and the symbol t represents the path through which the heat is dissipated (such as the heat conduction path t short / t long ), symbol A represents the heat dissipation area, and symbol T represents the temperature of the corresponding package structure 100 / stacked structure 10. In this case, assuming that A, ΔT and k are constants, that is, A, ΔT and k of the package structure 100 and the stacked structure 10 are the same, then:

[0042]

[0043] From the above analysis results, the heat Q generated is inversely proportional to the path t through which the heat is dissipated. Therefore, thinner electronic components (such as the first electronic component 102 and the second electronic component 104) can provide better and more efficient heat transfer because a shorter path t can be provided. short .

[0044] In summary, in the present application, the first electronic component 102 and the second electronic component 104 can be relatively thin, and the first electronic component 102 is embedded in the fan-out conductor structure 101, and the back surface (i.e., the top surface 104t) of the second electronic component 104 is relatively thin, so the package structure 100 provided by the present application has a more excellent heat transfer effect (avoiding heat storage) and is conducive to the miniaturization of the package structure 100. A second heat conductor 106 (e.g., a graphene layer) for heat transfer is manufactured at the back surface (i.e., the top surface 104t) of the second electronic component 104 at the top to provide a good path for the heat diffusion flow.

[0045] As the second electronic component 104 of the top layer and the first electronic component 102 of the bottom layer become thinner and thinner, the package structure 100 can also become thinner and thinner, and the package structure 100 provides a small available through-hole size (e.g., a diameter of <5 μm) and a high aspect ratio (e.g., >40 times). In addition, the first electronic component 102 of the bottom layer (such as an EIC chip) can use graphene at the double-sided edges of its upper surface (i.e., active surface 102a) and lower surface 102d to provide better thermal conductivity for the package structure 100, and graphite provides more effective heat transfer from the inside to the outside by contacting the edge of the first electronic component 102 (such as an EIC chip). In addition, the thermal via 103 made of graphene can be used to enhance the high thermal conductivity in the package structure 100.

[0046] Further, the bottom first electronic component 102 is designed as a motherboard enclosed by a solder ball 112, which enhances the heat transfer capability. In addition, the first electronic component 102 has a backside power supply element 102Pw, that is, the thinner first electronic component 102 of the backside power supply design provides a short path through the first electronic component 102. Furthermore, the first electronic component 102 (such as EIC) and the second electronic component 104 (such as VRM) are directly connected through microbumps 110 (or nanowires), reducing the loss or delay of electrical signals. In the packaging structure 100 of the present application, the conductor structure 101 and the redistribution structure 109 have fine pitch (for example, aspect ratio (L / S) less than 2um / 2um) capability. Further, the dielectric layer 101t of the conductor structure 101 covers around the bottom first electronic component 102, which is beneficial to enhance the bonding capability of the thinner first electronic component 102. In the present application, the conductor structure 101 is substrate-less. The substrate-less and wafer level (WL) / panel level packaging (PNL) result in lower costs in manufacturing and material selection.

[0047] exist Figure 2In the package structure 100 shown, the Z direction represents a direction perpendicular to the L horizontal direction and the D vertical direction. Specifically, the length of the first electronic component 102 and the second electronic component 104 in the L horizontal direction and the width in the Z direction are in the range of tens of μm to hundreds of mm, and the thickness of the first electronic component 102 and the second electronic component 104 in the vertical direction D is in the range of 20um to 200um. At the recess R, the size of the gap between the upper surface 101a of the wire structure 101 and the bottom surface 109d of the redistribution structure 109 is in the range of 5um to 20um, and the size of the gap between the active surface 102a of the first electronic component 102 and the lower surface 104d of the second electronic component 104 is in the range of 10um to 50um. The thickness of the second heat conductor 106 in the vertical direction D is in the range of 1um to 50um. The thickness of the molding compound 107 in the vertical direction D is in the range of 20um to 100um, the thickness of the dielectric layer 101t in the conductor structure 101 in the vertical direction D is in the range of 20um to 100um, the diameter of the metal wire in the metal layer 101l in the conductor structure 101 is in the range of 1um to 10um, and the thickness of the corresponding seed layer 101ls in the vertical direction D is in the range of 0.1um to 1um, and the aspect ratio L / S of the metal layer 101l and the seed layer 101ls is 2um / 2um to 20um / 20um. The diameter of the microbump 110 is in the range of 5um to 30um, and the spacing between the microbumps 110 is in the range of 10um to 60um. In addition, the diameter of the external connector 112 is in the range of 30um to 200um, and the spacing between the external connectors 112 is in the range of 50um to 400um. The distance between the horizontal plane L2 and the lower surface 102d of the first electronic component 102 is 0.3-1 times the thickness of the first electronic component 102 in the vertical direction D. The diameter or width of the thermal via 103 in the horizontal direction L is in the range of 5um to 30um, the depth of the thermal via 103 in the vertical direction D is in the range of 15um to 100um, and the aspect ratio (depth / width) of the thermal via 103 is between 0.5 and 40.

[0048] Refer to the following Figures 3 to 28 To describe the application Figure 2 The process flow of forming the package structure 100 is shown.

[0049] See also Figure 3 , placing the first electronic component 102 on the carrier 1001. In some embodiments, the carrier 1001 may be a silicon carrier, a glass carrier, etc., and may have a square shape or a circular shape (eg Fig.29A and Fig.29B). In some embodiments, the first electronic component 102 may be an electronic integrated circuit (EIC) or the like. In addition, the first electronic component 102 has an active surface 102a and a lower surface 102d opposite to the active surface 102a, and a side surface 102s connecting the active surface 102a and the lower surface 102d, and the first electronic component 102 also has a backside power supply element 102Pw disposed in the power supply area. In addition, a pad 102P, such as a copper pad, is disposed at the active surface 102a of the first electronic component 102.

[0050] Afterwards, see Figure 4 , a temporary layer 1002 is formed on the carrier 1001, and a dielectric layer such as polyimide is used as the temporary layer. After forming the temporary layer 1002, see Figure 5 A dielectric layer 101t such as gallium nitride is formed over the temporary layer 1002 and the active surface 102a of the first electronic element 102. Figure 6 After forming the dielectric layer 101t, the dielectric layer 101t is exposed P1 for patterning, thereby forming an opening corresponding to a portion of the pad 102P of the first electronic component 102, and forming a seed layer 101ls' on the surface of the dielectric layer 101t and in the opening. In some embodiments, the seed layer 101ls' includes a copper layer, and in some other embodiments, includes a titanium layer and a copper layer located above the titanium layer. The seed layer 101ls' can be formed using, for example, PVD. Thereafter, see Figures 7 to 9 , a photoresist 1003 is formed and patterned on the seed layer 1011s'. The photoresist can be formed by spin coating, etc., and exposure P2 can be performed for patterning. Patterning forms an opening through the photoresist to expose the seed layer 1011s'. A metal layer 1011 is formed in the opening of the photoresist and on the exposed portion of the seed layer 1011s'. The metal layer 1011 can be formed by plating such as electroplating or chemical plating. The metal layer 1011 may include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer 1011s' on which the metal layer 1011 is not formed are removed. The photoresist 1003 can be removed by an acceptable ashing or stripping process (such as using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer 1011s' is removed, such as by using an acceptable etching process (such as wet or dry etching).

[0051] Afterwards, repeat Figures 5 to 9 The process is repeated until a desired number of dielectric layers 101t and metal layers 101l are formed, thereby forming a conductive line structure 101 having a recess R, such as Fig.10 Next, see Fig.11 The second electronic component 104 is bonded to the metal layer 1011 in the recess R of the conductive line structure 101 through the micro bump 110. Fig.11 As shown, the second electronic component 104 has a top surface 104t' and a lower surface 104d opposite to the top surface 104t', and a redistribution structure 109 is present at the lower surface 104d to connect the second electronic component 104 to the first electronic component 102. In some embodiments, the redistribution structure 109 includes a dielectric layer 109t and a metal layer 109l embedded in the dielectric layer 109t. In some embodiments, the microbump 110 may include solder.

[0052] See also Fig.12 , an underfill 108 is formed between the redistribution structure 109 and the conductive line structure 101 on the second electronic component 104 and around the redistribution structure 109 and the microbump 110. The underfill 108 can reduce stress and protect the joints generated by the reflow of the microbump 110. The underfill 108 can be formed by a capillary flow process after the second electronic component 104 is attached. Fig.13 After forming the bottom filler 108, the top surface 104t' of the second electronic component 104 is etched by, for example, an etching process 1004, thereby forming Fig.14 The top surface 104t is shown. The etching process 1004 can be a wet etch such as with an etching chemical or a dry etch using, for example, oxygen.

[0053] Continue to refer to Fig.14 , forming a mold compound 107 around the second electronic component 104. The mold compound 107 may be formed by printing molding, transfer molding, etc. The mold compound 107 may be a molding compound, a polymer, an epoxy resin, etc., or a combination thereof. A curing step may be performed to cure the mold compound 107; the curing process may be thermal curing, UV curing, etc., or a combination thereof. After forming the mold compound 107, the top surface 104t of the second electronic component 104 is exposed from the mold compound 107.

[0054] See also Fig.15 ,Will Fig.14 The resulting structure is flipped over, and the carrier 1001 and the temporary layer 1002 are removed by a carrier removal process P3 such as a lift-off process. Fig.16 , the lower surface 102d' of the first electronic component 102 is etched by etching process 1005, thereby forming Fig.16 The etching process 1005 is similar to the etching process 1004 and will not be described in detail here.

[0055] See also Figures 16 to 18, a first heat-conducting layer 105' of graphene is formed on the lower surface 102d of the first electronic element 102 and the dielectric layer 101t by a coating process. A photoresist 1006 is formed and patterned on the first heat-conducting layer 105'. The photoresist 1006 can be formed by spin coating, etc., and can be exposed P3 for patterning. Fig.19 After the photoresist 1006 forms an opening, the portion of the first heat-conducting layer 105' exposed by the opening of the photoresist 1006 is etched by an etching process 1007, thereby forming a first heat-conducting member 105 including a plurality of sub-heat-conducting members 1051 ... The etching process 1007 is similar to the etching process 1004 and will not be described in detail here.

[0056] See also Fig. 20 , a dielectric layer 1008 is formed on the first thermal conductive member 105, and then Figures 4 to 9 Similarly, after the dielectric layer 1008 is formed, the dielectric layer 1008 is exposed P4 for patterning, thereby forming openings corresponding to the metal layer 101l in the wire structure 101, the back side power supply element 102Pw in the first electronic element 102, and a portion of the first heat conductor 105, and forming a seed layer 111Vs on the surface of the dielectric layer 1008 and in the openings. In some embodiments, the seed layer 111Vs includes a copper layer, and in some other embodiments, includes a titanium layer and a copper layer located above the titanium layer. The seed layer 111Vs can be formed using, for example, PVD. Thereafter, see Figure 22 to Figure 24 , a photoresist 1009 is formed and patterned on the seed layer 111Vs. The photoresist 1009 can be formed by spin coating, etc., and can be exposed to light for patterning. Patterning forms an opening through the photoresist to expose the seed layer 111Vs. A conductive material is formed in the opening of the photoresist 1009 and on the exposed portion of the seed layer 111Vs. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist 1009 and the seed layer 111Vs are removed, and the portion on which the conductive material is not formed. The photoresist 1009 can be removed by an acceptable ashing or stripping process (such as using oxygen plasma, etc.). Once the photoresist is removed, the exposed portion of the seed layer 111Vs is removed, such as by using an acceptable etching process (such as wet or dry etching), thereby forming a through hole 111V and a pad 111P.

[0057] Afterwards, see Fig.25 ,Will Fig.24 The resulting structure is flipped over, and an opening penetrating the conductive structure 101 is formed in the mold compound 107 and the conductive line structure 101 and beside the side 102s of the first electronic component 102 by a laser drilling process E. Fig.26, graphene is coated in the opening to form the thermal via 103 and the second thermal conductor 106. Next, see Fig. 27 , flip Fig.26 The resulting structure places external connectors 112 such as solder balls on the vias 111V and pads 111P by a ball placement process. Fig.28 , flip Fig.26 The resulting structure is formed by a sawing process Figure 2 The package structure 100 is shown.

[0058] In the above method, first, a PNL (or WL) carrier 1001 for placing the first electronic component 102 at the bottom is prepared. Next, a temporary layer 1002 is coated on the carrier 1001 and around the first electronic component 102. A conductor structure 101 is manufactured from the temporary layer 1002. In addition, a recess R is formed during the manufacturing process of the conductor structure 101. Next, a second electronic component 104 such as a VRM chip is bonded to the conductor structure 101 on the first electronic component 102 at the bottom. Then, a thinned first electronic component 102 is manufactured by back etching, and then a protective layer (such as a mold compound 107) and a heat transfer layer (such as a first thermal element 105) are manufactured.

[0059] Next, the temporary layer 1002 and the carrier 1001 are removed and the thinned second electronic component 104 is produced by back etching. Finally, the overall dielectric layer 1008 (part of the conductor structure 101), the vias 111V and the pads 111P at the bottom, and the ball placement to form the external connector 112 are produced on the bottom side. Next, after the segmentation, the Figure 2 The package structure 100 is shown.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A packaging structure, characterized in that: include: Conductor structure; A first electronic component embedded in the conductor structure; A thermal via passes through the conductive line structure and contacts the first electronic component.

2. The packaging structure according to claim 1, characterized in that: Also includes: A second electronic component is disposed on the conductor structure, Wherein, the second electronic component overlaps with the thermal via in a horizontal direction.

3. The packaging structure according to claim 1, characterized in that: Also includes: The first heat conducting member is disposed under and around the first electronic component and is in contact with the thermal via.

4. The packaging structure according to claim 3, characterized in that: The first heat conductor extends in a direction perpendicular to the thermal via.

5. The packaging structure according to claim 3, characterized in that: Also includes: A second heat conducting member is exposed outside the packaging structure, Wherein, the second heat conducting member is connected to the first heat conducting member through the thermal via.

6. The packaging structure according to claim 1, characterized in that: The first electronic component further includes an active surface facing the conductive line structure, a lower surface opposite to the active surface, and a side surface connecting the active surface and the lower surface. Wherein, the thermal via contacts the active surface and the side surface of the first electronic component.

7. The packaging structure according to claim 3, characterized in that: The first electronic component has a lower surface away from the wire structure, Wherein, the first heat conducting member contacts the lower surface of the first electronic component.

8. The packaging structure according to claim 5, characterized in that: The second heat conducting member is a continuously extending heat conducting member.

9. The packaging structure according to claim 3, characterized in that: The first heat conducting member includes a plurality of discretely distributed heat conducting sub-members.

10. The packaging structure according to claim 9, characterized in that: The plurality of heat conducting sub-members are located at different levels.

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