Wire structure

Abstract

The utility model provides a wire structure. The wire structure comprises a first dielectric layer; the seed layer is arranged on the first dielectric layer; the conductive trace is arranged on the upper surface, deviating from the first dielectric layer, of the seed layer; and the second dielectric layer covers the conductive trace and is in contact with the upper surface of the seed layer. In the prior art, in the wet etching process of a seed layer, an etching solution etches a conductive trace at the same time, so that the conductive trace is thinned, and the bending strength of the conductive trace is easily reduced and even broken, the photoresist is used as a protective layer before etching, the conductive trace is separated from the etching solution, and the conductive trace is prevented from being damaged. Therefore, when the seed layer is etched, the conductive traces are not etched, the conductive traces are prevented from being thinned, the bending strength of the conductive traces is ensured, the normal work of the whole lead structure is ensured, and the problems of open circuit and the like are avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a wire structure. Background Art

[0002] like Figure 1A and Figure 1B The fan-out process mainly forms a seed layer 02 on the upper surface of the dielectric layer 01, forms a conductive trace 03 on the side of the seed layer 02 away from the dielectric layer 01, and then wet etches to remove the seed layer 02 to prevent the conductive trace 03 from short-circuiting. However, during etching, the etching solution 04 removes the seed layer 02 and also etches the conductive trace 03 on the seed layer 02, thereby thinning the conductive trace 03, thinning the finer lines in the conductive trace 03, and causing the bending strength of the conductive trace 03 to decrease, thereby making the finer lines in the conductive trace 03 prone to short circuits during packaging. Utility Model Content

[0003] The purpose of this application is to provide a wire structure.

[0004] The present application proposes a wire structure, comprising:

[0005] a first dielectric layer;

[0006] A seed layer, disposed on the first dielectric layer;

[0007] a conductive trace disposed on an upper surface of the seed layer facing away from the first dielectric layer;

[0008] A second dielectric layer covers the conductive trace and contacts the upper surface of the seed layer.

[0009] The present application provides a wire structure, including a first dielectric layer, a seed layer is arranged on the upper surface of the first dielectric layer, and a conductive trace is arranged on the upper surface of the seed layer away from the first dielectric layer. In order to avoid etching the conductive trace at the same time when etching the seed layer, resulting in the conductive trace being thinned, and the conductive trace is prone to reduce the bending strength, or even open circuit problems, the present application uses a photoresist as a protective layer before etching to isolate the conductive trace from the etching solution to ensure that the conductive trace is not etched when etching the seed layer, so as to avoid the conductive trace being thinned, ensure the bending strength of the conductive trace, and then ensure the normal operation of the entire wire structure without problems such as open circuits. In the process of wet etching the seed layer, part of the seed layer close to the conductive trace will be retained under the protective effect of the photoresist protective layer, so that the overall width of the seed layer will be greater than the width of the conductive trace, that is, part of the seed layer will protrude laterally beyond the side of the conductive trace, which makes the second dielectric layer formed subsequently contact the upper surface of the protruding part of the seed layer, constituting a difference from the existing wire structure. In addition, due to the protective effect of the photoresist protective layer, the side surface of the conductive trace will not be etched and will not form an inward curved surface, but will remain a flat surface.

[0010] In some optional embodiments, the seed layer includes a first seed layer and a second seed layer;

[0011] The first seed layer is disposed on the first dielectric layer, the second seed layer is disposed on an upper surface of the first seed layer facing away from the first dielectric layer, and a sidewall of the second seed layer protrudes beyond a sidewall of the conductive trace.

[0012] In some optional embodiments, the sidewall of the first seed layer protrudes beyond the side surface of the second seed layer.

[0013] In some optional embodiments, the first seed layer sidewall includes a first inwardly contracted curved surface, and the second seed layer sidewall includes a second inwardly contracted curved surface.

[0014] In some optional embodiments, the sidewall of the first seed layer includes a first inwardly contracted curved surface, or the sidewall of the second seed layer includes a second inwardly contracted curved surface.

[0015] In some optional embodiments, the second dielectric layer contacts the upper surface of the conductive trace.

[0016] In some optional embodiments, the orthographic projection of the first seed layer on the first dielectric layer covers the orthographic projection of the second seed layer on the first dielectric layer.

[0017] In some optional embodiments, an orthographic projection of the conductive trace on the first dielectric layer is located within an orthographic projection of the second seed layer on the first dielectric layer.

[0018] In some optional embodiments, the first seed layer sidewall is at a first distance D1 from the second seed layer sidewall, the second seed layer sidewall is at a second distance D2 from the conductive trace sidewall, and the first distance D1 is less than the second distance D2.

[0019] In some optional embodiments, the width of the upper surface of the conductive trace is not equal to the width of the lower surface of the conductive trace.

[0020] In some optional embodiments, the width of the upper surface of the conductive trace is greater than the width of the lower surface of the conductive trace.

[0021] In some optional embodiments, the width of the upper surface of the conductive trace is smaller than the width of the lower surface of the conductive trace.

[0022] In some optional embodiments, the width of the upper surface of the conductive trace is equal to the width of the lower surface of the conductive trace.

[0023] In some optional embodiments, the width of the upper surface of the conductive trace is in the range of 0.5 μm-5 μm.

[0024] In some optional embodiments, the thickness of the conductive trace is in the range of 1 μm-5 μm.

[0025] In some optional embodiments, the thickness of the first seed layer ranges from 200 angstroms to 5000 angstroms.

[0026] In some optional embodiments, the second seed layer has a thickness ranging from 500 angstroms to 10,000 angstroms.

[0027] In some optional embodiments, the width of the upper surface of the conductive trace is a, the width of the lower surface of the conductive trace is b, and the ratio of b / a is in the range of 0.9-1.1.

[0028] In some optional embodiments, the material of the first seed layer is Ti, Ta, W, TiN or TaN.

[0029] In some optional embodiments, the material of the second seed layer is Cu or Ag. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0031] Figure 1A It is a partial structural cross-sectional view of the current wire structure before wet etching;

[0032] Figure 1B It is a partial structural cross-sectional view of the current conductor structure after wet etching;

[0033] Figure 2 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 2a of a conductor structure according to the present application;

[0034] Figure 3 It corresponds to Figure 2 A partial enlarged schematic diagram of the center A;

[0035] Figure 4 It corresponds to Figure 2 A partial enlargement of the middle A Figure 2 ;

[0036] Figure 5 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 5a of a conductor structure according to the present application;

[0037] Figure 6 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 6a of a conductor structure according to the present application;

[0038] Figure 7A-7H They are schematic diagrams of manufacturing steps of an embodiment of the conductor structure of the present application.

[0039] Description of reference numerals / symbols:

[0040] 01-dielectric layer; 02-seed layer; 03-conductive trace; 04-etching solution; 10-first dielectric layer; 20-seed layer; 21-first seed layer; 211-first inward curved surface; 22-second seed layer; 221-second inward curved surface; 30-conductive trace; 40-second dielectric layer; a-width of the upper surface of the conductive trace; b-width of the lower surface of the conductive trace; c-overall thickness of the conductive trace and seed layer; d-width of the first seed layer; e-width of the second seed layer; d1-thickness of the conductive trace; d2-thickness of the first seed layer; d3-thickness of the second seed layer; D1-first distance; D2-second distance; 50-first photoresist structure; 60-second photoresist structure; DETAILED DESCRIPTION

[0041] The specific implementation methods of the present application are described below in conjunction with the accompanying drawings and embodiments. Through the contents recorded in this specification, those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced. It is understood that the specific embodiments described herein are only used to explain the relevant utility model, rather than to limit the utility model. In addition, for the convenience of description, only the parts related to the relevant utility model are shown in the accompanying drawings.

[0042] It should be readily understood that the meanings of “on,” “over,” and “over” in this application should be interpreted in the broadest manner, so that “on” not only means “directly on something,” but also means “on something” including the presence of intermediate components or layers therebetween.

[0043] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0044] As used herein, the term "layer" refers to a portion of a material that includes an area having a certain thickness. A layer may

[0045] To extend over the entire lower or upper structure, or to a degree that is less than the range of the lower or upper structure. In addition, a layer can be a region of a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, one or more layers can be included therein, and / or one or more layers can be present thereon, above and / or below. A layer can include multiple layers. For example, a semiconductor layer can include one or more doped or undoped semiconductor layers, and can have the same or different materials.

[0046] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed in the present application. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present application without substantially changing the technical content.

[0047] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0048] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] refer to Figure 2 , Figure 2 FIG. 2 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 2a of the conductor structure according to the present application; Figure 2 As shown, the present application proposes a wire structure, comprising: a first dielectric layer 10;

[0050] A seed layer 20 is disposed on the first dielectric layer 10;

[0051] A conductive trace 30 is disposed on an upper surface of the seed layer 20 facing away from the first dielectric layer 10;

[0052] The second dielectric layer 40 covers the conductive trace 30 and contacts the upper surface of the seed layer 20 .

[0053] Here, the material of the first dielectric layer 10 and the second dielectric layer 40 may be, for example, PI (polyimide), PBO (polybenzoxazole), BCB (benzocyclobutene), or the like.

[0054] It should be noted that a conductor structure provided in the present application includes a first dielectric layer 10, a seed layer 20 is arranged on the upper surface of the first dielectric layer 10, and a conductive trace 30 is arranged on the upper surface of the seed layer 20 away from the first dielectric layer 10. In order to solve the problem that when the seed layer 20 is etched, the conductive trace 30 will also be etched at the same time, thereby causing the conductive trace 30 to be thinned, and the bending strength of the conductive trace 30 is easily reduced or even broken, the embodiment of the present application uses a photoresist as a protective layer before etching to isolate the conductive trace 30 from the etching solution to ensure that when the seed layer 20 is etched, the conductive trace 30 will not be etched, thereby avoiding the conductive trace 30 from being thinned, ensuring the bending strength of the conductive trace 30, and thus ensuring the normal operation of the entire conductor structure without problems such as circuit breakage.

[0055] In the manufacturing process of the conductor structure of the present application, during the wet etching process of the seed layer 20,

[0056] The portion of the seed layer 20 near the conductive trace 30 will be retained under the protective effect of the photoresist protective layer, so that the overall width of the seed layer 20 will be greater than the width of the conductive trace 30, that is, the portion of the seed layer 20 will protrude laterally beyond the side of the conductive trace 30, which makes the second dielectric layer 40 formed subsequently contact the upper surface of the protruding portion of the seed layer 20, constituting a difference from the existing wire structure. In addition, due to the protective effect of the photoresist protective layer, the side of the conductive trace 30 will not be etched, and an inward curved surface will not be formed, but it will remain a flat surface.

[0057] In some optional embodiments, the seed layer 20 includes a first seed layer 21 and a second seed layer 22; the first seed layer 21 is disposed on the first dielectric layer 10, the second seed layer 22 is disposed on the upper surface of the first seed layer 21 away from the first dielectric layer 10, and the sidewall of the second seed layer 22 protrudes from the sidewall of the conductive trace 30. Here, the material of the first seed layer 21 can be Ti, Ta, W, TiN or TaN; the material of the second seed layer 22 can be Cu or Ag.

[0058] Continue to refer Figure 2 , a width a of the upper surface of the conductive trace 30, a width b of the lower surface of the conductive trace 30, and a thickness d1 of the conductive trace 30. For example, the width of the upper surface of the conductive trace 30 and the width of the lower surface of the conductive trace 30 may be equal or unequal; Figure 2For example, the width a of the upper surface of the conductive trace 30 is greater than the width b of the lower surface of the conductive trace 30, that is, a>b; wherein the width a of the upper surface of the conductive trace 30 ranges from 0.5μm to 5μm, for example, a can be 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 2.0μm, 3.0μm, 4.0μm or 5.0μm; the ratio of b / a ranges from 0.9 to 1.1, for example, the ratio of b / a can be 0.9, 1 or 1.1, Figure 2 In the figure, the ratio of b / a is less than 1. Taking the ratio of b / a as 0.9 as an example, the range of b is determined to be 0.45μm-4.5μm. For example, b can be 0.45μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 2.0μm, 3.0μm, 4.0μm or 4.5μm. The thickness d1 of the conductive trace 30 ranges from 1μm to 5μm. For example, d1 can be 1μm, 2μm, 3μm, 4μm or 5μm. The second dielectric layer 40 contacts the upper surface of the conductive trace 30; in addition, the orthographic projection of the first seed layer 21 on the first dielectric layer 10 covers the orthographic projection of the second seed layer 22 on the first dielectric layer 10, and the orthographic projection of the conductive trace 30 on the first dielectric layer 10 is located within the orthographic projection of the second seed layer 22 on the first dielectric layer 10. Figure 2 In the embodiment, the width of the first seed layer 21 is d, the width of the second seed layer 22 is e, the b / e ratio ranges from 0.9 to 1, for example, the b / e ratio may be 0.98; the b / d ratio ranges from 0.9 to 1, for example, the b / d ratio may be 0.95. Figure 2 The overall thickness c of the conductive trace 30 and the seed layer 20 is in the range of 1 μm to 5 μm. For example, a may be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0059] For ease of understanding, continue to refer to Figure 3 , Figure 3 It corresponds to Figure 2 The enlarged schematic diagram of the part at A in the middle is as follows: The seed layer 20 located on the upper surface of the first dielectric layer 10 includes a first seed layer 21 and a second seed layer 22 arranged in a stacked manner, wherein the first seed layer 21 is located on the upper surface of the first dielectric layer 10, and the second seed layer 22 is located on the side surface of the first seed layer 21 away from the first dielectric layer 10, and the side wall of the first seed layer 21 protrudes from the side surface of the second seed layer 22. The side wall of the first seed layer 21 is a first distance D1 from the side wall of the second seed layer 22, and the side wall of the second seed layer 22 is a second distance D2 from the side wall of the conductive trace 30, and the first distance D1 is less than the second distance D2.

[0060] The second distance D2, that is, the first seed layer 21 and the second seed layer 22 form a step structure.

[0061] refer to Figure 4 , Figure 4 It corresponds to Figure 2 A partial enlargement of the middle A Figure 2 For example, the sidewall of the first seed layer 21 includes a first inward curved surface 211, and the sidewall of the second seed layer 22 includes a second inward curved surface 221; for example, the sidewall of the first seed layer 21 includes a first inward curved surface 211; for example, the sidewall of the second seed layer 22 includes a second inward curved surface 221. The thickness d2 of the first seed layer 21 ranges from 200 angstroms to 5000 angstroms, for example, d2 can be 200 angstroms, 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1000 angstroms, 2000 angstroms, 3000 angstroms, 4000 angstroms or 5000 angstroms. The thickness d3 of the second seed layer 22 ranges from 500 angstroms to 10,000 angstroms. For example, d3 may be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 900 angstroms, 1,000 angstroms, 2,000 angstroms, 3,000 angstroms, 4,000 angstroms, 5,000 angstroms, 6,000 angstroms, 7,000 angstroms, 8,000 angstroms, 9,000 angstroms or 10,000 angstroms. Here, the unit "angstrom" is also called "angstrom meter" and the symbol is Equal to 10-10m, which is one tenth of a nanometer.

[0062] refer to Figure 5 , Figure 5 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 5a of a conductor structure according to the present application; Figure 5 Comparison Figure 2 In terms of Figure 5 The cross section of the conductive track in is rectangular, that is, the width a of the upper surface of the conductive track is equal to the width b of the lower surface of the conductive track. Figure 5 In the embodiment, a seed layer 20 is arranged on the upper surface of the first dielectric layer 10, the seed layer 20 includes a first seed layer 21 and a second seed layer 22 which are stacked, a conductive trace 30 is arranged on the side of the second seed layer 22 away from the first seed layer 21, and the second dielectric layer 40 is in contact with the upper surface of the conductive trace 30; in addition, the orthographic projection of the first seed layer 21 on the first dielectric layer 10 covers the orthographic projection of the second seed layer 22 on the first dielectric layer 10, and the orthographic projection of the conductive trace 30 on the first dielectric layer 10 is located within the orthographic projection of the second seed layer 22 on the first dielectric layer 10.

[0063] refer to Figure 6 , Figure 6 is a schematic diagram of a partial longitudinal cross-sectional structure of an embodiment 6a of a conductor structure according to the present application; Figure 6 Comparison Figure 2 In terms of Figure 6The cross section of the conductive track in is a regular trapezoid, that is, the width a of the upper surface of the conductive track is smaller than the width b of the lower surface of the conductive track. Figure 6 In the embodiment, a seed layer 20 is arranged on the upper surface of the first dielectric layer 10, the seed layer 20 includes a first seed layer 21 and a second seed layer 22 which are stacked, a conductive trace 30 is arranged on the side of the second seed layer 22 away from the first seed layer 21, and the second dielectric layer 40 is in contact with the upper surface of the conductive trace 30; in addition, the orthographic projection of the first seed layer 21 on the first dielectric layer 10 covers the orthographic projection of the second seed layer 22 on the first dielectric layer 10, and the orthographic projection of the conductive trace 30 on the first dielectric layer 10 is located within the orthographic projection of the second seed layer 22 on the first dielectric layer 10.

[0064] For easier understanding, refer to Figure 7A-7H Schematic diagrams of the manufacturing steps of an embodiment of the conductor structure of the present application are shown in FIG. Fig. 7A As shown, a first dielectric layer 10 is provided, a first seed layer 21 is formed on the upper surface of the first dielectric layer 10, a second seed layer 22 is formed on the side surface of the first seed layer 21 away from the first dielectric layer 10, and the first seed layer 21 and the second seed layer 22 are stacked as a seed layer 20. Figure 7B is Fig. 7A On the basis of, a first photoresist structure 50 is formed on the side of the seed layer 20 away from the first dielectric layer 10, where the first photoresist structure 50 plays a role in defining a pattern; continue to refer to Figure 7C ,exist Figure 7B Based on the pattern defined by the photoresist structure 50, for example, a conductive trace 30 can be formed by an electroplating process; Fig.7D In the embodiment, a second photoresist structure 60 is formed on the upper surface of the conductive trace 30.

[0065] The second photoresist structure 60 at least completely covers the upper surface of the conductive trace 30 and contacts the upper surface of the conductive trace 30. The second photoresist structure 60 plays a protective role. Fig. 7E In, yes Fig.7D The structure in the embodiment of the present invention is dry-etched, and a portion of the photoresist (including the first photoresist structure 50 and the second photoresist structure 60) is removed by plasma. At this time, the remaining photoresist (part of the first photoresist structure 50 and part of the second photoresist structure 60) forms a protective layer that wraps the conductive trace 30, which plays a role in isolating the etching liquid and preventing it from being etched, so that the conductive trace 30 cannot be etched in the subsequent wet etching process; then, the seed layer 20 is wet-etched to form Figure 7F In the wet etching process, the conductive trace 30 is protected by the remaining photoresist and remains unetched; compared to Figure 7F , Figure 7GThe first photoresist structure 50 and the second photoresist structure 60 previously left as a protective layer are completely removed by dry etching. The conductive trace 30 formed by removing the first photoresist structure 50 and the second photoresist structure 60 by this method is finally smooth and has no etching burrs. Figure 7F On the basis of the above, a second dielectric layer 40 is further formed, the second dielectric layer 40 covers the conductive trace 30 and contacts the upper surface of the seed layer 20, and the above method is used to prepare the Figure 2 The conductor structure 2a shown has no cutting defects, and the problem of fine line delamination in the conductive trace 30 is greatly reduced.

[0066] Although the present application has been described and illustrated with reference to the specific embodiments of the present application, these descriptions and illustrations do not limit the present application. It is clearly understood by those skilled in the art that various changes can be made, and equivalent elements can be substituted in the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present application and the actual implementation. There may be other embodiments of the present application that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, material compositions, methods or processes to the goals, spirits and scopes of the present application. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.

Claims

1. A conductor structure, characterized in that: include: a first dielectric layer; a seed layer, disposed on the first dielectric layer; a conductive trace disposed on an upper surface of the seed layer facing away from the first dielectric layer; A second dielectric layer covers the conductive trace and contacts the upper surface of the seed layer.

2. The conductor structure according to claim 1, wherein: The seed layer includes a first seed layer and a second seed layer; The first seed layer is disposed on the first dielectric layer, the second seed layer is disposed on an upper surface of the first seed layer facing away from the first dielectric layer, and a sidewall of the second seed layer protrudes beyond a sidewall of the conductive trace.

3. The conductor structure according to claim 2, wherein: The sidewall of the first seed layer protrudes from the side surface of the second seed layer.

4. The conductor structure according to claim 3, wherein: The sidewall of the first seed layer includes a first inward-contracted curved surface, and the sidewall of the second seed layer includes a second inward-contracted curved surface.

5. The conductor structure according to claim 3, wherein: The sidewall of the first seed layer includes a first inwardly contracted curved surface, or the sidewall of the second seed layer includes a second inwardly contracted curved surface.

6. The conductor structure according to claim 1, wherein: The second dielectric layer contacts an upper surface of the conductive trace.

7. The conductor structure according to claim 2, wherein: An orthographic projection of the first seed layer on the first dielectric layer covers an orthographic projection of the second seed layer on the first dielectric layer.

8. The conductor structure according to claim 7, wherein: An orthographic projection of the conductive trace on the first dielectric layer is located within an orthographic projection of the second seed layer on the first dielectric layer.

9. The conductor structure according to claim 2, wherein: The first seed layer sidewall is at a first distance D1 from the second seed layer sidewall, and the second seed layer sidewall is at a second distance D2 from the conductive trace sidewall. The first distance D1 is less than the second distance D2.

10. The conductor structure according to any one of claims 1 to 9, characterized in that: The width of the upper surface of the conductive trace is not equal to the width of the lower surface of the conductive trace.

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