Low void rate chip packaging structure

Abstract

The utility model discloses a low void rate chip packaging structure, comprising a chip base island, the upper surface of the chip base island is provided with a plurality of grooves, the upper surface of the chip base island is connected with a chip through a welding material at the grooves, the chip is provided with a plurality of bonding leads, and the bonding leads are connected with the chip through the welding material. According to the invention, the plurality of grooves are vertically and horizontally arranged at equal intervals, and the welding material is located at the center of the grooves, so that the heat dissipation is uniform, the heat dissipation performance of the chip is improved, and in the cooling shrinkage process of the welding material, vacancies after air or soldering flux is discharged can be filled by backflow filling of the grooves. According to the packaging structure, the problem of welding voids is successfully solved on the premise that the original supporting mode of the chip base island to the chip is not affected, meanwhile, the grooves also have a locking function, the contact area and the binding force between the welding material and the chip base island can be enhanced, the welding material and the chip base island are not prone to delamination and separation, and the reliability of the packaging structure is improved. Therefore, the quality and the reliability of the product are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip packaging, in particular to a low void rate chip packaging structure. Background Art

[0002] With the development of science and technology, semiconductor devices and components have been widely used in engineering and commerce. Among them, the welding method of the chip is also a very important link to its reliability, which will directly affect the stability of the chip's operation.

[0003] At present, there are some shortcomings in the existing chip welding method, that is, the bonding part between the chip and the chip base island is prone to voids, delamination, and tilting of the chip after bonding. In the prior art, the thickness of the welding material is generally 15-20μm. After heating, baking and curing welding, many voids will appear in the welding material between the chip and the chip base island, which seriously affects the heat dissipation of the chip packaging product. In order to reduce welding voids, through experimental verification of welding materials, it is finally found that when the amount of welding material reaches a certain requirement and the thickness is greater than 30μm, the welding voids will be significantly reduced and meet the product use and heat dissipation requirements.

[0004] However, when the thickness of the solder is greater than 30μm, although the problem of solder voids is solved, it has an adverse effect on the subsequent packaging process. Due to the large thickness of the solder, it is easy for the chip to tilt beyond the standard during mounting. The tilt of the chip after welding will seriously affect the welding quality and output. At the same time, the chip tilt will also cause inconsistent thickness of the welding material, which will ultimately lead to uneven chip heat dissipation and problems with wire bonding, affecting the heat dissipation stability and reliability of wire bonding. In summary, a new packaging method is proposed, which can not only effectively solve the problem of solder voids, but also improve the heat dissipation and stability and reliability of the chip. Utility Model Content

[0005] The utility model aims to provide a chip packaging structure with a low void ratio, so as to solve the problem that the existing packaging method proposed in the above background technology has welding voids, thereby causing the chip heat dissipation performance to decrease.

[0006] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a low void rate chip packaging structure, including a chip base island, a plurality of grooves are opened on the upper surface of the chip base island, a chip is connected to the upper surface of the chip base island at the grooves through welding material, and a plurality of bonding wires are arranged on the chip.

[0007] Preferably, the other end of the bonding wire away from the chip is connected to a sub-chip base island.

[0008] Preferably, the thickness of the soldering material placed above the chip base island is 15-20 μm.

[0009] Preferably, the depth of the groove is 15-25 μm.

[0010] Preferably, the plurality of grooves are arranged at equal distances in both directions.

[0011] Preferably, the welding material is located at the center of the groove.

[0012] Compared with the prior art, the beneficial effects of the utility model are as follows: the present application utilizes a plurality of grooves arranged at equal distances in the vertical and horizontal directions, and the welding material is located at the center of the groove, so that the heat dissipation is uniform and the heat dissipation performance of the chip is improved. Moreover, during the cooling and shrinking process, the welding material can be filled by the groove reflux to fill the vacant space after the air or flux is discharged, so that the packaging structure successfully solves the welding void problem without affecting the original chip base island's support method for the chip. At the same time, the groove also has a locking effect, and can also enhance the contact area and bonding force between the welding material and the chip base island, making it more difficult for the welding material and the chip base island to delaminate and separate, thereby improving the quality and reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is the overall structural view of the utility model;

[0014] Figure 2 It is a top view of the utility model.

[0015] In the figure: 1. Chip base island; 2. Soldering material; 3. Groove; 4. Chip; 5. Bonding wire. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0017] Reference Figure 1 and Figure 2 As shown, the utility model provides a technical solution for a low void rate chip packaging structure:

[0018] A low void rate chip packaging structure includes a chip base island 1, a plurality of grooves 3 are formed on the upper surface of the chip base island 1, a chip 4 is connected to the upper surface of the chip base island 1 at the grooves 3 through welding material 2, and a plurality of bonding wires 5 are arranged on the chip 4.

[0019] The other end of the bonding wire 5 away from the chip 4 is connected to the sub-chip base island. The thickness of the welding material 2 placed on the chip base island 1 is 15-20μm, the depth of the groove 3 is 15-25μm, and several grooves 3 are arranged at equal distances vertically and horizontally, and the welding material 2 is located at the center of the groove 3.

[0020] Through the arrangement and cooperation of the chip base island 1, welding material 2, groove 3 and chip 4, a plurality of grooves 3 are arranged at equal distances in the vertical and horizontal directions, and the welding material 2 is located at the center of the groove 3, so that the heat dissipation is uniform and the heat dissipation performance of the chip 4 is improved. In addition, during the cooling and shrinking process, the welding material 2 can be reflowed through the groove 3 to fill the vacant space after the air or flux is discharged, so that the packaging structure successfully solves the welding void problem without affecting the original chip base island 1 supporting the chip 4. At the same time, the groove 3 also has a locking effect, and can also enhance the contact area and bonding force between the welding material 2 and the chip base island 1, making it more difficult for the welding material 2 and the chip base island 1 to delaminate and separate, thereby improving the quality and reliability of the product.

[0021] Working principle: When the chip uses the packaging structure of the present application, since the thickness of the welding material 2 between the chip 4 and the chip base island 1 is 15-20μm, it does not affect the original chip base island 1 to support the chip 4, so the chip 4 will not be tilted beyond the standard, even if it is fully tilted, it will not exceed 15-20μm, which meets the requirements of chip loading and product functionality. The depth of the groove 3 is 15-25μm, so that the overall thickness of the welding material 2 at the groove 3 below the chip 4 becomes greater than 30μm, and the air and flux volatilization between the chip 4 and the welding material 2 It can be discharged through the groove 3. Since a number of grooves 3 are arranged at equal distances in the vertical and horizontal directions, the welding material 2 is located at the center of the groove 3, so that the heat dissipation is uniform and the heat dissipation performance of the chip 4 is improved. In addition, the welding material 2 can be reflowed through the groove 3 during the cooling and shrinking process to fill the vacant space after the air or flux is discharged, successfully solving the welding void problem. At the same time, the groove 3 also has a locking effect, and can also enhance the contact area and bonding force between the welding material 2 and the chip base island 1, making it more difficult for the welding material 2 and the chip base island 1 to delaminate and separate, thereby improving the quality and reliability of the product.

[0022] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A low void ratio chip packaging structure, comprising a chip base island (1), characterized in that: The upper surface of the chip base island (1) is provided with a plurality of grooves (3), the upper surface of the chip base island (1) is connected to a chip (4) at the grooves (3) via welding material (2), and the chip (4) is provided with a plurality of bonding wires (5).

2. The low void ratio chip packaging structure according to claim 1, characterized in that: The other end of the bonding wire (5) away from the chip (4) is connected to a sub-chip base island.

3. The low void ratio chip packaging structure according to claim 1, characterized in that: The thickness of the soldering material (2) placed above the chip base island (1) is 15-20 μm.

4. The low void ratio chip packaging structure according to claim 3, characterized in that: The depth of the groove (3) is 15-25 μm.

5. The low void ratio chip packaging structure according to claim 1, characterized in that: A plurality of grooves (3) are arranged at equal distances in both directions.

6. The low void ratio chip packaging structure according to claim 1, characterized in that: The welding material (2) is located at the center of the groove (3).

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