Power management chip and power management circuit
By designing a power management chip with built-in gallium nitride, the package structure and silicon MOS devices are used to solve the problems of anti-interference, reliability and power productivity of gallium nitride devices in power applications, and efficient power management and miniaturization and high power density power products are achieved.
Patent Information
- Application Number
- CN202421668103.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-03-04
- Estimated Expiration
- 2034-07-15
AI Technical Summary
In power applications, existing gallium nitride power devices have problems such as poor anti-interference ability, poor reliability and poor power supply productivity, and external driving chips cause interference from connected parasitic inductance.
Design a power management chip with built-in gallium nitride. By packaging the PWM controller, MOS device and gallium nitride device in the same package structure, and adding silicon MOS devices between the two, the negative voltage shutdown problem is solved, so that the existing PWM control chip can control DM gallium nitride devices.
It improves the anti-interference, reliability and power productivity of gallium nitride devices in power supply applications, simplifies driver chip design, reduces costs, and realizes miniaturization and high power density of power products.
Smart Images
Figure CN222563696U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of power management chips, and relates to a power management chip, in particular to a power management chip and a power management circuit with built-in gallium nitride. Background Art
[0002] Gallium nitride power devices are currently divided into enhancement mode (E-Mode l, referred to as EM) and depletion mode (D-Mode l, referred to as DM). Existing gallium nitride power devices are difficult to produce, costly, have poor anti-interference capabilities, and complex control methods. As a single power device, it is difficult to promote large-scale application. The advantage of gallium nitride power devices is that they can operate at higher switching frequencies, reducing the size and cost of magnetic core components and filter components.
[0003] One of the market opportunities for GaN power chips is consumer electronics. As the charging power of mobile phones increases, the portability becomes worse as the power of adapters and chargers changes from 5W, 10W to 65W, 125W. However, chargers using GaN chips are small and charge quickly. Therefore, there are great challenges in designing GaN drivers, such as cost, performance, and power supply production pass rate.
[0004] Existing GaN product solutions all use an external driver chip. In power supply applications, the driver chip and GaN power device are independent of each other and are connected by PCB traces. There will be a certain amount of parasitic inductance in the connection between the two. When the switch signal travels back and forth on this connection, the parasitic inductance will cause a lot of voltage noise, which will cause the GaN power device to malfunction.
[0005] In view of this, there is an urgent need to design a new power management chip to overcome at least some of the above-mentioned defects of the existing power management chips. Utility Model Content
[0006] The utility model provides a power management chip and a power management circuit, which can improve the anti-interference performance, reliability and power manufacturability of gallium nitride devices in power supply applications.
[0007] In order to solve the above technical problems, according to one aspect of the utility model, the following technical solution is adopted:
[0008] A power management chip, comprising: a PWM controller, a MOS device and a gallium nitride device;
[0009] The PWM controller is used to generate a high-frequency PWM signal, and the output end of the PWM controller is connected to the input end of the MOS device to send the generated PWM signal to the MOS device;
[0010] The output end of the MOS device is connected to the input end of the GaN device, and a corresponding signal is formed according to the received PWM signal and sent to the GaN device; the GaN device performs a switching action according to the received signal.
[0011] As an implementation mode of the present invention, the gate of the gallium nitride device is connected to the source of the MOS device, and the source of the gallium nitride device is connected to the drain of the MOS device; the PWM controller is connected to the gate and source of the MOS device.
[0012] As an implementation mode of the utility model, the power management chip includes a packaging structure; the PWM controller, MOS device and gallium nitride device are packaged in the same packaging structure.
[0013] As an implementation mode of the utility model, the packaging structure is provided with a first base island, a second base island and a third base island; the first base island is provided with a PWM controller, the second base island is provided with a MOS device, and the third base island is provided with a gallium nitride device.
[0014] As an implementation mode of the utility model, the power management chip includes a first Drain pin, a first GND pin, a second GND pin, a CS pin, a second Drain pin, a VDD pin and a FB pin;
[0015] The first Drain pin is connected to the drain of the gallium nitride device, and the second Drain pin is connected to the drain of the MOS device; the PWM controller is connected to the VDD pin and the FB pin respectively, and the MOS device is connected to the CS pin.
[0016] According to another aspect of the utility model, the following technical solution is adopted: a power management circuit, the power management circuit includes the above-mentioned power management chip.
[0017] As an implementation mode of the utility model, the power management circuit further includes an input rectifier filter circuit, an isolation transformer and a secondary rectifier filter circuit; the rectifier filter circuit is respectively connected to the PWM controller and the isolation transformer, and the isolation transformer is respectively connected to the gallium nitride device and the secondary rectifier filter circuit;
[0018] The gallium nitride device is directly connected to the primary of the isolation transformer. As the gallium nitride device switches, the isolation transformer converts the DC high voltage level into a low voltage pulsating level through its turns ratio, and then converts it into the low voltage DC level required by the load through the secondary rectification and filtering circuit.
[0019] As an implementation mode of the utility model, the power management circuit further includes an isolation feedback circuit, and the isolation feedback circuit is connected to the load and the PWM controller respectively.
[0020] As an implementation mode of the utility model, the rectification and filtering circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4 and a first capacitor C1;
[0021] The cathode of the first diode D1 is respectively connected to the cathode of the third diode D3 and the first end of the first capacitor C1; the anode of the first diode D1 is connected to the cathode of the second diode D2, and the anode of the third diode D3 is connected to the cathode of the fourth diode D4; the anode of the second diode D2 is respectively connected to the anode of the fourth diode D4 and the second end of the first capacitor C1.
[0022] The beneficial effect of the utility model is that the power management chip and the power management circuit proposed by the utility model can improve the anti-interference performance, reliability and power manufacturability of gallium nitride devices in power supply applications.
[0023] The utility model solves the problems of poor anti-interference, poor reliability and power supply manufacturability of gallium nitride devices in power supply applications by using a sealing method on the basis of DM.
[0024] In one use scenario of the utility model, the driver chip and the gallium nitride power device chip of the utility model are sealed in the same package to solve the parasitic inductance interference problem of the connection. At the same time, a silicon MOS device is added between the two to solve the problem of negative pressure shutdown, so that the existing ordinary PWM control chip can be controlled.
[0025] The utility model utilizes the power management driver chip to control the switch of ordinary silicon MOS to realize the negative pressure shutdown function of DM gallium nitride, thereby eliminating the need to redesign the negative pressure driver chip, and adopts a simple ordinary PWM control chip to realize the control of DM gallium nitride devices, providing a basic platform for the vigorous development of gallium nitride, and also injecting new kinetic energy into the miniaturization and high power density of power supply products, thus greatly saving social resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Schematic diagram of a circuit module of a power management circuit in an embodiment of the utility model.
[0027] Figure 2 FIG. 1 is a circuit diagram of a power management chip in an embodiment of the utility model.
[0028] Figure 3 The figure is a schematic diagram of the packaging of a power management chip in one embodiment of the utility model.
[0029] Figure 4 FIG. 4 is a circuit diagram of a power management circuit in an embodiment of the utility model. DETAILED DESCRIPTION
[0030] The preferred embodiments of the present utility model are described in detail below with reference to the accompanying drawings.
[0031] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.
[0032] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced and are also within the scope of the present invention.
[0033] The term "connection" as used in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.
[0034] The utility model discloses a power management chip. Figure 1 This is a schematic diagram of the composition of the power management circuit in one embodiment of the utility model; please refer to Figure 1 The power management chip is a part of the power management circuit, and the power management chip includes: a PWM controller 1, a MOS device 2 and a gallium nitride device 3. The PWM controller 1 is used to generate a high-frequency PWM signal, and the output end of the PWM controller is connected to the input end of the MOS device 2, and the generated PWM signal is sent to the MOS device 2. The output end of the MOS device 2 is connected to the input end of the gallium nitride device 3, and a corresponding signal is formed according to the received PWM signal and sent to the gallium nitride device 3; the gallium nitride device 3 performs a switching action according to the received signal.
[0035] Figure 2 This is a circuit diagram of a power management chip in an embodiment of the utility model; please refer to Figure 2 In one embodiment of the present invention, the gate of the gallium nitride device is connected to the source of the MOS device, and the source of the gallium nitride device is connected to the drain of the MOS device; the PWM controller is connected to the gate and source of the MOS device.
[0036] Figure 3 This is a schematic diagram of the packaging of a power management chip in an embodiment of the utility model; please refer to Figure 3 In one embodiment of the utility model, the power management chip includes a packaging structure; the PWM controller, the MOS device and the gallium nitride device are packaged in the same packaging structure. The packaging structure is provided with a first base island, a second base island and a third base island; the first base island is provided with a PWM controller, the second base island is provided with a MOS device, and the third base island is provided with a gallium nitride device.
[0037] The power management chip includes a first Drain pin, a first GND pin, a second GND pin, a CS pin, a second Drain pin, a VDD pin and an FB pin; the first Drain pin is connected to the drain of the gallium nitride device, and the second Drain pin is connected to the drain of the MOS device; the PWM controller is respectively connected to the VDD pin and the FB pin, and the MOS device is connected to the CS pin.
[0038] The utility model further discloses a power management circuit, and the power management circuit includes the power management chip mentioned above.
[0039] like Figure 1 As shown, in one embodiment of the utility model, the power management circuit further includes a rectifier filter circuit 4, an isolation transformer 5 and a secondary rectifier filter circuit 6; the rectifier filter circuit 4 is respectively connected to the PWM controller 1 and the isolation transformer 5, and the isolation transformer 5 is respectively connected to the gallium nitride device 3 and the secondary rectifier filter circuit 6. The gallium nitride device 3 is directly connected to the primary of the isolation transformer 5. With the switching action of the gallium nitride device 3, the isolation transformer 5 converts the DC high voltage level into a low voltage pulsating level through its turns ratio, and then converts it into the low voltage DC level required by the load through the secondary rectifier filter circuit 6. In addition, the power management circuit may further include an isolation feedback circuit 7, and the isolation feedback circuit 7 is respectively connected to the load and the PWM controller 1.
[0040] Figure 4 This is a circuit diagram of a power management circuit in an embodiment of the present utility model; please refer to Figure 4 In one embodiment of the utility model, the rectifier filter circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4 and a first capacitor C1. The cathode of the first diode D1 is connected to the cathode of the third diode D3 and the first end of the first capacitor C1; the anode of the first diode D1 is connected to the cathode of the second diode D2, and the anode of the third diode D3 is connected to the cathode of the fourth diode D4; the anode of the second diode D2 is connected to the anode of the fourth diode D4 and the second end of the first capacitor C1.
[0041] The secondary rectifier and filter circuit 6 includes a fifth diode D5 and a second capacitor C2. The positive electrode of the fifth diode D5 is connected to the isolation transformer 5, and the negative electrode of the fifth diode D5 is connected to the first end of the second capacitor C2. The second end of the second capacitor C2 is connected to the isolation transformer 5.
[0042] In summary, the power management chip and power management circuit proposed in the present invention can improve the anti-interference performance, reliability and power manufacturability of gallium nitride devices in power applications.
[0043] The utility model solves the problems of poor anti-interference, poor reliability and power supply manufacturability of gallium nitride devices in power supply applications by using a sealing method on the basis of DM.
[0044] In one use scenario of the utility model, the driver chip and the gallium nitride power device chip of the utility model are sealed in the same package to solve the parasitic inductance interference problem of the connection. At the same time, a silicon MOS device is added between the two to solve the problem of negative pressure shutdown, so that the existing ordinary PWM control chip can be controlled.
[0045] The utility model utilizes the power management driver chip to control the switch of ordinary silicon MOS to realize the negative pressure shutdown function of DM gallium nitride, thereby eliminating the need to redesign the negative pressure driver chip, and adopts a simple ordinary PWM control chip to realize the control of DM gallium nitride devices, providing a basic platform for the vigorous development of gallium nitride, and also injecting new kinetic energy into the miniaturization and high power density of power supply products, thus greatly saving social resources.
[0046] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0047] The description and application of the utility model here are illustrative, and it is not intended to limit the scope of the utility model to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the utility model can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the utility model. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the utility model.
Claims
1. A power management chip, characterized in that: The power management chip includes: a PWM controller, a MOS device and a gallium nitride device; The PWM controller is used to generate a high-frequency PWM signal, and the output end of the PWM controller is connected to the input end of the MOS device to send the generated PWM signal to the MOS device; The output end of the MOS device is connected to the input end of the GaN device, and a corresponding signal is formed according to the received PWM signal and sent to the GaN device; the GaN device performs a switching action according to the received signal.
2. The power management chip according to claim 1, characterized in that: The gate of the gallium nitride device is connected to the source of the MOS device, and the source of the gallium nitride device is connected to the drain of the MOS device; The PWM controller is connected to the gate and source of the MOS device.
3. The power management chip according to claim 1, characterized in that: The power management chip comprises a packaging structure; the PWM controller, MOS device and gallium nitride device are packaged in the same packaging structure.
4. The power management chip according to claim 3, characterized in that: The packaging structure is provided with a first base island, a second base island and a third base island; the first base island is provided with a PWM controller, the second base island is provided with a MOS device, and the third base island is provided with a gallium nitride device.
5. The power management chip according to claim 3, characterized in that: The power management chip includes a first Drain pin, a first GND pin, a second GND pin, a CS pin, a second Drain pin, a VDD pin and a FB pin; The first Drain pin is connected to the drain of the gallium nitride device, and the second Drain pin is connected to the drain of the MOS device; the PWM controller is connected to the VDD pin and the FB pin respectively, and the MOS device is connected to the CS pin.
6. A power management circuit, characterized in that: The power management circuit comprises the power management chip according to any one of claims 1 to 5.
7. The power management circuit according to claim 6, characterized in that: The power management circuit further includes an input rectifier filter circuit, an isolation transformer and a secondary rectifier filter circuit; the rectifier filter circuit is connected to the PWM controller and the isolation transformer respectively, and the isolation transformer is connected to the gallium nitride device and the secondary rectifier filter circuit respectively; The gallium nitride device is directly connected to the primary of the isolation transformer. As the gallium nitride device switches, the isolation transformer converts the DC high voltage level into a low voltage pulsating level through its turns ratio, and then converts it into the low voltage DC level required by the load through the secondary rectification and filtering circuit.
8. The power management circuit according to claim 7, characterized in that: The power management circuit further includes an isolation feedback circuit, and the isolation feedback circuit is connected to the load and the PWM controller respectively.
9. The power management circuit according to claim 7, characterized in that: The rectification and filtering circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4 and a first capacitor C1; The cathode of the first diode D1 is respectively connected to the cathode of the third diode D3 and the first end of the first capacitor C1; the anode of the first diode D1 is connected to the cathode of the second diode D2, and the anode of the third diode D3 is connected to the cathode of the fourth diode D4; the anode of the second diode D2 is respectively connected to the anode of the fourth diode D4 and the second end of the first capacitor C1.