Power module and semiconductor device

Abstract

The utility model discloses a power module and a semiconductor device. The power module comprises a power chip, a first substrate and a second substrate. A first metal layer is arranged on the first substrate, a second metal layer is arranged on the second substrate, the first metal layer and the second metal layer are arranged on the sides, adjacent to each other, of the first substrate and the second substrate respectively in the thickness direction of the power chip, and the power chip is arranged between the first metal layer and the second metal layer. And the power chip is electrically connected with the first metal layer and the second metal layer. According to the power module provided by the utility model, the power module is electrically connected with the metal layer on the adjacent substrate, the structure of the power module is optimized, the thickness of the power module can be obviously reduced, the miniaturization design of the power module can be realized, the utilization rate of space can be increased, and the heat dissipation capability of the power module can be improved because the structure is simpler. And the use requirement of larger current is met.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a power module and a semiconductor device. Background Art

[0002] In the prior art, a power module includes a substrate and a power chip. When the power chip is electrically connected to the metal layer on the substrate, the metal layer on the substrate and the power chip are generally electrically connected through wires. However, connection through wires makes the internal structure of the power module more complicated, affects the assembly efficiency of the power module, and is not conducive to optimizing the volume of the power module. Utility Model Content

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to provide a power module that can simplify the power module structure.

[0004] Another object of the present invention is to provide a semiconductor device including the power module described above.

[0005] According to an embodiment of the first aspect of the present utility model, the power module includes: a power chip, a first substrate, and a second substrate, wherein a first metal layer is provided on the first substrate, and a second metal layer is provided on the second substrate, the first metal layer and the second metal layer are respectively provided on one side of the first substrate and the second substrate adjacent to each other along the thickness direction of the power chip, the power chip is provided between the first metal layer and the second metal layer, and the power chip is electrically connected to the first metal layer and the second metal layer.

[0006] According to the power module of the present invention, by electrically connecting the power module to the metal layer on the adjacent substrate, the structure of the power module is optimized, the thickness of the power module can be significantly reduced, which helps to achieve a miniaturized design of the power module and increase space utilization.

[0007] In some embodiments, the power chip includes: a first chip and a second chip, one side of the first chip is directly electrically connected to the first metal layer, and the other side of the first chip away from the first metal layer is directly electrically connected to the second metal layer; one side of the second chip is directly electrically connected to the second metal layer, and the other side of the second chip away from the second metal layer is directly electrically connected to the first metal layer.

[0008] In some embodiments, the first chip and the second chip both include: a power source, a power drain and a power gate, the power source and the power gate are arranged on one side of the thickness direction of the power chip, and the power drain is arranged on the other side of the thickness direction of the power chip, the power source and the power gate of the first chip are electrically connected to the first metal layer, and the power drain of the first chip is electrically connected to the second metal layer; the power source and the power gate of the second chip are electrically connected to the second metal layer, and the power drain of the second chip is electrically connected to the first metal layer.

[0009] In some embodiments, the first metal layer and the second metal layer both include: a source connection portion, a gate connection portion, and a drain connection portion, the source connection portion of the first metal layer is electrically connected to the power source of the second chip, and the source connection portion of the second metal layer is electrically connected to the power source of the first chip; the gate connection portion of the first metal layer is electrically connected to the power gate of the second chip, and the gate connection portion of the second metal layer is electrically connected to the power gate of the first chip; the drain connection portion of the first metal layer is electrically connected to the power drain of the first chip, and the drain connection portion of the second metal layer is electrically connected to the power drain of the second chip; the source connection portion, the gate connection portion, and the drain connection portion included in the first metal layer and the second metal layer are insulated from each other.

[0010] In some embodiments, at least one insulating trench is formed on each of the first metal layer and the second metal layer, and the insulating trench is provided between the source connecting portion, the gate connecting portion, and the drain connecting portion.

[0011] In some embodiments, the first metal layer includes a first sub-metal layer, a second sub-metal layer and a third sub-metal layer, the power drain of the first chip is electrically connected to the first sub-metal layer; the second sub-metal layer is electrically connected to the power source of the second chip; the third sub-metal layer is electrically connected to the power gate of the second chip, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer are spaced apart along a first direction, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer extend along a second direction, and the first direction is perpendicular to the second direction.

[0012] In some embodiments, there is at least one of the first sub-metal layer, the second sub-metal layer, and the third sub-metal layer, and the at least one first sub-metal layer, the at least one second sub-metal layer, and the at least one third sub-metal layer are alternately arranged along the first direction.

[0013] In some embodiments, a plurality of the third sub-metal layers are connected to each other.

[0014] In some embodiments, the power module further includes: multiple positive DC terminals and multiple negative DC terminals, and the multiple positive DC terminals are electrically connected to the multiple first sub-metal layers respectively; the multiple negative DC terminals are electrically connected to the multiple second sub-metal layers respectively, and the multiple positive DC terminals and the multiple negative DC terminals are alternately arranged along the first direction.

[0015] In some embodiments, the power module further includes: a first control terminal electrically connected to the third sub-metal layer, the first control terminal and the positive DC terminal and the negative DC terminal being arranged at the same end of the power module along the second direction.

[0016] In some embodiments, the second metal layer includes a fourth sub-metal layer, the fourth sub-metal layer includes a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion are connected at one end along the second direction, the first connecting portion and the second connecting portion are spaced apart from each other at the other end along the second direction, a plurality of second chips are spaced apart along the second direction on the first connecting portion and the second connecting portion, and the fourth sub-metal layer is electrically connected to the power drain of the second chip and the power source of the first chip, respectively.

[0017] In some embodiments, the second metal layer further includes: a fifth sub-metal layer, the fifth sub-metal layer and the fourth sub-metal layer are spaced apart along the first direction, one end of the fifth sub-metal layer is arranged between the first connecting portion and the second connecting portion, and the other end of the fifth sub-metal layer is arranged on one side of the fourth sub-metal layer along the first direction, and the fifth sub-metal layer is electrically connected to the power gate of the first chip.

[0018] In some embodiments, the power module further includes: an AC terminal and a second control terminal, wherein the AC terminal is electrically connected to the fourth sub-metal layer along the second direction; the second control terminal is connected to the fifth sub-metal layer, and the second control terminal and the AC terminal are arranged at the same end of the power module along the second direction.

[0019] In some embodiments, it further includes: a first control terminal, the first metal layer is formed with a first avoidance portion, the first avoidance portion is opposite to the second control terminal; the second metal layer is formed with a second avoidance portion, the second avoidance portion is opposite to the first control terminal.

[0020] In some embodiments, the first substrate further includes a third metal layer, which is located on a side of the first substrate away from the first metal layer; the second substrate further includes a fourth metal layer, which is located on a side of the second substrate away from the second metal layer.

[0021] In some embodiments, the first substrate and the second substrate are insulating members.

[0022] In some embodiments, the power module further includes: a mounting plate, the mounting plate being disposed on a side of the third metal layer and the fourth metal layer away from each other, the mounting plate being connected to the third metal layer and the fourth metal layer respectively.

[0023] In some embodiments, the mounting plate is a heat sink.

[0024] In some embodiments, the power module further includes: a plastic package, wherein the plastic package is provided between the first metal layer and the second metal layer.

[0025] The semiconductor device according to the second embodiment of the present invention includes the power module according to any one of the above embodiments.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description and will become apparent from the following description or learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 This is a schematic diagram of multiple power modules assembled together according to an embodiment of the present invention.

[0029] Figure 2 It is a schematic diagram of a power module according to an embodiment of the present utility model.

[0030] Figure 3 It is a partial cross-sectional schematic diagram of a power module according to an embodiment of the present utility model.

[0031] Figure 4 This is a schematic diagram of a first substrate according to an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of a second substrate according to an embodiment of the present invention.

[0033] Figure 6 This is a partially disassembled schematic diagram of a power module according to an embodiment of the present utility model.

[0034] Figure 7 It is a schematic diagram of a plastic sealing component according to an embodiment of the present invention.

[0035] Reference numerals:

[0036] 100. Power module;

[0037] 10. Power chip; 11. Power source; 12. Power gate; 13. Power drain; 14. First chip; 15. Second chip;

[0038] 30, second substrate; 21, first metal layer; 211, first sub-metal layer; 212, second sub-metal layer; 213, third sub-metal layer; 22, third metal layer;

[0039] 20, first substrate; 31, second metal layer; 311, fourth sub-metal layer; 3111, first connecting portion; 3112, second connecting portion; 312, fifth sub-metal layer; 32, fourth metal layer;

[0040] 41. Positive DC terminal; 42. Negative DC terminal; 43. AC terminal;

[0041] 51. First control terminal; 52. Second control terminal;

[0042] 61. Mounting plate; 62. Plastic package. DETAILED DESCRIPTION

[0043] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Figure 1-Figure 7 A power module 100 according to a first aspect of the embodiments of the present invention is described. The power module 100 includes: a power chip 10 , a first substrate 20 , and a second substrate 30 .

[0044] Specifically, if Figure 1-Figure 3 As shown, a first metal layer 21 is provided on the first substrate 20, and a second metal layer 31 is provided on the second substrate 30. The first metal layer 21 and the second metal layer 31 are respectively provided on the sides of the first substrate 20 and the second substrate 30 adjacent to each other along the thickness direction of the power chip 10. The power chip 10 is provided between the first metal layer 21 and the second metal layer 31, and the power chip 10 is electrically connected to the first metal layer 21 and the second metal layer 31.

[0045] In this embodiment, the power module 100 includes a first substrate 20 and a second substrate 30 that are opposite to each other in the thickness direction. A first metal layer 21 and a second metal layer 31 are respectively provided on the adjacent sides of the first substrate 20 and the second substrate 30. The power chip 10 is disposed between the first metal layer 21 and the second metal layer 31, and both sides of the power chip 10 in the thickness direction are electrically connected to the first metal layer 21 and the second metal layer 31. The power chip 10 is welded or sintered to at least one of the first substrate 20 and the second substrate 30. That is, the power chip 10 is electrically connected to one of the first substrate 20 and the second substrate 30 by welding or sintering. In this embodiment, both sides of the power chip 10 in the thickness direction are sintered to the first substrate 20 and the second substrate 30, so that the power chip 10 is electrically connected to the adjacent metal layers to achieve circuit conduction.

[0046] According to the power module 100 of the present invention, by electrically connecting the power module 100 to the metal layer on the adjacent substrate and optimizing the structure of the power module 100, the thickness of the power module 100 can be significantly reduced, which helps to achieve a miniaturized design of the power module 100 and increase space utilization. Moreover, due to the simpler structure, the heat dissipation capacity of the power module 100 can be improved to meet the use requirements of larger currents.

[0047] In some embodiments, as Figure 4 and Figure 5 As shown, the power chip 10 includes: a first chip 14 and a second chip 15. One side of the first chip 14 is directly electrically connected to the first metal layer 21, and the other side of the first chip 14 away from the first metal layer 21 is directly electrically connected to the second metal layer 31; one side of the second chip 15 is directly electrically connected to the second metal layer 31, and the other side of the second chip 15 away from the second metal layer 31 is directly electrically connected to the first metal layer 21.

[0048] That is, in this embodiment, when the first chip 14 and the second chip 15 are electrically connected to the first metal layer 21 and the second metal layer 31, conventional wires are eliminated, and the power chip 10 is directly electrically connected to the metal layers corresponding to the first substrate 20 and the second substrate 30 by welding or sintering, thereby optimizing the internal structure of the power module 100, reducing the height of the power module 100, and facilitating the flow of current between the metal layer on the first substrate 20 and the metal layer on the second substrate 30.

[0049] In some embodiments, as Figure 3-Figure 5As shown, both the first chip 14 and the second chip 15 include a power source 11, a power drain 13, and a power gate 12. The power source 11 and the power gate 12 are located on one side of the power chip 10 in the thickness direction, while the power drain 13 is located on the other side of the power chip 10 in the thickness direction, so that the first chip 14 and the second chip 15 can communicate with the first metal layer 21 and the second metal layer 31. The power source 11 and the power gate 12 of the first chip 14 are electrically connected to the first metal layer 21, and the power drain 13 of the first chip 14 is electrically connected to the second metal layer 31. The power source 11 and the power gate 12 of the second chip 15 are electrically connected to the second metal layer 31, and the power drain 13 of the second chip 15 is electrically connected to the first metal layer 21. In other words, the power chip 10 includes the power source 11 and the power gate 12 located on one side of the thickness direction, and the power drain 13 located on the other side of the thickness direction, wherein the power source 11, the power gate 12, and the power drain 13 are spaced apart.

[0050] When the power chip 10 is electrically connected to the first metal layer 21 and the second metal layer 31, the power source electrode 11 and the power gate electrode 12 on the first chip 14 included in the power chip 10 can be electrically connected to the second metal layer 31 first, and the power source electrode 11 and the power gate electrode 12 on the second chip 15 included in the power chip 10 can be electrically connected to the first metal layer 21, and then the power drain electrode 13 of the first chip 14 is electrically connected to the first metal layer 21, and the power drain electrode 13 of the second chip 15 is electrically connected to the second metal layer 31.

[0051] Therefore, when welding the power chip 10 with the first metal layer 21 and the second metal layer 31, since the size of the power source electrode 11 and the power gate electrode 12 is smaller than that of the power drain electrode 13, the power source electrode 11 and the power gate electrode 12 are welded to the corresponding metal layer first, which can maximize the accuracy and tolerance of the electrical connection. Then welding the power drain electrode 13 to the corresponding metal layer can reduce the requirements for welding accuracy and tolerance, and improve the convenience and efficiency of welding the power chip 10 with the first metal layer 21 and the second metal layer 31.

[0052] In some embodiments, the first metal layer 21 and the second metal layer 31 include: a source connection portion, a gate connection portion, and a drain connection portion. The source connection portion of the first metal layer 21 is electrically connected to the power source 11 of the second chip 15; the source connection portion of the second metal layer 31 is electrically connected to the power source 11 of the first chip 14. The gate connection portion of the first metal layer 21 is electrically connected to the power gate 12 of the second chip 15, and the gate connection portion of the second metal layer 31 is electrically connected to the power gate 12 of the first chip 14. The drain connection portion of the first metal layer 21 is electrically connected to the power drain 13 of the first chip 14, and the drain connection portion of the second metal layer 31 is electrically connected to the power drain 13 of the second chip 15. The source connection portion, gate connection portion, and drain connection portion included in the first metal layer 21 and the second metal layer 31 are insulated from each other.

[0053] Therefore, the source connection part, the gate connection part and the drain connection part corresponding to the power source 11, the power gate 12 and the power drain are respectively provided on the first metal layer 21 and the second metal layer 31, which can facilitate the accurate connection of the power chip 10 with the first metal layer 21 and the second metal layer 31, avoid the short circuit caused by the power source 11 and the power gate 12 being connected to the same position of the same metal layer, avoid the mutual influence between the power source 11, the power gate 12 and the power drain 13, and improve the safety of use.

[0054] In some embodiments, at least one insulating groove is formed on the first metal layer 21 and the second metal layer 31 respectively, and the insulating groove is provided between the source connection part and the gate connection part and the drain connection part. The first metal layer 21 and the second metal layer 31 have the functions of conducting current and heat, and the metal areas of different functional areas need to be etched to form insulating grooves to achieve insulation between the functional areas. Here, when the power chip 10 is set on the first metal layer 21, an insulating groove is provided between the source connection part, the gate connection part and the drain connection part electrically connected to the power chip 10 to achieve insulation. When the power chip 10 is set on the second metal layer 31, an insulating groove is also provided between the source connection part, the gate connection part and the drain connection part electrically connected to the power chip 10 to achieve insulation. Therefore, the design of the insulating groove can cut off the possibility of electrical connection between the source connection part, the gate connection part and the drain connection part through the metal layer, and achieve insulation between the source connection part, the gate connection part and the drain connection part.

[0055] In some embodiments, combined Figure 3, the thickness of the power module 100 is H, and H satisfies: 1.5mm≤H≤10mm. That is, compared with the method of connecting the power chip 10 and the metal layer through a wire in the prior art, the wire binding structure is eliminated in this embodiment to enable direct electrical connection between the power chip 10 and the metal layer, thereby reducing the thickness of the power chip 10, for example, H=3mm. If the thickness of the power chip 10 is less than 1.5mm, the process requirements for the manufacturing process are higher, the processing precision requirements are higher, and the implementation cost is also higher. If the thickness of the power module 100 is greater than 10mm, it may result in a thicker thickness of the power module 100, affecting the miniaturization and integrated design of the power module 100, resulting in higher space requirements, larger consumables and increased costs. Therefore, controlling the thickness of the power module 100 between 1.5mm-10mm can achieve a miniaturized and lightweight design of the power module 100, reduce costs, reduce space utilization, and have good assembly precision.

[0056] In some embodiments, as Figure 4 As shown, the first metal layer 21 includes a first sub-metal layer 211, a second sub-metal layer 212, and a third sub-metal layer 213. The power drain 13 of the first chip 14 is electrically connected to the first sub-metal layer 211, the second sub-metal layer 212 is electrically connected to the power source 11 of the second chip 15, and the third sub-metal layer 213 is electrically connected to the power gate 12 of the second chip 15. The first sub-metal layer 211, the second sub-metal layer 212, and the third sub-metal layer 213 are spaced apart along a first direction A. The first sub-metal layer 211, the second sub-metal layer 212, and the third sub-metal layer 213 all extend along a second direction B. The first direction A and the second direction B are perpendicular.

[0057] In this embodiment, the power source electrode 11 and the power gate electrode 12 of the second chip 15 are electrically connected to the second sub-metal layer 212 and the third sub-metal layer 213 respectively, and an avoidance groove and a protrusion arranged at the edge of the avoidance groove are formed on the third sub-metal layer 213. When the second chip 15 is electrically connected to the second metal layer 31, the power drain electrode 13 of the second chip 15 is electrically connected to the second metal layer 31. When the second chip 15 is electrically connected to the first metal layer 21, in order to avoid the power source electrode 11 and the power gate electrode 12 on the second chip 15 being electrically connected to the same metal layer, an avoidance groove for avoiding the power source electrode 11 and a protrusion for facilitating the electrical connection of the third sub-metal layer 213 and the power gate electrode 12 are provided on the third sub-metal layer 213 electrically connected to the power gate 12.

[0058] Therefore, the arrangement of the second sub-metal layer 212 and the third sub-metal layer 213 facilitates the arrangement of the power source 11 and the power gate 12 of the same power chip 10, effectively avoiding the short circuit caused by the electrical connection between the power source 11 and the power gate 12 and the same metal layer.

[0059] Along the first direction A, the third sub-metal layer 213, the first sub-metal layer 211, and the second sub-metal layer 212 are sequentially spaced apart. There are multiple first chips 14, and these multiple first chips 14 are spaced apart on the first sub-metal layer 211 along the second direction B. The power drain 13 of the first chip 14 is electrically connected to the first sub-metal layer 211. Thus, the arrangement of the first sub-metal layer 211 facilitates current conduction with the second metal layer 31 and the first chip 14, allowing current to flow through the first sub-metal layer 211 to the first chip 14, and then from the power source 11 of the first chip 14 to the second metal layer 31.

[0060] In some embodiments, as Figure 4 As shown, there is at least one first sub-metal layer 211 , second sub-metal layer 212 and third sub-metal layer 213 , and at least one first sub-metal layer 211 , at least one second sub-metal layer 212 and at least one third sub-metal layer 213 are alternately arranged along the first direction A.

[0061] If multiple third sub-metal layers 213 are provided, the multiple third sub-metal layers 213 are connected to each other. One end of each third sub-metal layer 213 is disposed between two adjacent first sub-metal layers 211 and second sub-metal layers 212, and the other end of each third sub-metal layer 213 is disposed at an edge of the first sub-metal layer 211 along the first direction A.

[0062] That is, the third sub-metal layer 213 is spaced apart from the first sub-metal layer 211 and the second sub-metal layer 212 along the first direction A, and the third sub-metal layer 213 has a U-shaped structure, one end of the third sub-metal layer 213 is located between the two adjacent first sub-metal layers 211 and the second sub-metal layer 212 in the middle, and the other end of the third sub-metal layer 213 is located on the side of the first substrate 20 along the first direction A, and the other end of the third sub-metal layer 213 is electrically connected to the first control terminal 51, so that the first control terminal 51 can control the second chip 15 through the third sub-metal layer 213.

[0063] The power module 100 also includes: multiple positive DC terminals 41 and multiple negative DC terminals 42. The multiple positive DC terminals 41 are electrically connected to the multiple first sub-metal layers 211 respectively; the multiple negative DC terminals 42 are electrically connected to the multiple second sub-metal layers 212 respectively. The multiple positive DC terminals 41 and the multiple negative DC terminals 42 are alternately arranged along the first direction A.

[0064] That is, multiple first sub-metal layers 211 and multiple second sub-metal layers 212 are alternately and spaced apart along the first direction A, and multiple positive DC terminals 41 and multiple negative DC terminals 42 are spaced apart along the first direction A. The first sub-metal layers 211 are electrically connected to the positive DC terminals 41, and the second sub-metal layers 212 are electrically connected to the negative DC terminals 42. Thus, the spaced arrangement of the positive DC terminals 41 and the negative DC terminals 42 along the first direction A can offset most stray inductance, reduce the parameters of the power module 100, and thereby reduce the loss and interference of the power module 100. This achieves more uniform heat dissipation of the power chip 10, reduces the temperature of the power chip 10, and improves the current capacity of the power module 100.

[0065] In some embodiments, reference Figure 4 The power module 100 further includes a first control terminal 51, which is electrically connected to the third sub-metal layer 213 and is electrically connected to the third sub-metal layer 213 at an edge of the power module 100 along the first direction A. The first control terminal 51 is disposed at the same end of the power module 100 along the second direction B as the positive DC terminal 41 and the negative DC terminal 42.

[0066] Therefore, the first control terminal 51 , the positive DC terminal 41 , and the negative DC terminal 42 are located at the same end in the second direction B, which facilitates the arrangement of the terminals on the power module 100 and optimizes the structure of the power module 100 .

[0067] In some embodiments, as Figure 5 As shown, the second metal layer 31 includes a fourth sub-metal layer 311, and the fourth sub-metal layer 311 includes a first connecting portion 3111 and a second connecting portion 3112. The first connecting portion 3111 and the second connecting portion 3112 are connected at one end along the second direction B, and the first connecting portion 3111 and the second connecting portion 3112 are spaced apart from each other at the other end along the second direction B. A plurality of second chips 15 are spaced apart along the second direction B on the first connecting portion 3111 and the second connecting portion 3112, and the fourth sub-metal layer 311 is electrically connected to the power drain 13 of the second chip 15 and the power source 11 of the first chip 14, respectively.

[0068] In this embodiment, the first connection portion 3111 and the second connection portion 3112 of the fourth sub-metal layer 311 extend along the second direction B and are connected to each other at one end in the second direction B, that is, the first connection portion 3111 and the second connection portion 3112 are connected to each other at one end of the second substrate 30 away from the first control terminal 51, and a plurality of second chips 15 are provided on the first connection portion 3111 and the second connection portion 3112, and the plurality of second chips 15 are spaced apart on the first connection portion 3111 and the second connection portion 3112 along the second direction B.

[0069] When the first substrate 20 and the second substrate 30 are connected, the multiple first chips 14 electrically connected on the first metal layer 21 and the multiple second chips 15 electrically connected on the second metal layer 31 are staggered along the first direction A to ensure that the power drain electrodes 13 of the second chips 15 are electrically connected to the fourth sub-metal layer 311 provided on the second metal layer 31, and the power source electrodes 11 of the first chips 14 are electrically connected to the fourth sub-metal layer 311. This can thereby increase the heat dissipation capability of the power chips 10 on the second metal layer 31, facilitate electrical connections between the first chips 14 and the second chips 15 and the first metal layer 21 and the second metal layer 31, and help reduce the thickness of the power module 100.

[0070] In some embodiments, as Figure 5 As shown, the second metal layer 31 further includes a fifth sub-metal layer 312, which is spaced apart from the fourth sub-metal layer 311 along the first direction A. One end of the fifth sub-metal layer 312 is located between the first connecting portion 3111 and the second connecting portion 3112, and the other end of the fifth sub-metal layer 312 is located on one side of the fourth sub-metal layer 311 along the first direction A. The fifth sub-metal layer 312 is electrically connected to the power gate 12 of the first chip 14. That is, the fifth sub-metal layer 312 has a U-shaped structure, with one end of the fifth sub-metal layer 312 located between the first connecting portion 3111 and the second connecting portion 3112, and the other end of the fifth sub-metal layer 312 located along the first direction A on the side of the first connecting portion 3111 away from the second connecting portion 3112, or on the side of the second connecting portion 3112 away from the first connecting portion 3111.

[0071] Furthermore, the power module 100 further includes an AC terminal 43 and a second control terminal 52. The AC terminal 43 is electrically connected to the fourth sub-metal layer 311 along the second direction B. The second control terminal 52 is connected to the fifth sub-metal layer 312. The second control terminal 52 and the AC terminal 43 are disposed at the same end of the power module 100 along the second direction B. The AC terminal 43 is electrically connected to the end where the first connecting portion 3111 and the second connecting portion 3112 are connected, and the second control terminal 52 is electrically connected to the fifth sub-metal layer 312, thereby achieving control over the power chip 10.

[0072] Combine Figure 3-Figure 6, current flows into the first sub-metal layer 211 through the positive DC terminal 41, passes through the power drain 13 of the first chip 14, and flows through the first chip 14 to the power source 11 of the first chip 14. Since the power source 11 of the first chip 14 is electrically connected to the fourth sub-metal layer 311, the current passes through the fourth sub-metal layer 311 to the AC terminal 43, and then flows out. Furthermore, if a reverse current is applied, the reverse current flows into the fourth sub-metal layer 311 through the AC terminal 43, passes through the power drain 13 of the second chip 15, and enters the power source 11 of the second chip 15. Since the power source 11 of the second chip 15 is electrically connected to the second sub-metal layer 212 of the first metal layer 21, it enters the first metal layer 21 and flows out through the negative DC terminal 42. The current of the second chip 15 disposed on the first connecting portion 3111 and the second chip 15 disposed on the second connecting portion 3112 respectively flows into the second sub-metal layer 212 of the first metal layer 21 and flows out through the corresponding negative DC terminal 42.

[0073] In some embodiments, the first metal layer 21 is formed with a first avoidance portion, which is opposite to the second control terminal 52; and the second metal layer 31 is formed with a second avoidance portion, which is opposite to the first control terminal 51. That is, when the first substrate 20 and the second substrate 30 are connected, the first avoidance portion of the first metal layer 21 provided on the first substrate 20 is opposite to the second control terminal 52 provided on the second substrate 30, thereby preventing the second control terminal 52 from being electrically connected to the first metal layer 21. The second avoidance portion of the second metal layer 31 provided on the second substrate 30 is opposite to the first control terminal 51 provided on the first substrate 20, thereby preventing the first control terminal 51 from being electrically connected to the second metal layer 31.

[0074] Therefore, the setting of the first avoidance portion and the second avoidance portion can ensure the electrical connection between the first control terminal 51 and the first metal layer 21, and the electrical connection between the second control terminal 52 and the second metal layer 31, thereby increasing the performance of the power terminal when the first substrate 20 and the second substrate 30 are merged, thereby increasing the safety of use.

[0075] In some embodiments, as Figure 3 As shown, the first substrate 20 is further provided with a third metal layer 22, which is disposed on a side of the first substrate 20 away from the first metal layer 21; the second substrate 30 is further provided with a fourth metal layer 32, which is disposed on a side of the second substrate 30 away from the second metal layer 31. That is, the first metal layer 21 and the third metal layer 22 are respectively disposed on both sides of the first substrate 20, and the second metal layer 31 and the fourth metal layer 32 are respectively disposed on both sides of the second substrate 30. The first metal layer 21 and the second metal layer 31 are adjacent to each other. After the first substrate 20 and the second substrate 30 are combined, they can be electrically connected to external components by welding the third metal layer 22 and the fourth metal layer 32.

[0076] Optionally, the first substrate 20 and the second substrate 30 are insulating members, thereby preventing the metal layers disposed on both sides of the substrates from contacting each other and causing a short circuit, thereby increasing the safety of the power module 100 .

[0077] The minimum gap between the first substrate 20 and the second substrate 30 may be 0 to 0.5 mm.

[0078] In some embodiments, as Figure 1 As shown, the power module 100 further includes a mounting plate 61, which is disposed on a side of the third metal layer 22 and the fourth metal layer 32 that is away from each other. The mounting plate 61 is connected to the third metal layer 22 and the fourth metal layer 32, respectively. For example, there may be multiple mounting plates 61, each of which is connected to the third metal layer 22 and the fourth metal layer 32, for mounting the first substrate 20 and the second substrate 30.

[0079] Optionally, the mounting plate 61 is a heat sink. For example, a heat exchange channel may be provided within the mounting plate 61, which can be connected to an external heat exchange system to dissipate heat from the power module 100. The mounting plate 61 can be connected to the third metal layer 22 and the fourth metal layer 32 through welding, sintering, or thermal grease to form a single product.

[0080] In some embodiments, combined Figure 7 The power module 100 further includes a plastic encapsulation member 62 disposed between the first metal layer 21 and the second metal layer 31. Specifically, after the first substrate 20 and the second substrate 30 are combined, the plastic encapsulation member 62 is filled between the first substrate 20 and the second substrate 30. The plastic encapsulation member 62 completely fills the gap between the first metal layer 21 and the second metal layer 31 of the entire power module 100, thereby ensuring insulation between the various components within the power module 100. This can effectively reduce thermal resistance, reduce the number of process steps, and improve production efficiency.

[0081] A semiconductor device according to an embodiment of the second aspect of the present invention includes the power module 100 according to any one of the above embodiments.

[0082] According to the semiconductor device of the embodiment of the present invention, including the above-mentioned one or more power modules 100, the current is directly conducted between the power chip 10 and the metal layer without passing through other conductive materials, which can reduce the volume of the semiconductor device, making the semiconductor device more miniaturized and thinner, improving the heat dissipation capacity of the semiconductor device, eliminating the wire bonding process, and reducing the structure of the semiconductor device, so that the semiconductor device has good production efficiency.

[0083] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation to the present invention.

[0084] In the description of the present invention, "first feature" and "second feature" may include one or more of the features. In the description of the present invention, "plurality" means two or more. In the description of the present invention, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may also include the first and second features not being in direct contact but being in contact via another feature between them. In the description of the present invention, the first feature being "above", "above" and "above" the second feature includes the first feature being directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature.

[0085] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0086] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and purpose of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A power module, characterized in that: include: Power chip; a first substrate, wherein a first metal layer is provided on the first substrate; as well as A second substrate, a second metal layer is provided on the second substrate, the first metal layer and the second metal layer are respectively provided on one side of the first substrate and the second substrate adjacent to each other along the thickness direction of the power chip, the power chip is provided between the first metal layer and the second metal layer, and the power chip is electrically connected to the first metal layer and the second metal layer.

2. The power module according to claim 1, characterized in that: The power chip comprises: a first chip, wherein one side of the first chip is directly electrically connected to the first metal layer, and the other side of the first chip away from the first metal layer is directly electrically connected to the second metal layer; A second chip, one side of the second chip is directly electrically connected to the second metal layer, and the other side of the second chip away from the second metal layer is directly electrically connected to the first metal layer.

3. The power module according to claim 2, characterized in that: The first chip and the second chip both include: A power source, a power drain and a power gate, wherein the power source and the power gate are arranged on one side of the power chip in the thickness direction, and the power drain is arranged on the other side of the power chip in the thickness direction, the power source and the power gate of the first chip are electrically connected to the first metal layer, and the power drain of the first chip is electrically connected to the second metal layer; A power source electrode and a power gate electrode of the second chip are electrically connected to the second metal layer, and a power drain electrode of the second chip is electrically connected to the first metal layer.

4. The power module according to claim 3, characterized in that: The first metal layer and the second metal layer both include: a source connection portion, wherein the source connection portion of the first metal layer is electrically connected to the power source of the second chip, and the source connection portion of the second metal layer is electrically connected to the power source of the first chip; a gate connection portion, wherein the gate connection portion of the first metal layer is electrically connected to the power gate of the second chip, and the gate connection portion of the second metal layer is electrically connected to the power gate of the first chip; a drain connection portion, wherein the drain connection portion of the first metal layer is electrically connected to the power drain of the first chip, and the drain connection portion of the second metal layer is electrically connected to the power drain of the second chip; The source connecting portion, the gate connecting portion, and the drain connecting portion included in the first metal layer and the second metal layer are insulated from each other.

5. The power module according to claim 4, characterized in that: At least one insulating groove is formed on the first metal layer and the second metal layer respectively, and the insulating groove is arranged between the source connecting part, the gate connecting part and the drain connecting part.

6. The power module according to claim 4, characterized in that: The first metal layer comprises: a first sub-metal layer, the power drain of the first chip being electrically connected to the first sub-metal layer; a second sub-metal layer, the second sub-metal layer being electrically connected to a power source electrode of the second chip; A third sub-metal layer, wherein the third sub-metal layer is electrically connected to the power gate of the second chip, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer are spaced apart along a first direction, the first sub-metal layer, the second sub-metal layer and the third sub-metal layer extend along a second direction, and the first direction is perpendicular to the second direction.

7. The power module according to claim 6, characterized in that: There is at least one of the first sub-metal layer, the second sub-metal layer and the third sub-metal layer, and the at least one first sub-metal layer, the at least one second sub-metal layer and the at least one third sub-metal layer are alternately arranged along the first direction.

8. The power module according to claim 7, characterized in that: The plurality of third sub-metal layers are connected to each other.

9. The power module according to claim 7, characterized in that: The power module further comprises: A plurality of positive DC terminals, wherein the plurality of positive DC terminals are electrically connected to the plurality of first sub-metal layers respectively; A plurality of negative DC terminals are electrically connected to the plurality of second sub-metal layers respectively, and the plurality of positive DC terminals and the plurality of negative DC terminals are alternately arranged along the first direction.

10. The power module according to claim 9, characterized in that: Also includes: A first control terminal, wherein the first control terminal is electrically connected to the third sub-metal layer, and the first control terminal, the positive DC terminal, and the negative DC terminal are arranged at the same end of the power module along the second direction.

11. The power module according to claim 6, characterized in that: The second metal layer comprises: A fourth sub-metal layer, the fourth sub-metal layer includes a first connecting portion and a second connecting portion, the first connecting portion and the second connecting portion are connected at one end along the second direction, the first connecting portion and the second connecting portion are spaced apart from each other at the other end along the second direction, a plurality of second chips are spaced apart on the first connecting portion and the second connecting portion along the second direction, and the fourth sub-metal layer is electrically connected to the power drain of the second chip and the power source of the first chip respectively.

12. The power module according to claim 11, characterized in that: The second metal layer further includes: A fifth sub-metal layer, wherein the fifth sub-metal layer and the fourth sub-metal layer are spaced apart along the first direction, one end of the fifth sub-metal layer is disposed between the first connecting portion and the second connecting portion, the other end of the fifth sub-metal layer is disposed on one side of the fourth sub-metal layer along the first direction, and the fifth sub-metal layer is electrically connected to the power gate of the first chip.

13. The power module according to claim 12, characterized in that: The power module further comprises: an AC terminal, the AC terminal being electrically connected to the fourth sub-metal layer along the second direction; A second control terminal, wherein the second control terminal is connected to the fifth sub-metal layer, and the second control terminal and the AC terminal are arranged at the same end of the power module along the second direction.

14. The power module according to claim 13, characterized in that: Also includes: The first control terminal, The first metal layer is formed with a first avoidance portion, and the first avoidance portion is opposite to the second control terminal; The second metal layer is formed with a second avoidance portion, and the second avoidance portion is opposite to the first control terminal.

15. The power module according to claim 1, characterized in that: The first substrate is further provided with a third metal layer, and the third metal layer is provided on a side of the first substrate away from the first metal layer; The second substrate is further provided with a fourth metal layer, and the fourth metal layer is provided on a side of the second substrate away from the second metal layer.

16. The power module according to claim 15, characterized in that: The first substrate and the second substrate are insulating members.

17. The power module according to claim 15, characterized in that: Also includes: A mounting plate is provided on a side where the third metal layer and the fourth metal layer are away from each other, and the mounting plate is connected to the third metal layer and the fourth metal layer respectively.

18. The power module according to claim 17, characterized in that: The mounting plate is a heat sink.

19. The power module according to any one of claims 1 to 18, characterized in that: Also includes: A plastic packaging component is arranged between the first metal layer and the second metal layer.

20. A semiconductor device, characterized in that: Comprising a power module according to any one of claims 1-19.

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