Optical sensor integrated with CMOS circuit and avalanche diode
By growing germanium films in silicon-based CMOS processes and integrating avalanche diodes, the problem of insufficient infrared wavelength detection capabilities of existing SPAD array sensors is solved, and the expansion of infrared wavelength range and performance improvement is achieved.
Patent Information
- Application Number
- CN202421317900.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-11
- Publication Date
- 2025-03-11
- Estimated Expiration
- 2034-06-11
AI Technical Summary
Existing SPAD array sensors have limitations in infrared wavelengths, especially the poor infrared perception performance of silicon materials, which cannot effectively detect optical signals with infrared wavelengths exceeding 910nm.
The light sensor using integrated CMOS circuit and avalanche diode is used to grow a germanium film based on silicon-based CMOS process, and the infrared light absorption characteristics of germanium materials are used to expand the detection range of infrared wavelengths to 1800nm.
The infrared wavelength range is expanded, the performance of SPAD array sensors is improved, the complexity and high cost of dual-chip stacked packaging is avoided, and the yield and reliability are improved.
Smart Images
Figure CN222602919U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of optical sensors, in particular to an optical sensor integrating a CMOS circuit and an avalanche diode. Background Art
[0002] As artificial intelligence is widely used in various fields, photoelectric conversion devices, as important sensors, are also gaining more and more attention. SPAD (single photon avalanche diode) arrays can be widely used in fields such as homeland security, aerial mapping, lidar, time-of-flight sensing, security monitoring, biomedical imaging, etc., which require detection and imaging under extremely weak light intensity.
[0003] The SPAD array sensor mainly includes an avalanche diode, a bias circuit, a quenching circuit, and a readout circuit to form a complete sensor function. The existing SPAD array sensors are mainly divided into two categories:
[0004] 1. A SPAD array sensor is formed by stacking and packaging an avalanche diode 10 made of III-V materials and an auxiliary circuit 20 (including bias circuit, quenching circuit, and readout circuit) implemented by a silicon-based CMOS process, such as Figure 1 This type of SPAD array sensor has good functional parameters, but is difficult to process, has high cost, and has a low yield rate.
[0005] 2. Avalanche diodes 30 are directly manufactured based on silicon-based CMOS technology, and avalanche diode arrays are directly manufactured on silicon-based CMOS auxiliary circuits 40. The two are directly connected through lines 50, so that all sensor functions can be completed on one chip, such as Figure 2 This type of SPAD array sensor is easy to process and has low cost, but SPAD uses silicon material and has poor infrared sensing performance, especially when used in infrared lidar detection. Due to the limitation of silicon material to infrared wavelength, the maximum infrared wavelength can only reach 910nm, which greatly limits its application. Utility Model Content
[0006] In order to solve at least some of the above problems in the prior art, the utility model provides a light sensor integrating a CMOS circuit and an avalanche diode, comprising:
[0007] An avalanche diode comprising:
[0008] an avalanche diode doped region located in the substrate;
[0009] A SPAD first electrode, which is located on the upper surface of the avalanche diode doping region;
[0010] an avalanche region film located on the avalanche diode doped region; and
[0011] The SPAD second electrode is located on the upper surface of the avalanche region film;
[0012] a CMOS transistor circuit arranged in parallel with the avalanche diode; and
[0013] A first interconnect structure is electrically connected to the avalanche diode and the CMOS transistor circuit.
[0014] Furthermore, the avalanche zone film is an N-type germanium film, a P-type germanium film, an intrinsic germanium film, an N-type germanium silicon film, a P-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, a P-type GaAs film, an N-type InGaAsP film or a P-type InGaAsP film.
[0015] Further, the SPAD first electrode is the SPAD cathode, and the SPAD second electrode is the SPAD anode; or
[0016] The SPAD first electrode is the SPAD anode, and the SPAD second electrode is the SPAD cathode.
[0017] Furthermore, the avalanche diode doping region is an N-type ion doping region or a P-type ion doping region.
[0018] Furthermore, the SPAD second electrode is partially exposed.
[0019] Furthermore, the CMOS transistor circuit comprises:
[0020] A PMOS transistor circuit comprising:
[0021] A first doped region, which is located in the substrate and is located in the same plane as the avalanche diode doped region;
[0022] A first active region, which is located on an upper surface of the first doped region;
[0023] A second active region located on an upper surface of the first doped region; and
[0024] a gate located above the first doped region; and
[0025] An NMOS transistor circuit comprising:
[0026] A second doped region, which is located in the substrate and is located in the same plane as the avalanche diode doped region;
[0027] A first active region, which is located on an upper surface of the second doped region;
[0028] A second active region located on an upper surface of the second doped region; and
[0029] A gate is located above the second doped region.
[0030] Further, the first interconnect structure comprises:
[0031] A first conductive member electrically connected to the SPAD first electrode, the SPAD second electrode, the first active region, the second active region and the gate of the PMOS transistor circuit and the NMOS transistor circuit;
[0032] A first metal wire is electrically connected to the first conductive member.
[0033] Furthermore, it also includes:
[0034] an oxide layer, which is located on the substrate and wraps the gate;
[0035] The dielectric layer is located on the oxide layer and wraps the first conductive member.
[0036] Furthermore, it also includes:
[0037] a second interconnect structure electrically connected to the first interconnect structure, the second interconnect structure comprising a second conductive member and a second metal line;
[0038] The insulating layer is located on the dielectric layer and wraps the first metal wire and the second conductive member.
[0039] Furthermore, the second metal wire is located on the insulating layer.
[0040] The utility model has at least the following beneficial effects:
[0041] (1) The optical sensor of the utility model integrates an avalanche diode and a CMOS circuit, which are arranged in parallel. The avalanche diode is manufactured without affecting the CMOS process, so that all the functions of the sensor can be completed on one chip. (2) A germanium film is used in the avalanche diode. The physical property of germanium material that absorbs infrared light better than silicon is utilized. Its infrared wavelength can be extended to 1800nm, which is greatly improved in performance compared with the all-silicon-based SPAD, especially the applicable range of infrared wavelengths is greatly expanded. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.
[0043] Figure 1A schematic diagram of the structure of a sensor with an existing avalanche diode and a CMOS auxiliary circuit stack is shown;
[0044] Figure 2 The schematic diagram of the structure of the sensor in which the existing avalanche diode array is directly fabricated on the silicon-based CMOS auxiliary circuit is shown;
[0045] Figures 3 to 18 A cross-sectional schematic diagram showing a process of forming an optical sensor integrating a CMOS circuit and an avalanche diode according to an embodiment of the present invention; and
[0046] Fig.19 A cross-sectional schematic diagram of an optical sensor integrating a CMOS circuit and an avalanche diode according to an embodiment of the utility model is shown. DETAILED DESCRIPTION
[0047] It should be noted that various components in the various drawings may be shown exaggeratedly for illustrative purposes and are not necessarily correct to scale.
[0048] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be understood as limiting.
[0049] In the present invention, unless otherwise specified, the quantifiers "a", "an" and "an" do not exclude the presence of multiple elements.
[0050] It should also be pointed out that in the embodiments of the present invention, for the sake of clarity and simplicity, only a portion of the parts or components may be shown, but a person of ordinary skill in the art will understand that, under the guidance of the present invention, required parts or components may be added according to the needs of specific scenarios.
[0051] It should also be pointed out that within the scope of the present invention, the terms "same", "equal", "equal to" and the like do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".
[0052] It should also be pointed out that in the description of the present invention, the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than explicitly or implicitly indicating that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as explicitly or implicitly indicating relative importance.
[0053] In addition, the embodiments of the present invention describe the process steps in a specific order, but this is only for the convenience of distinguishing the steps, and does not limit the order of the steps. In different embodiments of the present invention, the order of the steps can be adjusted according to the adjustment of the process.
[0054] In the present invention, the N-type doping element includes arsenic, phosphorus or antimony; the P-type doping element includes boron, gallium or indium.
[0055] Figures 3 to 18 A cross-sectional schematic diagram shows a process of forming an optical sensor integrating a CMOS circuit and an avalanche diode according to an embodiment of the utility model.
[0056] The steps to form a light sensor integrating CMOS circuit and avalanche diode include:
[0057] Step 1, such as Figure 3 and Figure 4 As shown, a first doping region 102 and an avalanche diode doping region 103 are formed in a substrate 101 .
[0058] A photoresist is coated on the surface of the substrate 101, and after exposure and development, a doping region pattern is obtained to expose the substrate, and then the exposed substrate 101 is subjected to N-type ion implantation to form the first doping region 102 and the avalanche diode doping region 103, and finally the photoresist is removed. The substrate 101 is a P-type silicon substrate, and can also be an N-type silicon substrate.
[0059] Step 2, such as Figure 5 As shown, a second doping region 104 is formed in the substrate 101. Photoresist is coated on the surface of the substrate 101, and after exposure and development, a doping region pattern is obtained to expose the substrate, and then P-type ions are implanted into the exposed substrate 101 to form the second doping region 104, and finally the photoresist is removed.
[0060] Step 3, such as Figure 6 As shown, a gate oxide layer 105 and a polysilicon layer 106 are sequentially grown on a substrate 101. The gate oxide layer 109 covers the first doping region 102, the avalanche diode doping region 103 and the second doping region 104.
[0061] Step 4, such as Figure 7 and 8 As shown, photoresist is coated on the surface of polysilicon 106, and after exposure and development, a gate pattern 107 is obtained, and then the exposed polysilicon layer 106 and gate oxide layer 105 are etched to form a gate structure, and finally, the photoresist is removed. The gate structure includes a gate oxide layer below and a gate 108 above.
[0062] Step 5, such as Fig. 9As shown, a first active region 110 is formed on the upper surface of the first doping region 102 and the second doping region 104, and a SPAD first electrode 111 is formed on the upper surface of the avalanche diode doping region 103. Specifically, an oxide layer 109 is grown on the substrate 101, and then a photoresist is coated on the oxide layer 109. After exposure and development, a portion of the photoresist located above the first doping region 102, the second doping region 104 and the avalanche diode doping region 103 is removed to expose the oxide layer; the oxide layer 109 is etched to expose the first doping region 102, the second doping region 104 and the avalanche diode doping region 103, and N+ ion implantation is performed to form the first active region 110 and the SPAD first electrode 111. Since the N+ ions are implanted, the SPAD first electrode 111 is the negative electrode of the SPAD, and the first active region 110 is an N active region.
[0063] Step 6, such as Fig.10 As shown, an avalanche region film 112 is formed on the SPAD first electrode 111. Specifically, a photoresist is coated on the oxide layer 109, the SPAD first electrode 111 and the first active region 110, and after exposure and development, a portion of the photoresist on the SPAD first electrode 111 is removed, and an avalanche region film is deposited and grown, and the excess germanium layer is removed by reverse etching, and finally the photoresist is removed. In one embodiment of the utility model, the avalanche region film 106 is an avalanche region film 204, which is an N-type germanium film or an intrinsic germanium film. The germanium film is used as the SPAD avalanche region, and the thickness is 2-6um to meet the bias voltage of 10V-100V.
[0064] The avalanche region film can also be an N-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, an N-type InGaAsP film, or the like.
[0065] Step 7, such as Fig.11 and 12 As shown, a SPAD second electrode 113 is formed on the upper surface of the avalanche region film 112 , and a second active region 114 is formed on the upper surfaces of the first doping region 102 and the second doping region 104 .
[0066] A photoresist is arranged on the oxide layer 109, the avalanche region film 112, the first doping region 102 and the second doping region 104, and is exposed and developed. Part of the photoresist located above the first doping region 102 and the second doping region 104 is removed to expose the oxide layer 109, and the exposed oxide layer 109 is etched to expose the first doping region 102 and the second doping region 104; the photoresist is exposed and developed again to remove the photoresist located on the avalanche region film 112; P+ ion implantation is performed on the exposed avalanche region film 112, the first doping region 102 and the second doping region 104 to obtain the SPAD second electrode 113 and the second active region 114, and finally the photoresist is removed. The SPAD second electrode 113 is the SPAD positive electrode. The second active region 114 is a P active region.
[0067] Step 8, such as Figures 13 to 15 As shown, a dielectric layer 115 is formed on the oxide layer 109 , a first conductive member 116 is formed in the dielectric layer 115 , and a first metal wire 117 is formed on the surface of the dielectric layer 115 , electrically connecting the gate 108 , the SPAD first electrode 111 , the SPAD second electrode 113 , the first active region 110 , and the second active region 114 .
[0068] The dielectric layer 115 covers the avalanche region film 112 , the SPAD first electrode 111 , the SPAD second electrode 113 , the first active region 110 and the second active region 114 .
[0069] A photoresist is arranged on the surface of the dielectric layer 115, and after exposure and development, a hole pattern is formed above the SPAD first electrode 111, the SPAD second electrode 113, the first active area 110 and the second active area 114, and then the dielectric layer 115 is etched according to the hole pattern to form a blind hole. The photoresist is patterned again to remove the photoresist located above the gate 108, and then the dielectric layer 115 and the oxide layer 109 are etched to form a blind hole to expose the gate.
[0070] The first conductive member 116 is obtained by filling the blind hole with metal through a hole filling, sputtering or evaporation process, and a metal layer is arranged on the surface of the dielectric layer 116, and then a photoresist is coated and patterned by exposure and development, and the metal layer not covered by the photoresist is etched to form a first metal line 117. The first conductive member 116 is electrically connected to the first metal line 117, the SPAD first electrode 111, the SPAD second electrode 113, the first active area 110 and the second active area 114.
[0071] Step 9, such as Fig.16 and 17 As shown, an insulating layer 118 is formed on the dielectric layer 115 , a second conductive member 119 is formed in the insulating layer 118 , and a second metal wire 120 is formed on the surface of the insulating layer 118 to electrically connect to the first metal wire 117 .
[0072] The insulating layer 118 covers the dielectric layer 115 and the first metal line 117, and a photoresist is arranged on the surface of the insulating layer 118. After exposure and development, a hole pattern is formed above the first metal line 117, and then the insulating layer 118 is etched according to the hole pattern to form a blind hole. The second conductive member 119 is obtained by filling the blind hole with metal through a hole filling, sputtering or evaporation process, and a metal layer is arranged on the surface of the insulating layer 118, and then a photoresist is coated and patterned by exposure and development. The metal layer not covered by the photoresist is etched to form a second metal line 120.
[0073] Step 10, such as Fig.18 As shown, the insulating layer 118 and the dielectric layer 115 are etched to expose the SPAD second electrode 113 .
[0074] Photoresist is arranged on the surface of the insulating layer 118, and exposure and development are performed to remove a portion of the photoresist located above the SPAD second electrode 113, exposing the insulating layer 118 above the SPAD second electrode 113, and then the exposed insulating layer 118 and the dielectric layer 115 are etched in sequence to expose the SPAD second electrode 113.
[0075] In another embodiment of the present invention:
[0076] In step 1, P-type ion implantation is performed on the exposed substrate to form a first doping region and an avalanche diode doping region.
[0077] In step 2, N-type ion implantation is performed on the exposed substrate to form a second doped region.
[0078] Step 5: Etch the oxide layer to expose the first doping region, the second doping region and the avalanche diode doping region, and perform P+ ion implantation to form the first active region and the SPAD first electrode. The P+ ion implantation forms the SPAD positive electrode.
[0079] Step 7, forming a SPAD second electrode on the upper surface of the avalanche region film, and forming a second active region on the upper surfaces of the first doping region and the second doping region. Etching the exposed oxide layer 109 to expose the first doping region and the second doping region; exposing and developing the photoresist again to remove the photoresist on the avalanche region film; performing N+ ion implantation on the exposed avalanche region film, the first doping region and the second doping region to obtain the SPAD second electrode and the second active region, and finally removing the photoresist. The SPAD second electrode is the SPAD cathode. The second active region is the N active region.
[0080] In one embodiment of the present invention, the avalanche region film 106 is a P-type germanium film, and the avalanche region film 204 is an intrinsic germanium film, a P-type germanium silicon film, an intrinsic germanium silicon film, a P-type GaAs film, a P-type InGaAsP film, etc.
[0081] Fig.19 A cross-sectional schematic diagram of an optical sensor integrating a CMOS circuit and an avalanche diode according to an embodiment of the utility model is shown.
[0082] like Fig.18 As shown, the optical sensor integrating CMOS circuit and avalanche diode includes an avalanche diode, a CMOS transistor circuit and a first interconnection structure. The avalanche diode and the CMOS transistor circuit are arranged in parallel on the substrate 201, and the two are electrically connected through the interconnection structure.
[0083] The avalanche diode includes an avalanche diode doping region 202 , a SPAD first electrode 203 , an avalanche region film 204 , and a SPAD second electrode 205 .
[0084] The avalanche diode doping region 202 is located in the substrate 201. In one embodiment of the present invention, the substrate 201 is a P-type silicon substrate, or an N-type silicon substrate. The avalanche diode doping region 202 can be an N-type ion doping region or a P-type ion doping region.
[0085] The SPAD first electrode 203 is located on the upper surface of the avalanche diode doping region 202. The SPAD first electrode 203 can be the SPAD cathode, formed by N+ ion implantation into the surface of the avalanche diode doping region. The SPAD first electrode 203 can also be the SPAD anode, formed by P+ ion implantation into the surface of the avalanche diode doping region.
[0086] The avalanche region film 204 is located on the avalanche diode doping region 202. The avalanche region film 204 is an N-type germanium film. The N-type germanium film is used as the SPAD avalanche region, and has a thickness of 2-6 um to meet the bias voltage of 10V-100V.
[0087] The avalanche zone film can also be an intrinsic germanium film, an N-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, an N-type InGaAsP film, a P-type germanium film, a P-type germanium silicon film, an intrinsic germanium silicon film, a P-type GaAs film or a P-type InGaAsP film, etc.
[0088] The SPAD second electrode 205 is located on the upper surface of the avalanche region film 204. The SPAD second electrode 205 can be a SPAD positive electrode, formed by P+ ion implantation into the surface of the avalanche diode doping region. The SPAD second electrode 205 can also be a SPAD negative electrode, formed by N+ ion implantation into the surface of the avalanche diode doping region. The SPAD second electrode 205 is partially exposed and not covered.
[0089] The SPAD first electrode 203 and the SPAD second electrode 205 constitute the positive and negative electrodes of the SPAD.
[0090] CMOS transistor circuits include PMOS transistor circuits and NMOS transistor circuits.
[0091] The PMOS transistor circuit includes a first doped region 206, a first active region 207, a second active region 208, and a gate 212 above the first doped region 206. The first doped region 206 is an N well, the first active region 207 is an N active region, and the second active region 208 is a P active region.
[0092] The first doped region 206 is located in the substrate 201 and is in the same plane as the avalanche diode doped region 202 .
[0093] The NMOS transistor circuit includes a second doped region 209, a first active region 210, a second active region 211, and a gate 213 located above the second doped region 209. The second doped region 209 is a P well, the first active region 210 is an N active region, and the second active region 211 is a P active region.
[0094] The second doped region 209 is located in the substrate 201 and is in the same plane as the avalanche diode doped region 202 .
[0095] The first interconnection structure electrically connects the SPAD first electrode 203 , the SPAD second electrode 205 , the first active region 207 , the second active region 208 , the first active region 210 , the second active region 211 , the gate 212 and the gate 213 . The first interconnection structure includes a first conductive member 214 and a first metal line 215 .
[0096] The above-mentioned optical sensor including CMOS circuit and avalanche diode further includes:
[0097] The oxide layer 216 is located on the substrate 201 and wraps around the gate.
[0098] The dielectric layer 217 is located on the oxide layer 216 and wraps the first conductive member 214. The first metal line 215 is located on the dielectric layer 217.
[0099] The second interconnect structure is electrically connected to the first interconnect structure, and the second interconnect structure includes a second conductive member 218 and a second metal line 219 .
[0100] The insulating layer 220 is located on the dielectric layer 217 and wraps the first metal wire 215 and the second conductive member 218. The second metal wire 219 is located on the insulating layer 220.
[0101] also, Fig.19 The CMOS transistor circuit and SPAD are illustrated in terms of unit number only, but an actual photosensor includes a plurality of SPADs arranged in an array and a plurality of CMOS transistor circuits, and a plurality of CMOS transistor circuits are combined to drive the SPAD.
[0102] The utility model has the following beneficial effects:
[0103] The utility model adopts silicon-based CMOS technology and grows germanium thin film on the basis of silicon material, uses the characteristics of germanium to produce avalanche diodes, and connects with auxiliary circuits realized by silicon-based CMOS technology in the same plane to achieve all the functions of the sensor on one chip. Since the sensor adopts germanium material, its infrared wavelength can be extended to 1800nm, which greatly expands the application range of SPAD array sensors, while avoiding the use of dual-chip stacking packaging, which greatly improves the yield rate and reliability and reduces the cost.
[0104] If you want to use the physical properties of Ge to make a SPAD array, a simple method is to selectively grow a Ge film directly outside the silicon-based CMOS, but this method has great limitations in the application field:
[0105] 1) The thickness of the Ge film grown by this method is limited. Since SPAD works in the avalanche breakdown region, a thicker film is required to ensure a wider barrier region to ensure that the diode is in an avalanche breakdown state rather than other breakdowns. Therefore, the thickness of this film will be between 2um and 6um. A film of this thickness directly protrudes from the surface of the silicon wafer, forming a large step on the device, which is not conducive to metal wiring, especially multi-layer wiring of CMOS process below 0.25um will be difficult to implement.
[0106] 2) In the CMOS process with a thickness less than 0.25um, the junction depth of the device is relatively shallow. If the Ge film is grown later, it usually needs to go through multiple high temperatures above 800°C, which will affect the process parameters that have been completed in the CMOS process. It is even impossible to manufacture CMOS devices with fine lines.
[0107] The utility model integrates an avalanche diode and a CMOS circuit, and manufactures the avalanche diode and the CMOS circuit at the same time through the same process. The silicon-based CMOS process is adopted and a germanium thin film is grown on the basis of silicon material. The avalanche diode is manufactured by utilizing the characteristics of germanium, and is connected with the silicon-based CMOS circuit to realize all the functions of the sensor on one chip. The optical sensor formation method of the utility model can avoid the defects of the method of selectively growing Ge thin film directly outside the silicon-based CMOS. Since the sensor adopts germanium material, its infrared wavelength can be extended to 1800nm, which greatly expands the application range of SPAD array sensors, and avoids the use of dual-chip stacking packaging, which greatly improves the yield rate, reduces the processing difficulty, and greatly reduces the cost.
[0108] Although some embodiments of the present invention have been described in this application document, it will be understood by those skilled in the art that these embodiments are only shown as examples. Under the guidance of the present invention, those skilled in the art can think of numerous variations, alternatives and improvements without exceeding the scope of the present invention. The attached claims are intended to define the scope of the present invention and thereby cover methods and structures within the scope of these claims themselves and their equivalents.
Claims
1. An optical sensor integrating CMOS circuit and avalanche diode, characterized in that: include: An avalanche diode comprising: an avalanche diode doped region located in the substrate; A SPAD first electrode, which is located on the upper surface of the avalanche diode doping region; an avalanche region film located on the avalanche diode doped region; and The SPAD second electrode is located on the upper surface of the avalanche region film; a CMOS transistor circuit arranged in parallel with the avalanche diode; and A first interconnect structure is electrically connected to the avalanche diode and the CMOS transistor circuit.
2. The optical sensor according to claim 1, characterized in that The avalanche zone film is an N-type germanium film, a P-type germanium film, an intrinsic germanium film, an N-type germanium silicon film, a P-type germanium silicon film, an intrinsic germanium silicon film, an N-type GaAs film, a P-type GaAs film, an N-type InGaAsP film or a P-type InGaAsP film.
3. The optical sensor according to claim 1, characterized in that The SPAD first electrode is the SPAD cathode, and the SPAD second electrode is the SPAD anode; or The SPAD first electrode is the SPAD anode, and the SPAD second electrode is the SPAD cathode.
4. The optical sensor according to claim 1, characterized in that The avalanche diode doping region is an N-type ion doping region or a P-type ion doping region.
5. The optical sensor according to claim 1, characterized in that The SPAD second electrode is partially exposed.
6. The optical sensor according to claim 1, characterized in that The CMOS transistor circuit comprises: A PMOS transistor circuit comprising: A first doped region, which is located in the substrate and is located in the same plane as the avalanche diode doped region; A first active region, which is located on an upper surface of the first doped region; A second active region located on an upper surface of the first doped region; and a gate located above the first doped region; and An NMOS transistor circuit comprising: A second doped region, which is located in the substrate and is located in the same plane as the avalanche diode doped region; A first active region, which is located on an upper surface of the second doped region; A second active region located on an upper surface of the second doped region; and A gate is located above the second doped region.
7. The optical sensor according to claim 6, characterized in that The first interconnect structure comprises: A first conductive member electrically connected to the SPAD first electrode, the SPAD second electrode, the first active region, the second active region and the gate of the PMOS transistor circuit and the NMOS transistor circuit; A first metal wire is electrically connected to the first conductive member.
8. The optical sensor according to claim 7, characterized in that Also includes: an oxide layer, which is located on the substrate and wraps the gate; The dielectric layer is located on the oxide layer and wraps the first conductive member.
9. The optical sensor according to claim 8, characterized in that Also includes: a second interconnect structure electrically connected to the first interconnect structure, the second interconnect structure comprising a second conductive member and a second metal line; The insulating layer is located on the dielectric layer and wraps the first metal wire and the second conductive member.
10. The optical sensor according to claim 9, characterized in that The second metal line is located on the insulating layer.