Multi-port protocol test board circuit

Abstract

The utility model discloses a multi-port protocol test board circuit and a multi-port protocol test board circuit, comprising an internal channel, a JTAG protocol port and an FPGA processor module; the interaction end comprises a TAP controller and an upper computer; the TAP controller receives an instruction from an upper computer, analyzes the instruction, enters a JTAG protocol port, and performs testing and read-back through the FPGA processor module; the TAP controller can be in cascade connection with a plurality of FPGA processor modules through a JTAG protocol port. And data interaction is carried out in combination with an IEEE STD 1149 communication protocol, so that the reliability of communication is ensured. An IEEE STD (Institute of Electrical and Electronic Engineers) 1149.1 protocol and an IEEE STD 1149.6 protocol are verified; meanwhile, connectivity testing of different interface connectors can be realized; and a multi-chip cascade verification test is realized. And compared with a traditional mode, the test range is larger, the application scene is more flexible, and the degree of freedom of Boundy Scan test is improved.

Description

Technical Field

[0001] The utility model relates to the field of port testing, in particular to a multi-port protocol testing board circuit. Background Art

[0002] JTAG's standard protocol IEEE Std 1149.1 has established a universal scan chain test method for testing the connectivity and integrity of semiconductor chips and other electronic devices. It can also detect connections and errors inside the chip without a component or connecting other devices. It is a very efficient and low-cost approach. For the connectivity verification of the IEEE Std1149.1 protocol and the 1149.6 protocol itself, a more complex signal interaction process is required, such as using the BoundaryScan functional test board for protocol testing. However, the traditional Boundary Scan functional test board is not perfect for the IEEE Std1149.1 protocol test, and the test method is relatively simple, and the efficiency is low when facing multi-level work. Therefore, a verification platform that can flexibly configure different inspection functions and can perform multi-chip cascade testing is designed, and its basic circuit structure located in the test board is summarized. Utility Model Content

[0003] The purpose of this section is to summarize some aspects of the embodiments of the utility model and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract of the specification and the name of the utility model of this application to avoid blurring the purpose of this section, the abstract of the specification and the name of the utility model, and such simplifications or omissions cannot be used to limit the scope of the utility model.

[0004] In view of the fact that the traditional Boundary Scan functional test board in the above and / or prior art is not perfect for the protocol test of IEEE Std 1149.1, the test method is relatively single, and the efficiency is low when facing multi-level work, the present utility model is proposed.

[0005] Therefore, the technical problem to be solved by the utility model is to design a verification platform that can flexibly configure different inspection functions and can perform multi-chip cascade testing, and summarize its basic circuit structure located in the test board.

[0006] In order to solve the above technical problems, the utility model provides the following technical solutions: a multi-port protocol test board circuit, comprising, an internal channel, including a JTAG protocol port, and an FPGA processor module;

[0007] Interaction end, including TAP controller and host computer;

[0008] The TAP controller receives instructions from the host computer, parses and enters the JTAG protocol port, and performs testing and reading back through the FPGA processor module;

[0009] The TAP controller can cascade multiple FPGA processor modules through the JTAG protocol port.

[0010] As a preferred solution of the multi-port protocol test board circuit described in the utility model, the FPGA processor module is composed of two XC7A35T modules and their peripheral circuits.

[0011] As a preferred solution of the multi-port protocol test board circuit described in the utility model, when the TAP controller completes the parsing of the test instruction of the host computer, the XC7A35T module controls the output voltage of the output pin and then reads back the interface status through the input pin to realize the testing of different functions.

[0012] As a preferred solution of the multi-port protocol test board circuit described in the utility model, the FPGA processor module transmits the test data to the TAP controller through the TDO pin in the JTAG protocol port, and sends it back to the host computer to obtain the test results.

[0013] As a preferred solution of the multi-port protocol test board circuit described in the utility model, when it is necessary to perform a connectivity test on the test board connector slot:

[0014] Connecting the IO interface of the TAP controller to the connector slot through the FPGA processing module, and inserting a standard test card into the connector slot;

[0015] The standard test card is connected to the TAP controller, and the TAP controller sends a test instruction, which is read back to the standard test card through the FPGA processor module to obtain the result.

[0016] As a preferred solution of the multi-port protocol test board circuit of the utility model, wherein: a plurality of the connector slots can be cascaded on one TAP controller through the JTAG protocol port to perform connectivity testing.

[0017] As a preferred solution of the multi-port protocol test board circuit of the utility model, the test instruction received by the TAP controller includes:

[0018] IDcode, Bypass, Samole, ExTest, ExTest Pulse;

[0019] Parse the test type according to the test instruction data and start the test.

[0020] As a preferred solution of the multi-port protocol test board circuit of the utility model, wherein: the TAP controller is connected to the FPGA processor module through the pins of the four JTAP protocol ports TDI, TCK, TMS, and TDO, with the assistance of the signal interface module;

[0021] The TCK pin lead is provided with a switch A1;

[0022] The TMS pin lead is provided with a switch A2;

[0023] The TDO pin leads are provided with switches A3, A4 and B4;

[0024] A cascade test switch K is connected in parallel between the TDI and TDO pin leads.

[0025] As a preferred solution of the multi-port protocol test board circuit of the utility model, when the FPGA processor module monolithically controls one TAP controller, the switch A4 and the switch B4 are in a closed state, and the other switches are disconnected;

[0026] When the FPGA processor module cascades multiple TAP controllers, the switch K and the switch A3 are closed, and the other switches are open.

[0027] As a preferred solution of the multi-port protocol test board circuit described in the utility model, wherein: when the test is started, the system needs to be powered externally, and the external power is converted into internal power through the step-down module;

[0028] The step-down power supply can input a 12V external power supply and step down the voltage to 1V, 1.2V, 1.8V, or 3.3V;

[0029] The FPGA processor module is electrically connected to the clock module to assist in controlling the test frequency.

[0030] The beneficial effects of the utility model are as follows: data interaction is carried out in combination with the IEEE STD 1149 communication protocol to ensure the reliability of communication. The IEEE STD 1149.1 protocol and the 1149.6 protocol are verified; at the same time, the connectivity test of different interface connectors can be realized; and multi-chip cascade verification test can be realized. Compared with the traditional method, the test range is larger, the applicable scenarios are more flexible, and the freedom of Boundary Scan test is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0032] Figure 1 A basic module logic diagram of a multi-port protocol test board circuit according to an embodiment of the utility model;

[0033] Figure 2 A schematic diagram of interactive circuit states of a multi-port protocol test board circuit according to an embodiment of the utility model;

[0034] Figure 3 An internal voltage reduction circuit diagram of a multi-port protocol test board circuit according to an embodiment of the utility model;

[0035] Figure 4 A JTAG protocol port circuit diagram of a multi-port protocol test board circuit according to an embodiment of the utility model;

[0036] Figure 5 A circuit diagram of an FPGA processor module of a multi-port protocol test board circuit according to an embodiment of the utility model; DETAILED DESCRIPTION

[0037] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0038] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0039] Secondly, the present invention is described in detail with reference to the schematic diagram. When describing the embodiments of the present invention, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0040] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0041] Example 1

[0042] Reference Figure 1 , this embodiment provides a multi-port protocol test board circuit, including an internal channel 100, which can be understood as a module and circuit inside the test board that participates in the test process, including a JTAG protocol port 101 and an FPGA processor module 102. The FPGA processor module 102 can provide the test board with a variety of connection solutions such as single-chip configuration, multi-chip configuration, and cascade configuration;

[0043] Further, the interactive end 200, i.e., the main component externally connected to the test board and participating in the test, includes a TAP controller 201 and a host computer 202. The TAP controller is a conventional interface for controlling JTAG and specifies four mandatory TAP signals;

[0044] Furthermore, the basic process of the entire test is as follows: the TAP controller 201 receives instructions from the host computer 202, parses the test category to be performed, and then enters the JTAG protocol port 101, controls the pins through the FPGA processor module 102, performs tests and reads back data to obtain results;

[0045] In detail, the TAP controller 201 can cascade multiple FPGA processor modules 102 through the JTAG protocol port 101. This change is the multi-port protocol testing effect brought by the FPGA.

[0046] The FPGA processor module 102 is composed of two XC7A35T modules and their peripheral circuits. The XC7A35T module provides the FPGA with the ability to control the output and input pins of the protocol circuit.

[0047] Example 2

[0048] Reference Figure 5 , which is the second embodiment of the utility model. This embodiment is based on the previous embodiment, and is different from the previous embodiment in that: Detailed test process: After the TAP controller 201 completes the parsing of the test instruction of the host computer 202, the XC7A35T module controls the output voltage of the output pin and then reads back the interface status through the input pin to implement tests of different functions. The pins are basically within the range of the JTAG protocol port.

[0049] In detail, the FPGA processor module 102 transmits the test data to the TAP controller 201 through the TDO pin in the JTAG protocol port 101. The TDO pin serves as an output pin interface. All data to be output from a specific one are output serially through the TDO interface. The TAP controller then sends the data back to the host computer 202 to obtain the test results, which are displayed on the host computer for display to the user.

[0050] Expansion solution: When you need to perform a connectivity test on the test board connector slot 400:

[0051] In detail, the IO interface of the FPGA processor module 102 is connected to the connector slot 400 through the interface assistance of the signal interface module 300. There are four connector slots 400 on the test board. The connectivity and welding status of the slot itself can be tested by inserting a standard test card W into the connector slot 400.

[0052] Furthermore, the standard test card is connected to the TAP controller 201, and the TAP controller 201 sends a test instruction, which is the same as the normal JTAG protocol detection process, and reads the interface information of the slot, and then reads the information back to the standard test card W through the FPGA processor module 102 to obtain the result.

[0053] As an extension, in the same way as the cascading of the FPGA processor module 102 and the TAP controller 201, multiple connector slots 400 can be cascaded on a TAP controller 201 through the JTAG protocol port 101 to perform a connectivity test and test the status of multiple connector slots 400 at the same time.

[0054] The test instructions received by the TAP controller 201 include:

[0055] IDcode, Bypass, Samole, ExTest, ExTest Pulse;

[0056] Parse the test type according to the test instruction data and start the test.

[0057] Example 3

[0058] Reference Figure 5 , which is the third embodiment of the utility model. This embodiment provides a multi-port protocol test board circuit. This embodiment is based on the previous embodiment, and is different from the previous embodiment in that: the test mode data instruction is configured through the signal interface module 300, and the input power is configured at the same time; the power input is directly input through the external input pin, and the internal level conversion chip of the board is stepped down to the internal power supply, and the connection of the power module is completed inside the board.

[0059] Since the system needs external power supply when the test is started, it is necessary to convert the external power into internal power supply through the step-down module 500 during the process;

[0060] Specifically, the step-down power supply 500 can input a 12V external power supply and step it down to 1V, 1.2V, 1.8V, and 3.3V; the circuit states of the four step-down modules can be Figure 3 Seen in.

[0061] Furthermore, the FPGA processor module 102 is electrically connected to the clock module 600 to assist in controlling the test frequency. The clock module is an essential component for the FPGA processor module 102 to ensure that there is a reference logic to ensure stable voltage output and signal output during the verification of the IEEE STD1149.1 protocol and the 1149.6 protocol.

[0062] In detail, the TAP controller 201 is connected to the FPGA processor module 102 through the four JTAP protocol ports 101 of TDI, TCK, TMS and TDO. The four ports are responsible for different signal transmission functions. The open state of each port determines the test mode. With the assistance of the signal interface module 300, the four ports are connected to the FPGA processor module 102 to form the main circuit, and the other output and input pins form the peripheral circuit;

[0063] A switch A1 is provided on the TCK pin lead;

[0064] A switch A2 is provided on the TMS pin lead;

[0065] The TDO pin is provided with switches A3, A4 and B4;

[0066] A1, A2 and A3 respectively control whether the TCK, TMS and TDO ports are connected to the signal interface module 300. If they are not connected to the signal interface module 300, cascading is not required.

[0067] When A1, A2, and A3 are not closed, open switch A4 and switch B4 to form a circuit mode in which they are connected separately. One TAP is connected to one FPGA, and they are tested one by one.

[0068] A cascade test switch K is connected in parallel between the TDI and TDO pin leads.

[0069] If switch A3 and switch K are closed, the necessary conditions for cascade testing are met, and a loop of multiple TAP controllers in parallel can be formed to perform TAP tests in different modes.

[0070] Importantly, it should be noted that the construction and arrangement of the present application shown in a plurality of different exemplary embodiments are only exemplary. Although only a few embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible (e.g., the size, scale, structure, shape and ratio of various elements, and parameter values ​​(e.g., temperature, pressure, etc.), installation arrangements, use of materials, color, directional changes, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present utility model. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure of performing the function described herein, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the present invention is not limited to a specific embodiment, but extends to various modifications that still fall within the scope of the appended claims.

[0071] Additionally, in order to provide a concise description of example embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0072] It will be appreciated that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but will be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure without undue experimentation.

[0073] It should be noted that the above embodiments are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model is described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A multi-port protocol test board circuit, characterized in that: include, An internal channel (100), including a JTAG protocol port (101) and an FPGA processor module (102); The interactive end (200) includes a TAP controller (201) and a host computer (202); The TAP controller (201) receives instructions from the host computer (202), parses and enters the JTAG protocol port (101), and performs testing and reading back through the FPGA processor module (102); The TAP controller (201) is capable of cascading a plurality of the FPGA processor modules (102) via the JTAG protocol port (101).

2. A multi-port protocol test board circuit according to claim 1, characterized in that: The FPGA processor module (102) is composed of two XC7A35T modules and their peripheral circuits.

3. A multi-port protocol test board circuit according to claim 2, characterized in that: When the TAP controller (201) completes parsing the test instruction of the host computer (202), the XC7A35T module controls the output pin to output voltage and then reads back the interface status through the input pin to implement tests of different functions.

4. A multi-port protocol test board circuit according to claim 3, characterized in that: The FPGA processor module (102) transmits the test data to the TAP controller (201) via the TDO pin in the JTAG protocol port (101), and sends the test data back to the host computer (202) to obtain the test result.

5. A multi-port protocol test board circuit according to claim 4, characterized in that: When it is necessary to perform a continuity test on the test board connector slot (400): Connecting the IO interface of the FPGA processor module (102) to the connector slot (400) via a signal interface module (300), and inserting a standard test card (W) into the connector slot (400); The standard test card is connected to the TAP controller (201), and the TAP controller (201) sends a test instruction, which is read back to the standard test card (W) through the FPGA processor module (102) to obtain a result.

6. A multi-port protocol test board circuit according to claim 5, characterized in that: A plurality of the connector slots (400) can be cascaded on one TAP controller (201) via the JTAG protocol port (101) to perform a connectivity test.

7. A multi-port protocol test board circuit according to claim 6, characterized in that: The test instruction received by the TAP controller (201) includes: IDcode, Bypass, Samole, ExTest, ExTest Pulse; Parse the test type according to the test instruction data and start the test.

8. A multi-port protocol test board circuit according to claim 7, characterized in that: The TAP controller (201) is connected to the FPGA processor module (102) through the four pins of the JTAP protocol port (101), namely TDI, TCK, TMS and TDO, with the assistance of the signal interface module (300); The TCK pin lead is provided with a switch A1; The TMS pin lead is provided with a switch A2; The TDO pin leads are provided with switches A3, A4 and B4; A cascade test switch K is connected in parallel between the TDI and TDO pin leads.

9. A multi-port protocol test board circuit according to claim 8, characterized in that: When the FPGA processor module (102) controls one of the TAP controllers (201) on a single chip, the switch A4 and the switch B4 are in a closed state, and the other switches are open; When the FPGA processor module (102) cascades a plurality of the TAP controllers (201), the switch K and the switch A3 are closed, and the other switches are opened.

10. The multi-port protocol test board circuit according to claim 9, characterized in that: When the test is started, the system needs to be powered externally, and the external power is converted into internal power through a step-down power supply (500); The step-down power supply (500) can input a 12V external power supply and step down the voltage to 1V, 1.2V, 1.8V, or 3.3V; The FPGA processor module (102) is electrically connected to a clock module (600) to assist in controlling the test frequency.

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