Fault-tolerant improvement-based inverter

Abstract

The utility model provides an inverter based on fault-tolerant improvement, which comprises a first redundant circuit, one end of the first redundant circuit is connected with a direct current power supply Vdc, a voltage stabilizing circuit and a second host circuit, and the other end of the first redundant circuit is connected with a second redundant circuit, a third redundant circuit and a fourth redundant circuit; one end of the second redundant circuit is connected with a first redundant circuit, a third redundant circuit and a fourth redundant circuit, and the other end of the second redundant circuit is connected with a direct-current power supply Vdc, a voltage stabilizing circuit and a third host circuit; one end of the third redundant circuit is connected with a first redundant circuit, a second redundant circuit and a fourth redundant circuit, and the other end of the third redundant circuit is connected with a first host circuit, a second host circuit, a third host circuit and a three-phase load; one end of the fourth redundant circuit is connected with the first redundant circuit, the second redundant circuit and the third redundant circuit, and the other end is connected with the voltage stabilizing circuit and the first host circuit; one end of the first host circuit is connected with the fourth redundant circuit and the voltage stabilizing circuit, and the other end is connected with a second host circuit, a third host circuit, a third redundant circuit and a three-phase load.

Description

Technical Field

[0001] The utility model relates to the technical field of inverters, in particular to an inverter based on fault tolerance improvement. Background Art

[0002] In applications with critical power requirements, such as emergency loads in electric vehicles, uninterruptible power supply systems, etc., constant rated power is essential. Similarly, in remote applications such as offshore wind power systems, maintenance is challenging. Any fault on the inverter system switch will significantly affect the maintenance-related costs, which in turn leads to higher overall machine costs. Therefore, it is a major challenge to develop a fault-tolerant inverter with retained rated voltage and minimal equipment. A simple and commonly used method to provide fault tolerance for three-phase inverters is to use redundant switches. In some works, the fault tolerance characteristics of the inverter are solved, but they are limited to single-phase faults and lack multi-phase fault tolerance. In a few works, the problem of multi-phase or multi-branch faults has been solved, which limits the application of the inverter. If the inverter uses two DC link capacitors to produce a three-level output, the occurrence of a fault will cause the capacitor voltage to be unbalanced. The capacitor balancing problem is generally solved by closed-loop control operation using an additional voltage sensor circuit.

[0003] The inverter uses redundant branches and thyristors to make the inverter single-phase fault-tolerant or a fault-tolerant inverter with a reduced number of devices. Both conversions can support rated power in the event of any single switch and single-phase faults, but lack multi-phase fault tolerance. Partially fault-tolerant inverters are derived from active NPC-type inverters, which have the inherent characteristic of tolerating certain switch faults, but in most fault conditions, the inverter's post-fault operation cannot be reconfigured to provide full rated output, and multi-phase fault tolerance is not possible under this topology. Inverters with single-phase and multi-phase fault tolerance characteristics, in which the inverter can be reconfigured to obtain a two-level output at rated power after a fault, use a higher diode count, resulting in reduced efficiency. Utility Model Content

[0004] In view of the problems existing in the prior art, the utility model provides an inverter based on fault tolerance improvement to solve the problems in the prior art that the inverter cannot obtain the required voltage level after single-phase and multi-phase faults and it is difficult to balance the capacitor voltage after the fault occurs.

[0005] The utility model is realized by the following technical solutions:

[0006] An inverter based on fault tolerance improvement comprises a first redundant circuit, wherein one end of the first redundant circuit is connected to a DC power supply Vdc, a voltage stabilizing circuit and a second host circuit, and the other end is connected to the second redundant circuit, the third redundant circuit and the fourth redundant circuit; one end of the second redundant circuit is connected to the first redundant circuit, the third redundant circuit and the fourth redundant circuit, and the other end is connected to the DC power supply Vdc, the voltage stabilizing circuit and the third host circuit; one end of the third redundant circuit is connected to the first redundant circuit, the second redundant circuit and the fourth redundant circuit, and the other end is connected to the first host circuit, the second host circuit, the third host circuit and a three-phase load; one end of the fourth redundant circuit is connected to the first redundant circuit, the second redundant circuit and the third redundant circuit, and the other end is connected to the voltage stabilizing circuit and the first host circuit; one end of the first host circuit is connected to the fourth redundant circuit and the voltage stabilizing circuit, and the other end is connected to the second host circuit, the third host circuit, the third redundant circuit and the three-phase load.

[0007] Furthermore, the first redundant circuit includes a power switch tube SrU2, a power switch tube SrU1 and a resistive-inductive load R1, the emitter of the power switch tube SrU2 is connected to the collector of the power switch tube SrU1, and the power switch tube SrU2 is connected in parallel with the resistive-inductive load R1.

[0008] Furthermore, the second redundant circuit includes a power switch tube SrL1, a power switch tube SrL2 and a resistive-inductive load R2, the emitter of the power switch tube SrL1 is connected to the collector of the power switch tube SrL2, and the power switch tube SrL2 is connected in parallel with the resistive-inductive load R2.

[0009] Furthermore, the third redundant circuit includes a bidirectional power switch tube Sra, a bidirectional power switch tube Srb and a bidirectional power switch tube Src connected in parallel, and the bidirectional power switch tube Sra, the bidirectional power switch tube Srb and the bidirectional power switch tube Src are all composed of collectors of two IGBTs connected together.

[0010] Furthermore, the fourth redundant circuit includes a bidirectional power switch tube SrM, and the bidirectional power switch tube SrM is composed of two collectors of IGBTs connected together.

[0011] Furthermore, the first host circuit includes a bidirectional power switch tube SaM, a bidirectional power switch tube SbM and a bidirectional power switch tube ScM connected in parallel with each other, and the bidirectional power switch tube SaM, the bidirectional power switch tube SbM and the bidirectional power switch tube ScM are all composed of collectors of two IGBTs connected together.

[0012] Furthermore, the first redundant circuit, the second redundant circuit and the fourth redundant circuit are interconnected to form a T-shaped structure.

[0013] Furthermore, the DC power supply Vdc, the voltage stabilizing circuit, the first host circuit, the second host circuit, and the third host circuit generate a three-level output voltage in each phase under healthy operation.

[0014] Furthermore, the DC voltage source Vdc value is 100V.

[0015] Furthermore, the first redundant circuit, the second redundant circuit, the second host circuit, and the third host circuit all use IGBT switch tubes of model SKM75GB12T4.

[0016] Compared with the prior art, the utility model has the following beneficial technical effects:

[0017] The utility model provides an inverter based on fault tolerance improvement, comprising a first redundant circuit, wherein one end of the first redundant circuit is connected to a DC power supply Vdc, a voltage stabilizing circuit and a second host circuit, and the other end is connected to the second redundant circuit, the third redundant circuit and the fourth redundant circuit; one end of the second redundant circuit is connected to the first redundant circuit, the third redundant circuit and the fourth redundant circuit, and the other end is connected to the DC power supply Vdc, the voltage stabilizing circuit and the third host circuit; one end of the third redundant circuit is connected to the first redundant circuit, the second redundant circuit and the fourth redundant circuit, and the other end is connected to the first host circuit, the second host circuit, the third host circuit and a three-phase load; one end of the fourth redundant circuit is connected to The first redundant circuit, the second redundant circuit and the third redundant circuit, and the other end are connected to the voltage stabilizing circuit and the first host circuit; one end of the first host circuit is connected to the fourth redundant circuit and the voltage stabilizing circuit, and the other end is connected to the second host circuit, the third host circuit, the third redundant circuit and the three-phase load; in the present application, when a host circuit fails, the redundant circuit supports the host circuit to provide an additional switching path to obtain the required voltage level. The redundant circuit based on the resistance switch can also be used to balance the capacitor voltage after a fault occurs, thereby avoiding the need for additional voltage sensors. The reliability of the inverter is very high, and therefore, it is widely used in uninterruptible power supplies, electric vehicles, and emergency loads for remote applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a topological structure diagram of the inverter based on fault tolerance improvement of the utility model;

[0019] Figure 2 It is a schematic diagram of working mode 1 of the inverter based on fault tolerance improvement of the utility model;

[0020] Figure 3 It is a schematic diagram of working mode 2 of the inverter based on fault tolerance improvement of the utility model;

[0021] Figure 4 It is a schematic diagram of working mode 3 of the inverter based on fault tolerance improvement of the utility model;

[0022] Figure 5 It is a schematic diagram of working mode 4 of the inverter based on fault tolerance improvement of the utility model;

[0023] Figure 6 It is a schematic diagram of working mode 5 of the inverter based on fault tolerance improvement of the utility model;

[0024] Figure 7 It is a schematic diagram of working mode 6 of the inverter based on fault tolerance improvement of the utility model;

[0025] Figure 8 It is a schematic diagram of the working mode 7 of the inverter based on fault tolerance improvement of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings, which are intended to explain the present invention rather than to limit it.

[0027] In order to enable those skilled in the art to better understand the solution of the utility model, the technical solution in the embodiment of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiment of the utility model. Obviously, the described embodiment is only a part of the embodiment of the utility model, not all of the embodiments. Based on the embodiment of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the utility model.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the utility model described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, products or devices.

[0029] The utility model provides an inverter based on fault tolerance improvement, such as Figure 1As shown, it includes a first redundant circuit, a second redundant circuit, a third redundant circuit, a fourth redundant circuit, a voltage stabilizing circuit, a first host circuit, a second host circuit, and a third host circuit; the positive pole of the DC power supply Vdc is connected to the first redundant circuit, the voltage stabilizing circuit, and the second host circuit, and the negative pole is connected to the second redundant circuit, the voltage stabilizing circuit, and the third host circuit; the upper port of the first redundant circuit is connected to the DC power supply Vdc, the voltage stabilizing circuit, and the second host circuit, and the lower port is connected to the second redundant circuit, the third redundant circuit, and the fourth redundant circuit; the upper port of the second redundant circuit is connected to the first redundant circuit, the third redundant circuit, and the fourth redundant circuit , the lower port is connected to the DC power supply Vdc, the voltage stabilizing circuit, and the third host circuit; the left port of the third redundant circuit is connected to the first redundant circuit, the second redundant circuit, and the fourth redundant circuit, and the right port is connected to the first host circuit, the second host circuit, the third host circuit, and the three-phase load; the left port of the fourth redundant circuit is connected to the first redundant circuit, the second redundant circuit, and the third redundant circuit, and the right port is connected to the voltage stabilizing circuit and the first host circuit; the left port of the first host circuit is connected to the fourth redundant circuit and the voltage stabilizing circuit, and the right port is connected to the second host circuit, the third host circuit, the third redundant circuit, and the three-phase load. When a host circuit fails, the redundant circuit supports the host circuit to provide an additional switch path to obtain the required voltage level. The redundant circuit based on the resistive switch can also be used to balance the capacitor voltage after a fault occurs, thereby avoiding the need for additional voltage sensors.

[0030] Preferably, the first redundant circuit includes power switch tubes SrU2 and SrU1, a resistive-inductive load R1, the emitter of the power switch tube SrU2 is connected to the collector of the power switch tube SrU1, and the power switch tube SrU2 is connected in parallel with the resistive-inductive load R1. The second redundant circuit includes power switch tubes SrL1 and SrL2, a resistive-inductive load R2, the emitter of the power switch tube SrL1 is connected to the collector of the power switch tube SrL2, and the power switch tube SrL2 is connected in parallel with the resistive-inductive load R2. The third redundant circuit includes bidirectional power switch tubes Sra, Srb, and Src, the bidirectional power switch tube is composed of two IGBT collectors connected, and the bidirectional power switch tubes Sra, Srb, and Src are connected in parallel with each other. The fourth redundant circuit includes a bidirectional power switch tube SrM, and the bidirectional power switch tube is composed of two IGBT collectors connected. The first host circuit includes bidirectional power switch tubes SaM, SbM, and ScM, and the bidirectional power switch tube is composed of two IGBT collectors connected, and the bidirectional power switch tubes SaM, SbM, and ScM are connected in parallel. The first redundant circuit, the second redundant circuit, and the fourth redundant circuit are connected to each other to form a T-type structure. It should be noted that the T-type structure control strategy is simpler, and the output harmonic distortion is lower. At the same time, because the T-type structure has lower losses, the T-type structure has higher efficiency in certain application scenarios.

[0031] Preferably, the DC power supply Vdc, the voltage stabilizing circuit, the first host circuit, the second host circuit, and the third host circuit generate a three-level output voltage in each phase under healthy operation. The DC voltage source Vdc value is 100V. The first redundant circuit, the second redundant circuit, the second host circuit, and the third host circuit all use IGBT switch tubes of model SKM75GB12T4. The third redundant circuit, the fourth redundant circuit, and the first host circuit all use IGBT switch tubes of model SKM15N120. The voltage stabilizing circuits all use model 335MWR400K, the capacitance is 680uF, and the withstand voltage is 450F. The resistance of the resistive-inductive load R1 and the resistive-inductive load R2 is 10Ω, the inductor core model is 1140-182K-RC, and its inductance value is 5mH.

[0032] Preferably, the present application also includes a driving circuit, a DSP chip, and a PWM controller;

[0033] The switching frequency of the PWM controller is 10 khz, and the duty cycle is not greater than 0.8; specifically, the driving circuit adopts the SKYPER32PRO driving circuit, and the DSP chip adopts the TMS320F28335 series.

[0034] It should be noted in this example that, in the inverter of the utility model, level shift pulse width modulation is used to generate the required PWM pulses; the initial LS-PWM is started to make the main unit produce a three-level output. Therefore, the fault detection signal determines the normal or fault operation of the inverter. Once a fault is detected at any position, the inverter will be reconfigured to the available switching state programmed for the specific fault, and the PWM will be reconstructed after the corresponding fault is programmed.

[0035] The working process of the utility model is introduced below:

[0036] When the inverter operates in healthy mode, the PWM load capacitor voltage is generally balanced, that is, the average voltage of the capacitor remains constant. However, whenever a switch fails, the capacitor voltage becomes unbalanced and some voltage levels become unavailable. After detecting a switch failure, the inverter can reconfigure the available redundant switch paths to obtain the exact voltage level. However, due to the unbalanced capacitor voltage, the output voltage will result in higher THD. Therefore, before reconfiguring the inverter after a fault, the capacitor voltage should be balanced to obtain the desired output. The resistor switching circuit in the proposed inverter makes the resistors connected in parallel with the capacitors equal in size, which helps to balance the capacitor voltage. Assuming a fault situation, when the capacitor voltage Vc1 is unbalanced and charges to a voltage value Vc1(0) due to the unavailability of the discharge path, in this case, when the resistor switching circuit is activated by sending a high signal to switches SrU1, SrL1 and SrM, the resistor can be connected across the two capacitors, thereby balancing the capacitor voltage. The time required to achieve capacitor voltage balancing depends on the value of the resistor.

[0037] It is necessary to further explain that in the inverter proposed by the utility model, in order to be able to perform fault-tolerant operation for a few multi-phase fault conditions, the midpoint should be connected to the positive or negative pole of the DC power supply. This is achieved by short-circuiting one of the capacitors through a resistor switching circuit. These unique switching states of the proposed inverter enhance the reliability of the inverter.

[0038] Working mode 1: Figure 2 As shown, the upper switch is open circuit fault SaU. When the upper switch SaU fails, the a-pole voltage level positive Vdc is not available, resulting in capacitor voltage imbalance. The switch circuit is used to balance the capacitor voltage, that is, SrU1, SrU2 and SrM are activated, and all other switches remain open. This configuration makes equal resistances between the capacitors in parallel, which helps to make the voltages of the two capacitors equal. After achieving capacitor voltage balance, the switch paths SrU1, SrU2, and Sra are used to make the a-pole voltage obtain positive Vdc, the switch SaM is used to obtain +Vdc / 2, and the switch SaL is used to obtain a 0 voltage state, ensuring that each pole produces a three-level output. The results obtained show that the output voltage and current are the same in a healthy state. In the same way, other single-phase faults can be solved.

[0039] Working mode 2: Figure 3As shown, the upper switch open circuit fault SaUSbU, when the upper switches SaU and SbU have open circuit faults at the same time, the DC capacitor voltage is unbalanced, and the switching path of the voltage level +Vdc of poles a and b is unavailable. In order to obtain the voltage level missing at pole a, the switching path obtains the voltage level +Vdc at pole a through SrU1, SrU2, Sra. Similarly, the circuit is reconfigured to use switches SrU1, SrU2, Srb to obtain the voltage level +Vdc at pole b. Next, the signals of the remaining healthy switches remain unchanged, generating voltage levels +Vdc / 2 and 0 at poles a and b, and voltage levels +Vdc, +Vdc / 2 and 0 at pole c. The results obtained show that the output voltage and current are the same in a healthy state. In the same way, other upper switch two-phase faults can be solved.

[0040] Working mode 3: Figure 4 As shown, the upper switch open circuit fault SaUSbUScU, when the upper switches SaUSbUScU fail at the same time, the discharge path of capacitor C1 is unavailable, causing the voltage of capacitor C1 to rise very quickly. In this fault, the voltage level +Vdc is unavailable at all poles. Similarly, after the fault, before reconfiguration, the capacitor voltage balance is ensured by activating the resistance switch circuit. After achieving capacitor voltage balance, the switch paths SrU1, SrU2, and Sra are used to make the a pole voltage obtain positive Vdc, the switch paths SrU1, SrU2, and Srb are used to make the b pole voltage obtain positive Vdc, and the switch paths SrU1, SrU2, and Src are used to make the c pole voltage obtain positive Vdc. The switch states corresponding to the remaining voltage levels remain unchanged. The results obtained show that the output voltage and current are the same in a healthy state.

[0041] Working mode 4: Figure 5 As shown, when the middle switch is open circuit fault SaMSbM, in normal operation, the switch states SaM, SbM, and ScM are used to obtain the voltage level +Vdc / 2 of poles a, b, and c, respectively. When the middle switches SaM and SbM fail, the voltage level +Vdc / 2 of poles a and b is not available. Here, the capacitor voltage is firstly balanced by activating the resistor switch circuit, and then the voltage of pole a is obtained by the switch paths SrM and Sra to obtain +Vdc / 2, and the voltage of pole b is obtained by the switch paths SrM and Srb to obtain +Vdc / 2, and the proposed inverter is reconfigured, and the switch states corresponding to the remaining voltage levels remain unchanged. The results show that the output voltage and current are the same in a healthy state.

[0042] Working mode 5: Figure 6As shown, the upper switch and the middle switch open circuit fault SaUSbM, the switch SaU, SbM open circuit fault causes the a-pole voltage +Vdc and the b-pole voltage +Vdc / 2 to be unavailable. Since these unavailable voltage levels are not the same, they cannot be reconfigured with a single redundant branch to generate a three-level output voltage. In this fault condition, the switch paths SrU1, SrU2, Sra are used to make the a-pole voltage obtain +Vdc, and since the redundant path is unavailable, the switch path of +V / 2 is discarded. In order to obtain a better line voltage distribution diagram, the voltage level +Vdc / 2 of the remaining two poles is also discarded. That is, the control of the switch SaU is transferred to the switches SrU1, SrU2, Sra, and the control of the middle switch SxM is abandoned. Here, only the +Vdc and 0 voltage levels are used after the fault, so capacitor balancing is not required. The switch states corresponding to the remaining voltage levels remain unchanged. The results obtained show that the output voltage and current are the same as in a healthy state.

[0043] Working mode 6: Figure 7 As shown, the upper and lower switches fail open circuit faults SaUSbL, and the a-pole voltage +Vdc and b-pole voltage 0 are unavailable when switches SaU and SbL fail simultaneously. Here, a redundant unit can be used to provide the missing voltage level of one phase (for example, 0 at the b-pole). The other missing voltage (+Vdc at the a-pole) cannot be discarded to obtain the rated output as in the previous case. In order to provide fault tolerance, the midpoint is connected to the positive pole of the DC power supply through the short-circuited capacitor C1, and the healthy middle switch SaM is used to obtain +Vdc at the a-pole. Here, by activating SrU1 and SrM, the capacitor voltage Vc1 is gently discharged to close to "0", and then SrU2 is activated to short-circuit capacitor C1. For better understanding, once the midpoint is connected to the positive pole of the DC power supply, the voltage level +Vdc / 2 disappears. Then, the +Vdc voltage level is generated at the a-pole through the switch paths SrU1, SrU2, SrM, and SaM, and the 0 voltage level is generated at the b-pole through the switch paths SrL1, SrL2, and Srb. The proposed inverter is reconfigured, and the switch states corresponding to the remaining voltage levels remain unchanged. The obtained results show that the output voltage and current are the same in the healthy state.

[0044] Working mode 7: Figure 8As shown, the upper switch and the lower switch are open-circuited at the same time, SaUSbLScU, and the switches SaU, SbL, and ScU fail at the same time, resulting in the loss of the +Vdc voltage level at the a pole, the 0 voltage level at the b pole, and the +Vdc voltage level at the c pole. Similar to the previous case, by making the midpoint potential +Vdc, the inverter can be reconfigured to a two-level output. In this case, after the capacitor C1 is softly discharged to "0", the control of the inverter is updated and the inverter is reconfigured. The +Vdc voltage level is generated at the a pole through the switch paths SrU1, SrU2, SrM, and SaM, the 0 voltage level is generated at the b pole through the switch paths SrL1, SrL2, and Srb, and the +Vdc voltage level is generated at the c pole through the switch paths SrU1, SrU2, SrM, and ScM. The switch states corresponding to the remaining voltage levels remain unchanged. The results obtained show that the output voltage and current are the same as in a healthy state.

[0045] This utility model proposes an inverter based on fault tolerance improvement. The operation of the inverter under healthy and open switch fault conditions is discussed in depth, emphasizing the importance of the newly introduced resistive switch circuit in balancing the capacitor voltage and facilitating the soft discharge of the capacitor of the additional switch path under specific switch fault conditions. The operation of the inverter is verified using hardware results for single-phase and multi-phase faults. The proposed inverter shows improved switching status in various switch faults of the main branch, thereby verifying the improvement of system reliability through reliability analysis. It proves to be very promising and well suited for critical and remote load applications.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model.

Claims

1. An inverter based on fault tolerance improvement, characterized in that: The invention comprises a first redundant circuit, wherein one end of the first redundant circuit is connected to a DC power supply Vdc, a voltage stabilizing circuit and a second host circuit, and the other end is connected to the second redundant circuit, the third redundant circuit and the fourth redundant circuit; one end of the second redundant circuit is connected to the first redundant circuit, the third redundant circuit and the fourth redundant circuit, and the other end is connected to the DC power supply Vdc, the voltage stabilizing circuit and the third host circuit; one end of the third redundant circuit is connected to the first redundant circuit, the second redundant circuit and the fourth redundant circuit, and the other end is connected to the first host circuit, the second host circuit, the third host circuit and a three-phase load; one end of the fourth redundant circuit is connected to the first redundant circuit, the second redundant circuit and the third redundant circuit, and the other end is connected to the voltage stabilizing circuit and the first host circuit; one end of the first host circuit is connected to the fourth redundant circuit and the voltage stabilizing circuit, and the other end is connected to the second host circuit, the third host circuit, the third redundant circuit and the three-phase load.

2. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The first redundant circuit includes a power switch tube SrU2, a power switch tube SrU1 and a resistive-inductive load R1, the emitter of the power switch tube SrU2 is connected to the collector of the power switch tube SrU1, and the power switch tube SrU2 is connected in parallel with the resistive-inductive load R1.

3. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The second redundant circuit includes a power switch tube SrL1, a power switch tube SrL2 and a resistive-inductive load R2, the emitter of the power switch tube SrL1 is connected to the collector of the power switch tube SrL2, and the power switch tube SrL2 is connected in parallel with the resistive-inductive load R2.

4. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The third redundant circuit includes a bidirectional power switch tube Sra, a bidirectional power switch tube Srb and a bidirectional power switch tube Src connected in parallel with each other, and the bidirectional power switch tube Sra, the bidirectional power switch tube Srb and the bidirectional power switch tube Src are all composed of collectors of two IGBTs connected together.

5. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The fourth redundant circuit includes a bidirectional power switch tube SrM, and the bidirectional power switch tube SrM is composed of two collectors of IGBTs connected together.

6. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The first host circuit includes a bidirectional power switch tube SaM, a bidirectional power switch tube SbM and a bidirectional power switch tube ScM connected in parallel with each other, and the bidirectional power switch tube SaM, the bidirectional power switch tube SbM and the bidirectional power switch tube ScM are all composed of collectors of two IGBTs connected together.

7. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The first redundant circuit, the second redundant circuit and the fourth redundant circuit are connected to each other to form a T-shaped structure.

8. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The DC power supply Vdc, the voltage stabilizing circuit, the first host circuit, the second host circuit, and the third host circuit generate a three-level output voltage in each phase under healthy operation.

9. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The DC power supply Vdc value is 100V.

10. The inverter based on fault tolerance improvement according to claim 1, characterized in that: The first redundant circuit, the second redundant circuit, the second host circuit and the third host circuit all use IGBT switch tubes of model SKM75GB12T4.

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