Straight-through prevention circuit and topology circuit

Abstract

The utility model discloses an anti-straight-through circuit and a topology circuit, in the anti-straight-through circuit, a first input end of a first NAND gate module is used for receiving a first input signal, and a second input end of the first NAND gate module is used for receiving a second input signal; the first input end of the second NAND gate module is used for receiving a first input signal, and the second input end of the second NAND gate module is used for receiving a third input signal; the first input end of the first AND gate module is connected with the output end of the first NAND gate module, and the second input end of the first AND gate module is used for receiving a first input signal; the first input end of the second AND gate module is connected with the output end of the second NAND gate module, and the second input end of the second AND gate module is used for receiving a third input signal; the first input end of the third AND gate module is connected with the output end of the second NAND gate module, and the second input end of the third AND gate module is connected with the output end of the first AND gate module. Based on the above mode, the reliability of bridge arm switch control can be improved.

Description

Technical Field

[0001] The present application relates to the field of control technology, and in particular to an anti-shoot-through circuit and a topology circuit. Background Art

[0002] In the prior art, in the inverter circuit, the switch topology used by the unidirectional inverter generally includes the H4 topology and the Heric topology, and the switch topology used by the three-phase inverter generally includes the T-type three-level topology, etc. These switch topologies all belong to the bridge topology, and one arm of the bridge topology is divided into an upper arm and a lower arm. During the operation of the inverter, the switches on the upper arm and the switches on the lower arm are usually controlled accordingly to realize the inverter function of the inverter.

[0003] The defect of the prior art is that when an abnormality occurs in the control circuit of the inverter, such as when it is disturbed, control abnormality is likely to occur, resulting in the upper arm and the lower arm of a bridge arm being turned on, which will easily cause excessive current on the bridge arm, thereby causing damage to the inverter itself. Therefore, the reliability of the existing bridge arm switch control is low. Utility Model Content

[0004] The main technical problem solved by this application is how to improve the reliability of bridge arm switch control.

[0005] In order to solve the above technical problems, the first technical solution adopted in the present application is: an anti-straight-through circuit, applied to a target circuit, the target circuit includes a first bridge arm, the first bridge arm includes a first switch module and a second switch module, one end of the first switch module is used to receive a power supply voltage signal, the other end of the first switch module is connected to one end of the second switch module, and the other end of the second switch module is grounded, and the first switch module and the second switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; the anti-straight-through circuit includes: a first NAND gate module, the first input end of the first NAND gate module is used to receive a first input signal, and the second input end of the first NAND gate module is used to receive a second input signal; a second NAND gate module, the first input end of the second NAND gate module is used to receive the first input signal, and the second input end of the second NAND gate module is used to receive a third An input signal; a first AND gate module, a first input end of the first AND gate module is connected to the output end of the first NAND gate module, and a second input end of the first AND gate module is used to receive the first input signal; a second AND gate module, a first input end of the second AND gate module is connected to the output end of the second NAND gate module, and a second input end of the second AND gate module is used to receive a third input signal; a third AND gate module, a first input end of the third AND gate module is connected to the output end of the second NAND gate module, and a second input end of the third AND gate module is connected to the output end of the first AND gate module; the output end of the second AND gate module is used to connect to the driving end of the first switch module, and the output end of the third AND gate module is used to connect to the driving end of the second switch module; or, the output end of the second AND gate module is used to connect to the driving end of the second switch module, and the output end of the third AND gate module is used to connect to the driving end of the first switch module.

[0006] The target circuit further includes a second bridge arm, the second bridge arm includes a third switch module and a fourth switch module, one end of the third switch module is used to receive a power supply voltage signal, the other end of the third switch module is connected to one end of the fourth switch module, the other end of the fourth switch module is grounded, and the third switch module and the fourth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; the anti-straight-through circuit also includes: a third NAND gate module, the first input end of the third NAND gate module is used to receive the second input signal, and the second input end of the third NAND gate module is used to receive the fourth input signal; a fourth AND gate module, the first input end of the fourth AND gate module is connected to the output end of the first NAND gate module, and the fourth AND gate module The second input end of the module is used to receive a second input signal; a fifth AND gate module, the first input end of the fifth AND gate module is connected to the output end of the third NAND gate module, and the second input end of the fifth AND gate module is used to receive a fourth input signal; a sixth AND gate module, the first input end of the sixth AND gate module is connected to the output end of the third NAND gate module, and the second input end of the sixth AND gate module is connected to the output end of the fourth AND gate module; the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module; or, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module.

[0007] Among them, the target circuit also includes a third bridge arm, the third bridge arm includes a fifth switch module and a sixth switch module, one end of the fifth switch module is used to receive a power supply voltage signal, the other end of the fifth switch module is connected to one end of the sixth switch module, and the other end of the sixth switch module is grounded, and the fifth switch module and the sixth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; the anti-straight-through circuit includes: a fourth NAND gate module, a first input end of the fourth NAND gate module is used to receive a fifth input signal, and a second input end of the fourth NAND gate module is used to receive a sixth input signal; a fifth NAND gate module, a first input end of the fifth NAND gate module is used to receive a fifth input signal, and a second input end of the fifth NAND gate module is used to receive a seventh input signal; a seventh AND gate module, a seventh NAND ... first input end of the fifth NAND gate module The first input end of the gate module is connected to the output end of the fourth NAND gate module, and the second input end of the seventh AND gate module is used to receive a fifth input signal; the eighth AND gate module, the first input end of the eighth AND gate module is connected to the output end of the fifth NAND gate module, and the second input end of the eighth AND gate module is used to receive a seventh input signal; the ninth AND gate module, the first input end of the ninth AND gate module is connected to the output end of the fifth NAND gate module, and the second input end of the ninth AND gate module is connected to the output end of the seventh AND gate module; the output end of the eighth AND gate module is connected to the driving end of the fifth switch module, and the output end of the ninth AND gate module is connected to the driving end of the sixth switch module; or, the output end of the eighth AND gate module is connected to the driving end of the sixth switch module, and the output end of the ninth AND gate module is connected to the driving end of the fifth switch module.

[0008] The sixth input signal is the same as the first input signal, or the sixth input signal is the same as the second input signal, or the sixth input signal is the same as the third input signal, or the sixth input signal is the same as the fourth input signal.

[0009] The target circuit further includes a fourth bridge arm, the fourth bridge arm includes a seventh switch module and an eighth switch module, one end of the seventh switch module is used to receive a power supply voltage signal, the other end of the seventh switch module is connected to one end of the eighth switch module, the other end of the eighth switch module is grounded, and the seventh switch module and the eighth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; the anti-straight-through circuit also includes: a sixth NAND gate module, the first input end of the sixth NAND gate module is used to receive a sixth input signal, and the second input end of the sixth NAND gate module is used to receive an eighth input signal; a tenth AND gate module, the first input end of the tenth AND gate module is connected to the output end of the first NAND gate module, and the second input end of the tenth AND gate module is connected to the output end of the first NAND gate module. The input end is used to receive the sixth input signal; the eleventh AND gate module, the first input end of the eleventh AND gate module is connected to the output end of the sixth NAND gate module, and the second input end of the eleventh AND gate module is used to receive the eighth input signal; the twelfth AND gate module, the first input end of the twelfth AND gate module is connected to the output end of the sixth NAND gate module, and the second input end of the twelfth AND gate module is connected to the output end of the tenth AND gate module; the output end of the eleventh AND gate module is connected to the driving end of the seventh switch module, and the output end of the twelfth AND gate module is connected to the driving end of the eighth switch module; or, the output end of the eleventh AND gate module is connected to the driving end of the seventh switch module, and the output end of the twelfth AND gate module is connected to the driving end of the eighth switch module.

[0010] Among them, the first NAND gate module, the second NAND gate module, the first AND gate module, the second AND gate module and the third AND gate module are all signal modules to be input, and the signal modules to be input have at least one input end; the anti-straight-through circuit also includes: at least one filtering module, at least one filtering module is respectively arranged on the line connected to the input end of the corresponding signal module to be input, and the filtering module is used to filter the signal input to the signal module to be input.

[0011] Among them, the filtering module includes a resistor and a capacitor; one end of the resistor is used to receive the signal of the target input end of the signal module to be input, and the other end of the resistor is respectively connected to the target input end of the signal module to be input and one end of the capacitor, and the other end of the capacitor is grounded; the target input end is an input end of the gate module.

[0012] Wherein, the first NAND gate module and the second NAND gate module are both NAND gate modules; the NAND gate module comprises an AND gate unit and a NOT gate unit, and the input end of the NOT gate unit is connected to the output end of the AND gate unit.

[0013] In order to solve the above technical problems, the second technical solution adopted in the present application is: a topological circuit, including: a first switch module and a second switch module, one end of the first switch module is used to receive a power supply voltage signal, the other end of the first switch module is connected to one end of the second switch module, and the other end of the second switch module is grounded, and the first switch module and the second switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; a first NAND gate module, the first input end of the first NAND gate module is used to receive a first input signal, and the second input end of the first NAND gate module is used to receive a second input signal; a second NAND gate module, the first input end of the second NAND gate module is used to receive the first input signal, and the second input end of the second NAND gate module is used to receive a third input signal; the first AND gate module , the first input end of the first AND gate module is connected to the output end of the first NAND gate module, and the second input end of the first AND gate module is used to receive the first input signal; the second AND gate module, the first input end of the second AND gate module is connected to the output end of the second NAND gate module, and the second input end of the second AND gate module is used to receive the third input signal; the third AND gate module, the first input end of the third AND gate module is connected to the output end of the second NAND gate module, and the second input end of the third AND gate module is connected to the output end of the first AND gate module; the output end of the second AND gate module is connected to the driving end of the first switch module, and the output end of the third AND gate module is connected to the driving end of the second switch module; or, the output end of the second AND gate module is connected to the driving end of the second switch module, and the output end of the third AND gate module is connected to the driving end of the first switch module.

[0014] The topology circuit further includes: a third switch module and a fourth switch module, wherein one end of the third switch module is used to receive a power supply voltage signal, the other end of the third switch module is connected to one end of the fourth switch module, the other end of the fourth switch module is grounded, and the third switch module and the fourth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; a third NAND gate module, wherein the first input end of the third NAND gate module is used to receive a second input signal, and the second input end of the third NAND gate module is used to receive a fourth input signal; and a fourth AND gate module, wherein the first input end of the fourth AND gate module is connected to the output end of the first NAND gate module, and the second input end of the fourth AND gate module is used to Receive a second input signal; a fifth AND gate module, wherein the first input end of the fifth AND gate module is connected to the output end of the third NAND gate module, and the second input end of the fifth AND gate module is used to receive a fourth input signal; a sixth AND gate module, wherein the first input end of the sixth AND gate module is connected to the output end of the third NAND gate module, and the second input end of the sixth AND gate module is connected to the output end of the fourth AND gate module; the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module; or, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module.

[0015] The beneficial effect of the present application is that, different from the prior art, in the technical solution of the present application, the first input end of the first NAND gate module is used to receive the first input signal, the second input end of the first NAND gate module is used to receive the second input signal, the first input end of the second NAND gate module is used to receive the first input signal, the second input end of the second NAND gate module is used to receive the third input signal, the first input end of the first AND gate module is connected to the output end of the first NAND gate module, the second input end of the first AND gate module is used to receive the first input signal, the first input end of the second AND gate module is connected to the output end of the second NAND gate module, the second input end of the second AND gate module is used to receive the third input signal, the first input end of the third AND gate module is connected to the output end of the second NAND gate module, the second input end of the third AND gate module is connected to the output end of the first AND gate module, and the output end of the second AND gate module and the output end of the third AND gate module respectively output driving signals. Based on the above method, the high and low level combination of the driving signals outputted from the output end of the second AND gate module and the output end of the third AND gate module can be controlled by changing the high and low level combination of the first input signal, the second input signal and the third input signal, and the driving signals outputted from the output end of the second AND gate module and the output end of the third AND gate module cannot be both high level at the same time, that is, it can ensure that the bridge arm driven and controlled based on the driving signals outputted from the output end of the second AND gate module and the output end of the third AND gate module will not be fully turned on, thereby reducing the possibility of corresponding damage caused by excessive current on the bridge arm and improving the reliability of the bridge arm switch control. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic structural diagram of an embodiment of the target circuit of the present application;

[0018] Figure 2 is a structural schematic diagram of a first embodiment of the anti-straight-through circuit of the present application;

[0019] Figure 3 is a structural schematic diagram of a second embodiment of the anti-straight-through circuit of the present application;

[0020] Figure 4 is a structural schematic diagram of a third embodiment of the anti-straight-through circuit of the present application;

[0021] Figure 5 is a structural schematic diagram of a fourth embodiment of the anti-shoot-through circuit of the present application;

[0022] Figure 6 It is a structural schematic diagram of an embodiment of the filtering module of the present application;

[0023] Figure 7 It is a structural diagram of the fifth embodiment of the anti-straight-through circuit of the present application.

[0024] The reference numerals are: first bridge arm 11, first switch module 111, second switch module 112, second bridge arm 12, third switch module 121, fourth switch module 122, third bridge arm 13, fifth switch module 131, sixth switch module 132, fourth bridge arm 14, seventh switch module 141, eighth switch module 142, first NAND gate module 201, second NAND gate module 202, first AND gate module 203, second AND gate module 204, third bridge arm 13, fifth switch module 131, sixth switch module 132, fourth bridge arm 14, seventh switch module 141, eighth switch module 142, first NAND gate module 201, second NAND gate module 202, first AND gate module 203, second AND gate module 204, The third AND gate module 205, the third NAND gate module 206, the fourth AND gate module 207, the fifth AND gate module 208, the sixth AND gate module 209, the fourth NAND gate module 210, the fifth NAND gate module 211, the seventh AND gate module 212, the eighth AND gate module 213, the ninth AND gate module 214, the sixth NAND gate module 215, the tenth AND gate module 216, the eleventh AND gate module 217, the twelfth AND gate module 218, the resistor 301, and the capacitor 302. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0026] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] This application proposes an anti-shoot-through circuit, see Figure 1 , Figure 1 is a schematic diagram of the structure of an embodiment of the target circuit of the present application, such as Figure 1 As shown, the target circuit includes a first bridge arm 11, and the first bridge arm 11 includes a first switch module 111 and a second switch module 112. One end of the first switch module 111 is used to receive a power supply voltage signal, and the other end of the first switch module 111 is connected to one end of the second switch module 112, and the other end of the second switch module 112 is grounded. The first switch module 111 and the second switch module 112 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0029] See also Figure 2 , Figure 2 is a schematic diagram of the structure of the first embodiment of the anti-straight-through circuit of the present application. Figure 2 As shown, the anti-shoot-through circuit includes a first NAND gate module 201 , a second NAND gate module 202 , a first AND gate module 203 , a second AND gate module 204 and a third AND gate module 205 .

[0030] The first input terminal of the first NAND gate module 201 is used to receive a first input signal, and the second input terminal of the first NAND gate module 201 is used to receive a second input signal.

[0031] The first input terminal of the second NAND gate module 202 is used to receive a first input signal, and the second input terminal of the second NAND gate module 202 is used to receive a third input signal.

[0032] A first input end of the first AND gate module 203 is connected to an output end of the first NAND gate module 201 , and a second input end of the first AND gate module 203 is used to receive a first input signal.

[0033] A first input terminal of the second AND gate module 204 is connected to an output terminal of the second NAND gate module 202 , and a second input terminal of the second AND gate module 204 is used to receive a third input signal.

[0034] A first input terminal of the third AND gate module 205 is connected to an output terminal of the second NAND gate module 202 , and a second input terminal of the third AND gate module 205 is connected to an output terminal of the first AND gate module 203 .

[0035] Among them, the output end of the second AND gate module 204 is used to connect the driving end of the first switch module 111, and the output end of the third AND gate module 205 is used to connect the driving end of the second switch module 112, or, the output end of the second AND gate module 204 is used to connect the driving end of the second switch module 112, and the output end of the third AND gate module 205 is used to connect the driving end of the first switch module 111.

[0036] Specifically, Figure 2 As shown, the first input signal VIN1 , the second input signal VIN2 , and the third input signal VIN3 are all driving signals that can be switched between a high level and a low level.

[0037] By respectively inputting the first input signal VIN1 to the first input end of the first NAND gate module 201, the first input end of the second NAND gate module 202 and the second input end of the first AND gate module 203 in the circuit, and inputting the second input signal VIN2 to the second input end of the first NAND gate module 201, and respectively inputting the third input signal VIN3 to the second input end of the second NAND gate module 202 and the second input end of the second AND gate module 204, it can be achieved that when the first input signal VIN1, the second input signal VIN2 and the third input signal VIN3 are any combination of high-level and low-level driving signals, the first output signal VOUT1 outputted from the output end of the third AND gate module 205 and the third output signal VOUT3 outputted from the output end of the second AND gate module 204 will not be high-level at the same time.

[0038] For example, when the second input signal VIN2 is high, no matter the first input signal VIN1 is high or low, the first output signal VOUT1 must be low. At this time, the first output signal VOUT1 and the third output signal VOUT3 will not be high at the same time.

[0039] When the second input signal VIN2 is at a low level:

[0040] If the first input signal VIN1 is at a low level and the third input signal VIN3 is at a low level, the first output signal VOUT1 is at a low level and the third output signal VOUT3 is at a low level.

[0041] If the first input signal VIN1 is at a low level and the third input signal VIN3 is at a high level, the first output signal VOUT1 is at a low level and the third output signal VOUT3 is at a high level.

[0042] If the first input signal VIN1 is at a high level and the third input signal VIN3 is at a low level, the first output signal VOUT1 is at a high level and the third output signal VOUT3 is at a low level.

[0043] If the first input signal VIN1 is at a high level and the third input signal VIN3 is at a high level, the first output signal VOUT1 is at a low level and the third output signal VOUT3 is at a low level.

[0044] Therefore, when the second input signal VIN2 is at a low level, no matter the first input signal VIN1 is at a high level or a low level, and the third input signal VIN3 is at a high level or a low level, at this time, the first output signal VOUT1 and the third output signal VOUT3 will not be at a high level at the same time.

[0045] It can be seen from the above that based on the setting of the above-mentioned anti-straight-through circuit, when the first input signal VIN1, the second input signal VIN2 and the third input signal VIN3 are any high and low level combinations, the first output signal VOUT1 and the third output signal VOUT3 can jointly output all possible high and low level combinations except for being high levels at the same time. That is, under this premise, the first output signal VOUT1 and the third output signal VOUT3 are input to the driving ends of the two switch modules on the first bridge arm 11 one by one to realize the corresponding function of the first bridge arm 11, which can avoid the situation in which the first switch module 111 and the second switch module 112 of the first bridge arm 11 are turned on at the same time, thereby reducing the possibility of excessive current in the first bridge arm 11, reducing the possibility of damage to the corresponding circuit, and improving the reliability of the bridge arm switch control.

[0046] In addition, it should be noted that the step of inputting the first output signal VOUT1 and the third output signal VOUT3 to the driving ends of the two switch modules on the first bridge arm 11 in a one-to-one correspondence may specifically include:

[0047] The first output signal VOUT1 outputted from the output end of the third AND gate module 205 is inputted to the first switch module 111, and the third output signal VOUT3 outputted from the output end of the second AND gate module 204 is inputted to the second switch module 112; alternatively, the third output signal VOUT3 outputted from the output end of the second AND gate module 204 is inputted to the first switch module 111, and the first output signal VOUT1 outputted from the output end of the third AND gate module 205 is inputted to the second switch module 112.

[0048] Any of the above methods may be used to control the first bridge arm 11 , and is not limited here.

[0049] The target circuit may specifically be an inverter circuit having a bridge arm, or may be other types of circuits having a bridge arm, which is not limited here.

[0050] Different from the prior art, in the technical solution of the present application, the first input end of the first NAND gate module is used to receive the first input signal, the second input end of the first NAND gate module is used to receive the second input signal, the first input end of the second NAND gate module is used to receive the first input signal, the second input end of the second NAND gate module is used to receive the third input signal, the first input end of the first AND gate module is connected to the output end of the first NAND gate module, the second input end of the first AND gate module is used to receive the first input signal, the first input end of the second AND gate module is connected to the output end of the second NAND gate module, the second input end of the second AND gate module is used to receive the third input signal, the first input end of the third AND gate module is connected to the output end of the second NAND gate module, the second input end of the third AND gate module is connected to the output end of the first AND gate module, and the second AND gate module The output end and the output end of the third AND gate module respectively output driving signals. Based on the above method, the high and low level combination of the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module can be controlled by changing the high and low levels of the first input signal, the second input signal and the third input signal, and the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module cannot be both high levels at the same time, that is, it can ensure that the bridge arm driven and controlled based on the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module will not be completely turned on, thereby reducing the possibility of corresponding damage caused by excessive current on the bridge arm, and improving the reliability of the bridge arm switch control.

[0051] In one embodiment, if Figure 1 As shown, the target circuit may also include a second bridge arm 12, the second bridge arm 12 includes a third switch module 121 and a fourth switch module 122, one end of the third switch module 121 is used to receive a power supply voltage signal, the other end of the third switch module 121 is connected to one end of the fourth switch module 122, the other end of the fourth switch module 122 is grounded, and the third switch module 121 and the fourth switch module 122 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0052] See also Figure 3 , Figure 3 is a schematic diagram of the structure of the second embodiment of the anti-straight-through circuit of the present application. Figure 3 As shown, the anti-shoot-through circuit further includes a third NAND gate module 206 , a fourth AND gate module 207 , a fifth AND gate module 208 and a sixth AND gate module 209 .

[0053] The first input terminal of the third NAND gate module 206 is used to receive the second input signal, and the second input terminal of the third NAND gate module 206 is used to receive the fourth input signal.

[0054] A first input terminal of the fourth AND gate module 207 is connected to the output terminal of the first NAND gate module 201 , and a second input terminal of the fourth AND gate module 207 is used to receive a second input signal.

[0055] A first input terminal of the fifth AND gate module 208 is connected to the output terminal of the third NAND gate module 206 , and a second input terminal of the fifth AND gate module 208 is used to receive a fourth input signal.

[0056] A first input terminal of the sixth AND gate module 209 is connected to an output terminal of the third NAND gate module 206 , and a second input terminal of the sixth AND gate module 209 is connected to an output terminal of the fourth AND gate module 207 .

[0057] Among them, the output end of the fifth AND gate module 208 is connected to the driving end of the third switch module 121, and the output end of the sixth AND gate module 209 is connected to the driving end of the fourth switch module 122, or the output end of the fifth AND gate module 208 is connected to the driving end of the third switch module 121, and the output end of the sixth AND gate module 209 is connected to the driving end of the fourth switch module 122.

[0058] Specifically, Figure 3 As shown, the first input signal VIN1 , the second input signal VIN2 , the third input signal VIN3 and the fourth input signal VIN4 are all driving signals that can be converted between a high level and a low level.

[0059] By inputting the first input signal VIN1 into the first input end of the first NAND gate module 201 in the circuit, and respectively inputting the second input signal VIN2 into the second input end of the first NAND gate module 201, the first input end of the third NAND gate module 206 and the second input end of the fourth AND gate module 207, and respectively inputting the fourth input signal VIN4 into the second input end of the third NAND gate module 206 and the second input end of the fifth AND gate module 208, it can be achieved that when the first input signal VIN1, the second input signal VIN2 and the fourth input signal VIN4 are any combination of high-level and low-level driving signals, the second output signal VOUT2 outputted from the output end of the sixth AND gate module 209 and the fourth output signal VOUT4 outputted from the output end of the fifth AND gate module 208 will not be high levels at the same time.

[0060] For example, when the first input signal VIN1 is high, no matter the second input signal VIN2 is high or low, the second output signal VOUT2 must be low. At this time, the second output signal VOUT2 and the fourth output signal VOUT4 will not be high at the same time.

[0061] When the first input signal VIN1 is at a low level:

[0062] If the second input signal VIN2 is at a low level and the fourth input signal VIN4 is at a low level, the second output signal VOUT2 is at a low level and the fourth output signal VOUT4 is at a low level.

[0063] If the second input signal VIN2 is at a low level and the fourth input signal VIN4 is at a high level, the second output signal VOUT2 is at a low level and the fourth output signal VOUT4 is at a high level.

[0064] If the second input signal VIN2 is at a high level and the fourth input signal VIN4 is at a low level, the second output signal VOUT2 is at a high level and the fourth output signal VOUT4 is at a low level.

[0065] If the second input signal VIN2 is at a high level and the fourth input signal VIN4 is at a high level, the second output signal VOUT2 is at a low level and the fourth output signal VOUT4 is at a low level.

[0066] Therefore, when the first input signal VIN1 is at a low level, no matter the second input signal VIN2 is at a high level or a low level, and the fourth input signal VIN4 is at a high level or a low level, at this time, the second output signal VOUT2 and the fourth output signal VOUT4 will not be at a high level at the same time.

[0067] As can be seen from the above, combined with the control of the first bridge arm 11 in the above embodiments, based on the setting of the above anti-straight-through circuit, when the first input signal VIN1, the second input signal VIN2, the third input signal VIN3 and the fourth input signal VIN4 are any high and low level combinations, the first output signal VOUT1 and the third output signal VOUT3 can jointly output all possible high and low level combinations except for being high levels at the same time, and the second output signal VOUT2 and the fourth output signal VOUT4 can jointly output all possible high and low level combinations except for being high levels at the same time, that is, under this premise, the first output signal VOUT1 and the third output signal VOUT3 are sent to the first bridge arm 11. The driving ends of the two switch modules on the arm 11 are input one by one to realize the corresponding function of the first bridge arm 11, and the second output signal VOUT2 and the fourth output signal VOUT4 are input one by one to the driving ends of the two switch modules on the second bridge arm 12 to realize the corresponding function of the second bridge arm 12. This can avoid the situation where the first switch module 111 and the second switch module 112 are turned on at the same time in the first bridge arm 11, and can also avoid the situation where the third switch module 121 and the fourth switch module 122 are turned on at the same time in the second bridge arm 12, thereby reducing the possibility of excessive current in the first bridge arm 11 or the second bridge arm 12, reducing the possibility of damage to the corresponding circuit, and improving the reliability of the bridge arm switch control.

[0068] Alternatively, if Figure 1 As shown, the target circuit may also include a third bridge arm 13, the third bridge arm 13 includes a fifth switch module 131 and a sixth switch module 132, one end of the fifth switch module 131 is used to receive a power supply voltage signal, the other end of the fifth switch module 131 is connected to one end of the sixth switch module 132, the other end of the sixth switch module 132 is grounded, and the fifth switch module 131 and the sixth switch module 132 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0069] See also Figure 4 , Figure 4 is a schematic diagram of the structure of the third embodiment of the anti-straight-through circuit of the present application. Figure 4 As shown, the anti-shoot-through circuit includes a fourth NAND gate module 210 , a fifth NAND gate module 211 , a seventh AND gate module 212 , an eighth AND gate module 213 and a ninth AND gate module 214 .

[0070] The first input terminal of the fourth NAND gate module 210 is used to receive the fifth input signal, and the second input terminal of the fourth NAND gate module 210 is used to receive the sixth input signal.

[0071] The first input terminal of the fifth NAND gate module 211 is used to receive the fifth input signal, and the second input terminal of the fifth NAND gate module 211 is used to receive the seventh input signal.

[0072] A first input terminal of the seventh AND gate module 212 is connected to the output terminal of the fourth NAND gate module 210 , and a second input terminal of the seventh AND gate module 212 is used to receive the fifth input signal.

[0073] A first input terminal of the eighth AND gate module 213 is connected to the output terminal of the fifth NAND gate module 211 , and a second input terminal of the eighth AND gate module 213 is used to receive the seventh input signal.

[0074] A first input terminal of the ninth AND gate module 214 is connected to the output terminal of the fifth NAND gate module 211 , and a second input terminal of the ninth AND gate module 214 is connected to the output terminal of the seventh AND gate module 212 .

[0075] Among them, the output end of the eighth AND gate module 213 is connected to the driving end of the fifth switch module 131, and the output end of the ninth AND gate module 214 is connected to the driving end of the sixth switch module 132, or the output end of the eighth AND gate module 213 is connected to the driving end of the sixth switch module 132, and the output end of the ninth AND gate module 214 is connected to the driving end of the fifth switch module 131.

[0076] Specifically, Figure 4 The anti-shoot-through circuit shown is Figure 3 Based on the anti-shoot-through circuit shown in the figure, an additional Figure 2 The circuits shown are circuit parts with the same anti-shoot-through circuit structure but different input signals.

[0077] Therefore, with Figure 2 The principle of the anti-straight-through circuit shown is similar. When the fifth input signal VIN5, the sixth input signal VIN6 and the seventh input signal VIN7 are any high-low level combinations, the fifth output signal VOUT5 and the seventh output signal VOUT7 can jointly output all possible high-low level combinations except for being high levels at the same time. That is, under this premise, the fifth output signal VOUT5 and the seventh output signal VOUT7 are input to the driving ends of the two switch modules on the third bridge arm 13 in a one-to-one correspondence to realize the corresponding function of the third bridge arm 13, which can avoid the situation in which the fifth switch module 131 and the sixth switch module 132 of the third bridge arm 13 are turned on at the same time, thereby reducing the possibility of excessive current in the third bridge arm 13, reducing the possibility of damage to the corresponding circuit, and improving the reliability of the bridge arm switch control.

[0078] It should be noted that in the target circuit only Figure 4In the case of the circuit shown, the sixth input signal is the same as the first input signal, or the sixth input signal is the same as the second input signal, or the sixth input signal is the same as the third input signal, or the sixth input signal is the same as the fourth input signal. Based on the above method, there is no need to additionally provide a separately controlled sixth input signal, so that the number of separately controlled drive signals required for the entire anti-straight-through circuit is reduced, thereby reducing the control difficulty of the anti-straight-through circuit and improving the ease of use of the anti-straight-through circuit.

[0079] Furthermore, if Figure 1 As shown, the target circuit also includes a fourth bridge arm 14, and the fourth bridge arm 14 includes a seventh switch module 141 and an eighth switch module 142. One end of the seventh switch module 141 is used to receive a power supply voltage signal, and the other end of the seventh switch module 141 is connected to one end of the eighth switch module 142, and the other end of the eighth switch module 142 is grounded. The seventh switch module 141 and the eighth switch module 142 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0080] See also Figure 5 , Figure 5 is a structural diagram of a fourth embodiment of the anti-straight-through circuit of the present application. Figure 5 As shown, the anti-shoot-through circuit further includes a sixth NAND gate module 215 , a tenth AND gate module 216 , an eleventh AND gate module 217 and a twelfth AND gate module 218 .

[0081] The first input terminal of the sixth NAND gate module 215 is used to receive the sixth input signal, and the second input terminal of the sixth NAND gate module 215 is used to receive the eighth input signal.

[0082] A first input terminal of the tenth AND gate module 216 is connected to the output terminal of the first NAND gate module 201 , and a second input terminal of the tenth AND gate module 216 is used to receive a sixth input signal.

[0083] A first input terminal of the eleventh AND gate module 217 is connected to the output terminal of the sixth NAND gate module 215 , and a second input terminal of the eleventh AND gate module 217 is used to receive the eighth input signal.

[0084] A first input terminal of the twelfth AND gate module 218 is connected to an output terminal of the sixth NAND gate module 215 , and a second input terminal of the twelfth AND gate module 218 is connected to an output terminal of the tenth AND gate module 216 .

[0085] Among them, the output end of the eleventh AND gate module 217 is connected to the driving end of the seventh switch module 141, and the output end of the twelfth AND gate module 218 is connected to the driving end of the eighth switch module 142, or, the output end of the eleventh AND gate module 217 is connected to the driving end of the seventh switch module 141, and the output end of the twelfth AND gate module 218 is connected to the driving end of the eighth switch module 142.

[0086] Specifically, Figure 5 As shown, the fifth input signal VIN5 , the sixth input signal VIN6 , the seventh input signal VIN7 and the eighth input signal VIN8 are all driving signals that can be converted between a high level and a low level.

[0087] By inputting the fifth input signal VIN5 into the first input terminal of the fourth NAND gate module 210 in the circuit, and respectively inputting the sixth input signal VIN6 into the second input terminal of the fourth NAND gate module 210, the first input terminal of the sixth NAND gate module 215 and the second input terminal of the tenth AND gate module 216, and respectively inputting the eighth input signal VIN8 into the second input terminal of the sixth NAND gate module 215 and the second input terminal of the eleventh AND gate module 217, it can be achieved that when the fifth input signal VIN5, the sixth input signal VIN6 and the eighth input signal VIN8 are any combination of high-level and low-level driving signals, the sixth output signal VOUT6 outputted from the output terminal of the twelfth AND gate module 218 and the eighth output signal VOUT8 outputted from the output terminal of the eleventh AND gate module 217 will not be high levels at the same time.

[0088] For example, when the fifth input signal VIN5 is high, no matter the sixth input signal VIN6 is high or low, the sixth output signal VOUT6 must be low. At this time, the sixth output signal VOUT6 and the eighth output signal VOUT8 will not be high at the same time.

[0089] When the fifth input signal VIN5 is at a low level:

[0090] If the sixth input signal VIN6 is at a low level and the eighth input signal VIN8 is at a low level, the sixth output signal VOUT6 is at a low level and the eighth output signal VOUT8 is at a low level.

[0091] If the sixth input signal VIN6 is at a low level and the eighth input signal VIN8 is at a high level, the sixth output signal VOUT6 is at a low level and the eighth output signal VOUT8 is at a high level.

[0092] If the sixth input signal VIN6 is at a high level and the eighth input signal VIN8 is at a low level, the sixth output signal VOUT6 is at a high level and the eighth output signal VOUT8 is at a low level.

[0093] If the sixth input signal VIN6 is at a high level and the eighth input signal VIN8 is at a high level, the sixth output signal VOUT6 is at a low level and the eighth output signal VOUT8 is at a low level.

[0094] Therefore, when the fifth input signal VIN5 is at a low level, no matter the sixth input signal VIN6 is at a high level or a low level, and the eighth input signal VIN8 is at a high level or a low level, at this time, the sixth output signal VOUT6 and the eighth output signal VOUT8 will not be at a high level at the same time.

[0095] As can be seen from the above, combined with the control of the third bridge arm 13 in the above embodiments, based on the setting of the above anti-through circuit, when the fifth input signal VIN5, the sixth input signal VIN6, the seventh input signal VIN7 and the eighth input signal VIN8 are any high and low level combinations, the fifth output signal VOUT5 and the seventh output signal VOUT7 can jointly output all possible high and low level combinations except for being high levels at the same time, and the sixth output signal VOUT6 and the eighth output signal VOUT8 can jointly output all possible high and low level combinations except for being high levels at the same time, that is, under this premise, the fifth output signal VOUT5 and the seventh output signal VOUT7 are sent to the third bridge arm 13. The driving ends of the two switch modules on the arm 13 are input one by one to realize the corresponding function of the third bridge arm 13, and the sixth output signal VOUT6 and the eighth output signal VOUT8 are input one by one to the driving ends of the two switch modules on the fourth bridge arm 14 to realize the corresponding function of the fourth bridge arm 14. This can avoid the situation where the fifth switch module 131 and the sixth switch module 132 are turned on at the same time in the third bridge arm 13, and can also avoid the situation where the seventh switch module 141 and the eighth switch module 142 are turned on at the same time in the fourth bridge arm 14, thereby reducing the possibility of excessive current in the third bridge arm 13 or the fourth bridge arm 14, reducing the possibility of damage to the corresponding circuit, and improving the reliability of the bridge arm switch control.

[0096] In one embodiment, the first NAND gate module 201 , the second NAND gate module 202 , the first AND gate module 203 , the second AND gate module 204 , and the third AND gate module 205 are all signal waiting input modules, and the signal waiting input modules have at least one input terminal.

[0097] The anti-straight-through circuit also includes at least one filtering module, which is respectively arranged on the line connected to the input end of the corresponding signal module to be input, and the filtering module is used to filter the signal input to the signal module to be input.

[0098] Specifically, the filter module includes a resistor and a capacitor. One end of the resistor is used to receive a signal input to the target input end of the signal module to be input, and the other end of the resistor is respectively connected to the target input end of the signal module to be input and one end of the capacitor, and the other end of the capacitor is grounded. The target input end is an input end of the gate module.

[0099] In one example, the input signal module is taken as a gate module for explanation, and the first NAND gate module 201, the second NAND gate module 202, the first AND gate module 203, the second AND gate module 204, and the third AND gate module 205 are all gate modules.

[0100] In addition, the AND gate modules and NOT gate modules described in other embodiments above, such as the third AND gate module 206, the fourth AND gate module 207, the fifth AND gate module 208, the sixth AND gate module 209, the fourth AND gate module 210, the fifth AND gate module 211, the seventh AND gate module 212, the eighth AND gate module 213, the ninth AND gate module 214, the sixth NAND gate module 215, the tenth AND gate module 216, the eleventh AND gate module 217, and the twelfth AND gate module 218, are also gate modules.

[0101] See also Figure 6 , Figure 6 is a schematic diagram of the structure of an embodiment of the filtering module of the present application, such as Figure 6 As shown, the filtering module includes a resistor 301 and a capacitor 302 .

[0102] One end of the resistor 301 is used to receive a signal input to the target input end of the gate module, and the other end of the resistor 301 is respectively connected to the target input end of the gate module and one end of the capacitor 302, and the other end of the capacitor 302 is grounded. The target input end is any input end of the gate module, such as the first input end or the second input end of the gate module.

[0103] It should be noted that Figure 6 The examples shown are illustrated using the gate module as a NAND gate. In other examples, the NAND gate may be replaced by other devices with input terminals, such as an AND gate, which is not limited here.

[0104] See also Figure 7 , Figure 7 is a structural diagram of the fifth embodiment of the anti-straight-through circuit of the present application. Figure 7 As shown, in the anti-straight-through circuit, a filtering module can be arranged before the input end of each gate module, so that the signal to be input to the corresponding input end is first filtered by the filtering module and then enters the corresponding input end.

[0105] When the gate module is a NAND gate module, an example is given by taking the gate module as the first NAND gate module 201. Figure 7As shown, a filter module is provided before the first input terminal of the first NAND gate module 201. At this time, the first input signal VIN1 received by the first input terminal of the first NAND gate module 201 is as follows: Figure 6 The second input signal VIN2 received by the second input terminal of the first NAND gate module 201 is as shown in FIG. Figure 6 The signal sent by the output end of the first NAND gate module 201 is as shown in V2. Figure 6 V3 shown.

[0106] When the gate module is an AND gate module, the gate module is taken as the second AND gate module 204 for example. Figure 7 As shown, a filtering module is set before the first input end of the second AND gate module 204. At this time, the signal output by the second NAND gate module 202 is first filtered by the filtering module and then enters the first input end of the second AND gate module 204. The third input signal VIN3 is first filtered by the filtering module and then enters the second input end of the second AND gate module 204.

[0107] Other gate modules may also be provided with filter modules accordingly, for filtering the signals input to their input terminals, which is not limited here.

[0108] Based on the above method, a filtering module can be set at the input end of each AND gate module and / or NAND gate module to filter the signal input to the gate module and remove stray signals to improve the reliability of the output result processed by the gate module.

[0109] In addition, the above is only an example description that the signal module to be input is a gate module. In other examples, the signal module to be input can also be replaced by other types of modules with input ends, and a filtering module can also be set on the line connected to the input end. The specific details can be determined according to actual needs and are not limited here.

[0110] In one embodiment, the first NAND gate module 201 and the second NAND gate module 202 are both NAND gate modules.

[0111] The NAND gate module comprises an AND gate unit and a NOT gate unit, and the input end of the NOT gate unit is connected to the output end of the AND gate unit.

[0112] Specifically, the NAND gate module may be formed by splicing an AND gate unit and a NOT gate unit, or may be a separate NAND gate module, which is not limited here.

[0113] The present application also proposes a topological circuit, which includes the target circuit and the anti-straight-through circuit described in the above embodiments. Specifically, it can be a power switch circuit or other types of circuits, which are not limited here.

[0114] like Figures 1 to 5 As shown, the topology circuit includes a first switch module 111 , a second switch module 112 , a first NAND gate module 201 , a second NAND gate module 202 , a first AND gate module 203 , a second AND gate module 204 and a third AND gate module 205 .

[0115] One end of the first switch module 111 is used to receive a power supply voltage signal, the other end of the first switch module 111 is connected to one end of the second switch module 112, the other end of the second switch module 112 is grounded, and the first switch module 111 and the second switch module 112 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0116] The first input terminal of the first NAND gate module 201 is used to receive a first input signal, and the second input terminal of the first NAND gate module 201 is used to receive a second input signal.

[0117] The first input terminal of the second NAND gate module 202 is used to receive a first input signal, and the second input terminal of the second NAND gate module 202 is used to receive a third input signal.

[0118] A first input end of the first AND gate module 203 is connected to an output end of the first NAND gate module 201 , and a second input end of the first AND gate module 203 is used to receive a first input signal.

[0119] A first input terminal of the second AND gate module 204 is connected to an output terminal of the second NAND gate module 202 , and a second input terminal of the second AND gate module 204 is used to receive a third input signal.

[0120] A first input terminal of the third AND gate module 205 is connected to an output terminal of the second NAND gate module 202 , and a second input terminal of the third AND gate module 205 is connected to an output terminal of the first AND gate module 203 .

[0121] Among them, the output end of the second AND gate module 204 is connected to the driving end of the first switch module 111, and the output end of the third AND gate module 205 is connected to the driving end of the second switch module 112, or the output end of the second AND gate module 204 is connected to the driving end of the second switch module 112, and the output end of the third AND gate module 205 is connected to the driving end of the first switch module 111.

[0122] In one embodiment, the topology circuit further includes a third switch module 121 , a fourth switch module 122 , a third NAND gate module 206 , a fourth AND gate module 207 , a fifth AND gate module 208 and a sixth AND gate module 209 .

[0123] One end of the third switch module 121 is used to receive a power supply voltage signal, the other end of the third switch module 121 is connected to one end of the fourth switch module 122, the other end of the fourth switch module 122 is grounded, and the third switch module 121 and the fourth switch module 122 are both used to be turned on when the corresponding driving end receives a high-level voltage signal.

[0124] The first input terminal of the third NAND gate module 206 is used to receive the second input signal, and the second input terminal of the third NAND gate module 206 is used to receive the fourth input signal.

[0125] A first input terminal of the fourth AND gate module 207 is connected to the output terminal of the first NAND gate module 201 , and a second input terminal of the fourth AND gate module 207 is used to receive a second input signal.

[0126] A first input terminal of the fifth AND gate module 208 is connected to the output terminal of the third NAND gate module 206 , and a second input terminal of the fifth AND gate module 208 is used to receive a fourth input signal.

[0127] A first input terminal of the sixth AND gate module 209 is connected to an output terminal of the third NAND gate module 206 , and a second input terminal of the sixth AND gate module 209 is connected to an output terminal of the fourth AND gate module 207 .

[0128] Among them, the output end of the fifth AND gate module 208 is connected to the driving end of the third switch module 121, and the output end of the sixth AND gate module 209 is connected to the driving end of the fourth switch module 122, or the output end of the fifth AND gate module 208 is connected to the driving end of the third switch module 121, and the output end of the sixth AND gate module 209 is connected to the driving end of the fourth switch module 122.

[0129] Specifically, the topological circuit may include some modules of the anti-straight-through circuit described in any of the above embodiments and corresponding connection methods, which will not be described in detail here.

[0130] Different from the prior art, in the technical solution of the present application, the first input end of the first NAND gate module is used to receive the first input signal, the second input end of the first NAND gate module is used to receive the second input signal, the first input end of the second NAND gate module is used to receive the first input signal, the second input end of the second NAND gate module is used to receive the third input signal, the first input end of the first AND gate module is connected to the output end of the first NAND gate module, the second input end of the first AND gate module is used to receive the first input signal, the first input end of the second AND gate module is connected to the output end of the second NAND gate module, the second input end of the second AND gate module is used to receive the third input signal, the first input end of the third AND gate module is connected to the output end of the second NAND gate module, the second input end of the third AND gate module is connected to the output end of the first AND gate module, and the second AND gate module The output end and the output end of the third AND gate module respectively output driving signals. Based on the above method, the high and low level combination of the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module can be controlled by changing the high and low levels of the first input signal, the second input signal and the third input signal, and the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module cannot be both high levels at the same time, that is, it can ensure that the bridge arm driven and controlled based on the driving signals output by the output end of the second AND gate module and the output end of the third AND gate module will not be completely turned on, thereby reducing the possibility of corresponding damage caused by excessive current on the bridge arm, and improving the reliability of the bridge arm switch control.

[0131] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An anti-shoot-through circuit, characterized in that: Applied to a target circuit, the target circuit includes a first bridge arm, the first bridge arm includes a first switch module and a second switch module, one end of the first switch module is used to receive a power supply voltage signal, the other end of the first switch module is connected to one end of the second switch module, the other end of the second switch module is grounded, and the first switch module and the second switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; The anti-straight-through circuit comprises: A first NAND gate module, wherein a first input end of the first NAND gate module is used to receive a first input signal, and a second input end of the first NAND gate module is used to receive a second input signal; A second NAND gate module, wherein the first input end of the second NAND gate module is used to receive a first input signal, and the second input end of the second NAND gate module is used to receive a third input signal; A first AND gate module, wherein a first input end of the first AND gate module is connected to an output end of the first NAND gate module, and a second input end of the first AND gate module is used to receive a first input signal; A second AND gate module, wherein a first input end of the second AND gate module is connected to an output end of the second NAND gate module, and a second input end of the second AND gate module is used to receive the third input signal; A third AND gate module, wherein a first input end of the third AND gate module is connected to an output end of the second NAND gate module, and a second input end of the third AND gate module is connected to an output end of the first AND gate module; Among them, the output end of the second AND gate module is used to connect the driving end of the first switch module, and the output end of the third AND gate module is used to connect the driving end of the second switch module; or, the output end of the second AND gate module is used to connect the driving end of the second switch module, and the output end of the third AND gate module is used to connect the driving end of the first switch module.

2. The anti-shoot-through circuit according to claim 1, characterized in that: The target circuit further includes a second bridge arm, the second bridge arm includes a third switch module and a fourth switch module, one end of the third switch module is used to receive a power supply voltage signal, the other end of the third switch module is connected to one end of the fourth switch module, the other end of the fourth switch module is grounded, and the third switch module and the fourth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; The anti-straight-through circuit also includes: A third NAND gate module, wherein the first input end of the third NAND gate module is used to receive the second input signal, and the second input end of the third NAND gate module is used to receive a fourth input signal; a fourth AND gate module, wherein a first input end of the fourth AND gate module is connected to an output end of the first NAND gate module, and a second input end of the fourth AND gate module is used to receive the second input signal; a fifth AND gate module, wherein a first input end of the fifth AND gate module is connected to an output end of the third NAND gate module, and a second input end of the fifth AND gate module is used to receive the fourth input signal; a sixth AND gate module, wherein a first input end of the sixth AND gate module is connected to an output end of the third NAND gate module, and a second input end of the sixth AND gate module is connected to an output end of the fourth AND gate module; Among them, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module; or, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module.

3. The anti-shoot-through circuit according to claim 2, characterized in that: The target circuit further includes a third bridge arm, the third bridge arm includes a fifth switch module and a sixth switch module, one end of the fifth switch module is used to receive a power supply voltage signal, the other end of the fifth switch module is connected to one end of the sixth switch module, the other end of the sixth switch module is grounded, and the fifth switch module and the sixth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; The anti-straight-through circuit comprises: a fourth NAND gate module, wherein the first input end of the fourth NAND gate module is used to receive a fifth input signal, and the second input end of the fourth NAND gate module is used to receive a sixth input signal; a fifth NAND gate module, wherein the first input end of the fifth NAND gate module is used to receive the fifth input signal, and the second input end of the fifth NAND gate module is used to receive the seventh input signal; a seventh AND gate module, wherein a first input end of the seventh AND gate module is connected to an output end of the fourth NAND gate module, and a second input end of the seventh AND gate module is used to receive the fifth input signal; an eighth AND gate module, wherein a first input end of the eighth AND gate module is connected to an output end of the fifth NAND gate module, and a second input end of the eighth AND gate module is used to receive the seventh input signal; a ninth AND gate module, wherein a first input end of the ninth AND gate module is connected to an output end of the fifth NAND gate module, and a second input end of the ninth AND gate module is connected to an output end of the seventh AND gate module; Among them, the output end of the eighth AND gate module is connected to the driving end of the fifth switch module, and the output end of the ninth AND gate module is connected to the driving end of the sixth switch module; or, the output end of the eighth AND gate module is connected to the driving end of the sixth switch module, and the output end of the ninth AND gate module is connected to the driving end of the fifth switch module.

4. The anti-shoot-through circuit according to claim 3, characterized in that: The sixth input signal is the same as the first input signal, or the sixth input signal is the same as the second input signal, or the sixth input signal is the same as the third input signal, or the sixth input signal is the same as the fourth input signal.

5. The anti-shoot-through circuit according to claim 3, characterized in that: The target circuit further includes a fourth bridge arm, the fourth bridge arm includes a seventh switch module and an eighth switch module, one end of the seventh switch module is used to receive a power supply voltage signal, the other end of the seventh switch module is connected to one end of the eighth switch module, the other end of the eighth switch module is grounded, and the seventh switch module and the eighth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; The anti-straight-through circuit also includes: a sixth NAND gate module, wherein the first input end of the sixth NAND gate module is used to receive a sixth input signal, and the second input end of the sixth NAND gate module is used to receive an eighth input signal; a tenth AND gate module, wherein a first input end of the tenth AND gate module is connected to an output end of the first NAND gate module, and a second input end of the tenth AND gate module is used to receive the sixth input signal; an eleventh AND gate module, wherein a first input end of the eleventh AND gate module is connected to an output end of the sixth NAND gate module, and a second input end of the eleventh AND gate module is used to receive the eighth input signal; A twelfth AND gate module, wherein a first input end of the twelfth AND gate module is connected to an output end of the sixth NAND gate module, and a second input end of the twelfth AND gate module is connected to an output end of the tenth AND gate module; Among them, the output end of the eleventh AND gate module is connected to the driving end of the seventh switch module, and the output end of the twelfth AND gate module is connected to the driving end of the eighth switch module; or, the output end of the eleventh AND gate module is connected to the driving end of the seventh switch module, and the output end of the twelfth AND gate module is connected to the driving end of the eighth switch module.

6. The anti-straight-through circuit according to any one of claims 1 to 4, characterized in that: The first NAND gate module, the second NAND gate module, the first AND gate module, the second AND gate module and the third AND gate module are all signal modules to be input, and the signal modules to be input have at least one input terminal; The anti-straight-through circuit also includes: At least one filtering module, wherein the at least one filtering module is respectively arranged on a line connected to an input end of a corresponding signal module to be input, and the filtering module is used to filter a signal input to the signal module to be input.

7. The anti-shoot-through circuit according to claim 6, characterized in that: The filtering module includes a resistor and a capacitor; One end of the resistor is used to receive a signal input to a target input end of the signal module to be input, the other end of the resistor is respectively connected to the target input end of the signal module to be input and one end of the capacitor, and the other end of the capacitor is grounded; The target input terminal is an input terminal of the gate module.

8. The anti-shoot-through circuit according to any one of claims 1 to 4, characterized in that: The first NAND gate module and the second NAND gate module are both NAND gate modules; The NAND gate module comprises an AND gate unit and a NOT gate unit, and the input end of the NOT gate unit is connected to the output end of the AND gate unit.

9. A topological circuit, characterized in that: include: a first switch module and a second switch module, wherein one end of the first switch module is used to receive a power supply voltage signal, the other end of the first switch module is connected to one end of the second switch module, the other end of the second switch module is grounded, and the first switch module and the second switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; A first NAND gate module, wherein a first input end of the first NAND gate module is used to receive a first input signal, and a second input end of the first NAND gate module is used to receive a second input signal; A second NAND gate module, wherein the first input end of the second NAND gate module is used to receive a first input signal, and the second input end of the second NAND gate module is used to receive a third input signal; A first AND gate module, wherein a first input end of the first AND gate module is connected to an output end of the first NAND gate module, and a second input end of the first AND gate module is used to receive a first input signal; A second AND gate module, wherein a first input end of the second AND gate module is connected to an output end of the second NAND gate module, and a second input end of the second AND gate module is used to receive the third input signal; A third AND gate module, wherein a first input end of the third AND gate module is connected to an output end of the second NAND gate module, and a second input end of the third AND gate module is connected to an output end of the first AND gate module; Among them, the output end of the second AND gate module is connected to the driving end of the first switch module, and the output end of the third AND gate module is connected to the driving end of the second switch module; or, the output end of the second AND gate module is connected to the driving end of the second switch module, and the output end of the third AND gate module is connected to the driving end of the first switch module.

10. The topological circuit according to claim 9, characterized in that: The topology circuit also includes: a third switch module and a fourth switch module, wherein one end of the third switch module is used to receive a power supply voltage signal, the other end of the third switch module is connected to one end of the fourth switch module, the other end of the fourth switch module is grounded, and the third switch module and the fourth switch module are both used to be turned on when the corresponding driving end receives a high-level voltage signal; A third NAND gate module, wherein the first input end of the third NAND gate module is used to receive the second input signal, and the second input end of the third NAND gate module is used to receive the fourth input signal; a fourth AND gate module, wherein a first input end of the fourth AND gate module is connected to an output end of the first NAND gate module, and a second input end of the fourth AND gate module is used to receive a second input signal; a fifth AND gate module, wherein a first input end of the fifth AND gate module is connected to an output end of the third NAND gate module, and a second input end of the fifth AND gate module is used to receive the fourth input signal; A sixth AND gate module, wherein a first input end of the sixth AND gate module is connected to an output end of the third NAND gate module, and a second input end of the sixth AND gate module is connected to an output end of the fourth AND gate module; Among them, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module; or, the output end of the fifth AND gate module is connected to the driving end of the third switch module, and the output end of the sixth AND gate module is connected to the driving end of the fourth switch module.

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