Single-chip microcomputer watchdog circuit with controllable period

Abstract

The utility model discloses a single-chip microcomputer watchdog circuit with a controllable period, and relates to the field of electronic circuits. Comprising a dog feeding circuit and a reset circuit, the dog feeding circuit comprises an input circuit and a counting circuit, the input circuit suppresses interference through RC filtering and diode clamping, the counting circuit adopts a 74LS161DC counting chip and is matched with an active crystal oscillator U2 and a control button with preset data to realize controllable period, and a counting space can be expanded in a cascading manner. The reset circuit is composed of a triode Q1, an SP708SEN voltage detection chip U3 and a manual reset circuit, the auxiliary power supply is connected to a voltage fault input pin of the U3, meanwhile, reset signals are transmitted to the input circuit at the same time, and the reset circuit has the functions of signal processing, voltage monitoring and synchronous reset. The circuit solves the problems that a traditional watchdog circuit is fixed in period, insufficient in interference resistance and the like, and has the advantages of being flexible and controllable in period, high in anti-interference capacity, capable of achieving multiple protection and convenient to maintain due to the modular design.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuits, and in particular to a microcontroller watchdog circuit with controllable cycle. Background Technology

[0002] In the fields of computers, communications, and automation, the electronic circuits of microcomputer systems composed of microcontrollers and embedded systems are often subject to interference from external electromagnetic fields. This interference causes data corruption and errors in various registers and memory within the chip, leading to program and electronic circuit malfunctions. Consequently, the entire system may cease normal operation and become stuck, potentially resulting in unpredictable consequences. Therefore, a watchdog circuit is used to monitor the running status of the MCU's internal program. In case of abnormalities such as program crashes or deadlocks, an automatic reset can be implemented to ensure system stability and reliability. The watchdog circuit is a key module for ensuring the stable operation of a microcontroller system. Its core function is to monitor the microcontroller's operating status and trigger a reset when the system malfunctions, preventing program crashes or system freezes. However, existing watchdog circuits generally have the following drawbacks:

[0003] Fixed reset cycle: The reset cycle of traditional circuits is determined by internal fixed parameters, which cannot be flexibly adjusted according to different application scenarios, thus limiting the applicability of the circuit; Insufficient anti-interference capability: The input signal is susceptible to high-frequency noise interference, which may lead to false reset and affect system stability; Limited functionality: It lacks a manual reset interface and power supply voltage monitoring mechanism, making it unable to cope with special situations such as sudden failures or power fluctuations. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a microcontroller watchdog circuit with controllable external cycle that can adapt to complex working conditions.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0006] A microcontroller watchdog circuit with controllable cycle, the key technology of which includes a watchdog feeding circuit and a reset circuit; the watchdog feeding circuit includes an input circuit and a counting circuit; the counting circuit includes a crystal oscillator clock circuit and a cycle control circuit;

[0007] The input terminal WD1 of the input circuit is connected to the dog feed pulse pin of the microcontroller; the output terminal of the input circuit is connected to the control chip U1 in the period control circuit; the output terminal of the crystal clock circuit is connected to U1; the output terminal of the period control circuit is connected to the input terminal of the reset circuit as the output terminal of the counting circuit; the negative output terminal of the reset circuit is connected to the MCU_RST pin of the microcontroller; the positive output terminal of the reset circuit is connected between capacitor C1 and resistor R2 in the input circuit.

[0008] Preferably, the input terminal of the input circuit is connected to capacitor C1, and the other end of C1 is connected to the CLR# and LOAD# pins of U1 through resistor R1; resistor R2 and diode D1 are connected in parallel across R1; R2 is connected in series with D1, and the negative terminal of D1 is connected to the CLR# pin of U1; the crystal clock circuit includes an active crystal oscillator U2; the VDD terminal of U2 is connected to the power supply, and the output terminal of U2 is connected to the CLK pin of U1; the period control circuit includes a control chip U1 and five control buttons, and the A, B, C, and D pins of U1 are respectively connected to the power supply VCC through switches; the ENP, VCC, and ENT pins of U1 are respectively connected to the power supply VCC; the RCD pin of U1, as the output terminal of the counting circuit, is connected to the input terminal of the reset circuit after passing through an RC rectification circuit.

[0009] Preferably, U1 is a 74LS161DC counter chip.

[0010] Preferably, the reset circuit includes a transistor Q1, a reset control chip U3, and a manual reset circuit; the input terminal of the reset circuit is connected to the base of Q1 through a resistor R4; the emitter of Q1 is grounded; the VCC pin of U3 is connected to the power supply VCC; the MR# pin of U3 is connected to a resistor R5, the collector of Q1, capacitor C3, capacitor C4, and the reset button K5, respectively; the other end of C4 is connected to the PFI pin of U3; the other ends of K5 and C3 are grounded; the other end of R5 is connected to the power supply VCC; the RESET pin of U3 is the positive output terminal of the reset circuit; the RESET# pin of U3 has an internal inverter and is the negative output terminal of the reset circuit.

[0011] Preferably, U3 is an SP708SEN voltage detection chip.

[0012] The beneficial effects of adopting the above technical solution are as follows:

[0013] This invention allows for changing the watchdog reset cycle via a manual button without altering the circuit structure or microcontroller program. Furthermore, it enables precise adjustment and expansion by cascading counter chips and replacing the crystal oscillator frequency, adapting to various needs.

[0014] This invention effectively filters out noise and reduces external interference through the filter circuit before the input circuit and the reset circuit, and connects the reset signal to the input circuit through feedback to achieve synchronous reset. Combined with the manual reset button, it can be applied to industrial production environments under complex working conditions. Attached Figure Description

[0015] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0016] Figure 1 This is a schematic diagram of a microcontroller watchdog circuit with a controllable cycle proposed in this utility model. Detailed Implementation

[0017] To make the above-mentioned objectives, features, and advantages of this utility model more apparent and understandable, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0018] A microcontroller watchdog circuit with controllable cycle includes a watchdog feeding circuit and a reset circuit; the watchdog feeding circuit includes an input circuit and a counting circuit; the counting circuit includes a crystal oscillator clock circuit and a cycle control circuit.

[0019] The input terminal WD1 of the input circuit is connected to the watchdog pulse pin of the microcontroller; the output terminal of the input circuit is connected to the control chip U1 in the period control circuit; the output terminal of the crystal clock circuit is connected to U1; the output terminal of the period control circuit is connected to the input terminal of the reset circuit as the output terminal of the counting circuit; the negative output terminal of the reset circuit is connected to the MCU_RST pin of the microcontroller; the positive output terminal of the reset circuit is connected between capacitor C1 and resistor R2 in the input circuit.

[0020] The input circuit's input terminal is connected to capacitor C1, with the other end of C1 connected to the CLR# and LOAD# pins of U1 via resistor R1. Resistor R2 and diode D1 are connected in parallel across R1. R2 is connected in series with D1, and the cathode of D1 is connected to the CLR# pin of U1. By establishing an RC filter circuit and diode clamping design, the input signal is detected, effectively suppressing high-frequency interference signals and preventing false triggering of resets.

[0021] The crystal clock circuit includes an active crystal oscillator U2; the VDD terminal of U2 is connected to the power supply, and the output terminal of U2 is connected to the CLK pin of U1; the cycle control circuit includes a control chip U1 and five control buttons; the A, B, C, and D pins of U1 are connected to the power supply VCC through switches; the ENP, VCC, and ENT pins of U1 are connected to the power supply VCC; the RCD pin of U1, as the output terminal of the counting circuit, is connected to the input terminal of the reset circuit after passing through an RC rectifier circuit.

[0022] U1 uses a 74LS161DC counter chip. CLK is the clock input, counting on the rising edge; CLR# is the asynchronous clear, with an internal inverter, active high. When CLR# is 1, the counter is immediately cleared; LOAD# is the synchronous preset, with an internal inverter, active high. When LOAD# = 1 and the rising edge of CLK arrives, the data from A, B, C, and D are loaded into the counter in parallel; ENP and ENT are enable, both active high. When both ENP and ENT are 1, the timer counts normally on the rising edge of the clock; A, B, C, and D are the data inputs, used for parallel data input when using the preset function; RCO is the carry output. When ENT = 1 and the counter reaches its maximum value, RCO outputs a high level to drive the reset circuit or cascade with the next counter chip to achieve multi-level counting.

[0023] The reset circuit includes transistor Q1, reset control chip U3, and a manual reset circuit. The input of the reset circuit is connected to the base of Q1 through resistor R4; the emitter of Q1 is grounded; the VCC pin of U3 is connected to the power supply VCC; the MR# pin of U3 is connected to resistor R5, the collector of Q1, capacitor C3, capacitor C4, and reset button K5 respectively; the other end of C4 is connected to the PFI pin of U3; the other ends of K5 and C3 are grounded; the other end of R5 is connected to the power supply VCC. U3 is an SP708SEN voltage detection chip. MR# is the voltage acquisition pin of U3. When the voltage is lower than a specified threshold, a reset signal is immediately triggered and output, which is used to connect to the manual reset circuit; RESET is the high-level reset output pin of U3, and also serves as the positive output of the reset circuit; RESET# is the low-level reset output pin, which is inverted from RESET and serves as the negative output of the reset circuit; the PFI pin is the voltage fault input pin. When the auxiliary power supply of the circuit fails, a reset signal is output in time to prevent the microcontroller from malfunctioning due to a watchdog circuit failure.

[0024] In practical applications, the microcontroller's watchdog signal is input to the watchdog circuit via the WD1 terminal. After passing through an RC filter circuit and diodes, high-frequency filtering is achieved to prevent noise interference and improve the stability and anti-interference capabilities of the watchdog circuit. Simultaneously, the input circuit receives the reset signal from the positive output of the reset circuit and outputs it to the CLR# and LOAD# terminals of the control chip U1, achieving synchronous reset and preventing reset cycle disruption. The counting circuit is reset simultaneously with the microcontroller's reset. The crystal clock circuit provides a stable clock pulse through the active crystal oscillator U2, achieving the smallest unit output of the cycle. The CLK pin of U1 receives the clock pulse signal and performs counting. Simultaneously, utilizing U1's preset and cascading functions, the preset data pin position is controlled via a button, and the required number of cycles is determined according to actual needs. When the 4-bit counter is insufficient, the CLK pin of another counting chip is cascaded through the RCO pin to expand the counting space. The expanded counting chip is still controlled by the button to set the preset data pin, and the CLR# and LOAD# pins are connected to the output of the input circuit to achieve synchronous clearing and synchronous reset functions. Through the selection of the active crystal oscillator and the coordination of the cycle control circuit, external manual control of the watchdog circuit reset cycle can be achieved, facilitating adaptation to various modes in specific applications.

[0025] The reset signal is connected to the reset circuit through an RC filter circuit, controlling the on / off state of transistor Q1, thereby controlling the level of pin MR#. When Q1 is off, the voltage at pin MR# is the voltage divided by the parallel connection of C3 and C4, at which point MR# is at a high level and no reset signal is triggered. When Q1 is on or the manual reset button K5 is pressed, MR# is at a low level, outputting a reset signal to achieve the reset function. When the VCC power supply experiences voltage fluctuations exceeding the low-voltage threshold, the PFI pin detects the low voltage and outputs a reset signal. This signal can be recorded via the output potential at PFO#, ensuring fault warning from the watchdog circuit and thus guaranteeing the normal operation of the microcontroller.

[0026] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A cycle-controllable watchdog circuit for a single-chip microcontroller, characterized in that It includes a watchdog circuit and a reset circuit; the watchdog circuit includes an input circuit and a counting circuit; the counting circuit includes a crystal clock circuit and a period control circuit. The input terminal WD1 of the input circuit is connected to the dog feed pulse pin of the microcontroller; the output terminal of the input circuit is connected to the control chip U1 in the periodic control circuit. The output of the crystal clock circuit is connected to U1; the output of the period control circuit is connected to the input of the reset circuit as the output of the counting circuit; the negative output of the reset circuit is connected to the MCU_RST pin of the microcontroller; the positive output of the reset circuit is connected between capacitor C1 and resistor R2 in the input circuit.

2. A cycle-controllable watchdog circuit for a single-chip microcontroller according to claim 1, characterized in that The input terminal of the input circuit is connected to capacitor C1, and the other end of C1 is connected to the CLR# and LOAD# pins of U1 through resistor R1; resistor R2 and diode D1 are connected in parallel across R1; R2 is connected in series with D1, and the negative terminal of D1 is connected to the CLR# pin of U1; the crystal clock circuit includes an active crystal oscillator U2; the VDD terminal of U2 is connected to the power supply, and the output terminal of U2 is connected to the CLK pin of U1; the period control circuit includes a control chip U1 and five control buttons, and the A, B, C, and D pins of U1 are connected to the power supply VCC through switches; the ENP, VCC, and ENT pins of U1 are connected to the power supply VCC; the RCD pin of U1, as the output terminal of the counting circuit, is connected to the input terminal of the reset circuit after passing through an RC rectifier circuit.

3. A cycle-controllable watchdog circuit for a single chip microcontroller as claimed in claim 1, characterized in that The U1 is a 74LS161DC counter chip.

4. A cycle-controllable watchdog circuit for a single-chip microcontroller according to claim 1, characterized in that The reset circuit includes a transistor Q1, a reset control chip U3, and a manual reset circuit. The input terminal of the reset circuit is connected to the base of Q1 through a resistor R4. The emitter of Q1 is grounded. The VCC pin of U3 is connected to the power supply VCC. The MR# pin of U3 is connected to a resistor R5, the collector of Q1, capacitor C3, capacitor C4, and the reset button K5. The other end of C4 is connected to the PFI pin of U3. The other ends of K5 and C3 are grounded. The other end of R5 is connected to the power supply VCC. The RESET pin of U3 is the positive output terminal of the reset circuit. The RESET# pin of U3 has an internal inverter and is the negative output terminal of the reset circuit.

5. A cycle-controllable watchdog circuit for a single-chip microcontroller according to claim 4, characterized in that The U3 is an SP708SEN voltage detection chip.

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