Three-phase hardware current detection protection circuit

Abstract

The embodiment of the utility model provides a three-phase hardware current detection protection circuit, which comprises a U-phase detection protection circuit, a V-phase detection protection circuit and a W-phase detection protection circuit, and is characterized in that a PWMUL signal input port of a driving chip is connected with a main control chip through the U-phase detection protection circuit; the U-phase detection protection circuit is connected with a sampling end of the U-phase sampling resistor R4, a PWMVL signal input port of the driving chip is connected with the main control chip through the V-phase detection protection circuit, the V-phase detection protection circuit is connected with a sampling end of the V-phase sampling resistor R6, a PWMWL signal input port of the driving chip is connected with the main control chip through the W-phase detection protection circuit, and the W-phase detection protection circuit is connected with a sampling end of the V-phase sampling resistor R6. And the W-phase detection protection circuit is connected with the sampling end of the W-phase sampling resistor R7. According to the utility model, the three paths of current can be respectively detected and controlled, the current protection is effectively carried out, the response speed is fast, the reliability is high, and the cost is low.

Description

Technical Field

[0001] This utility model relates to the field of servo drive control hardware technology, and more specifically, to a three-phase hardware current detection and protection circuit. Background Technology

[0002] For common low-cost applications or other special scenarios, relatively simple driver chips are usually selected. These driver chips generally only include basic functions such as gate driving and lack overcurrent protection. In such cases, a common method to add current protection is to monitor the bus / phase current through the ADC (Analog-to-digital converter) acquisition port of the main control chip such as an MCU (Micro Controller Unit) or DSP (Digital Signal Processor). The current amplitude is then limited by software, and the control signal is blocked when the current exceeds the protection threshold, thereby protecting the hardware circuit, external power supply, and load. However, using software to monitor and control current requires the main control chip for servo control to handle not only ADC data but also other tasks such as communication, motor control, and logic decision-making. Therefore, in most application scenarios, the main control chip lacks the capability to sample and protect against current at high frequencies. This leads to delays in software-implemented current protection, especially when power devices fail, causing shoot-through. Software protection typically has a microsecond-level response time, which is generally insufficient to prevent further damage. Furthermore, the main control chip is usually located a considerable distance from the drive circuit and sampling circuit. This makes the analog signals generated by the sampling circuit susceptible to interference over long distances, potentially causing false triggering of protection mechanisms. Utility Model Content

[0003] This application provides a three-phase hardware current detection and protection circuit, which can realize the separate detection and control of three currents, effectively protect the current, has a fast response speed, avoids false triggering of protection, has high reliability, and low cost.

[0004] According to an embodiment of this application, a three-phase hardware current detection and protection circuit is provided. The PWM_UH, PWM_VH, and PWM_WH signal input ports of the driver chip are electrically connected to the main control chip. The gate of the upper U-phase transistor Q2 of the driver chip is electrically connected to the G_UH signal output port of the driver chip. The gate of the lower U-phase transistor Q5 of the driver chip is electrically connected to the G_UL signal output port of the driver chip. The source of the upper U-phase transistor Q2 is electrically connected to the drain of the lower U-phase transistor Q5. The source of the lower U-phase transistor Q5 is connected to the sampling terminal of the U-phase sampling resistor R4. The gate of the upper V-phase transistor Q3 of the driver chip is electrically connected to the G_VH signal output port of the driver chip. The gate of the lower V-phase transistor Q6 of the driver chip is electrically connected to the G_VL signal output port of the driver chip. The source of the upper V-phase transistor Q3 is electrically connected to the drain of the lower V-phase transistor Q6. The source of the lower V-phase transistor Q6 is connected to the sampling terminal of the V-phase sampling resistor R6. The gate of the upper W-phase transistor Q4 of the driver chip is electrically connected to the G_WH signal output port of the driver chip. The gate of the lower W-phase transistor Q7 of the driver chip is electrically connected to the G_WL signal output port of the driver chip. The source of the upper W-phase transistor Q4 is electrically connected to the drain of the lower W-phase transistor Q7. The source of the lower W-phase transistor Q7 is connected to the sampling terminal of the W-phase sampling resistor R7. The drains of the upper U-phase transistor Q2, the upper V-phase transistor Q3, and the upper W-phase transistor Q4 are respectively connected to the positive terminal of the bus. The other ends of the sampling resistors R4, R6, and R7 are respectively connected to the negative terminal of the bus.

[0005] The three-phase hardware current detection and protection circuit includes: a U-phase detection and protection circuit, a V-phase detection and protection circuit, and a W-phase detection and protection circuit. The PWM_UL signal input port of the driver chip is connected to the main control chip through the U-phase detection and protection circuit, and the U-phase detection and protection circuit is connected to the sampling terminal of the U-phase sampling resistor R4. The PWM_VL signal input port of the driver chip is connected to the main control chip through the V-phase detection and protection circuit, and the V-phase detection and protection circuit is connected to the sampling terminal of the V-phase sampling resistor R6. The PWM_WL signal input port of the driver chip is connected to the main control chip through the W-phase detection and protection circuit, and the W-phase detection and protection circuit is connected to the sampling terminal of the W-phase sampling resistor R7.

[0006] In some embodiments of this application, the U-phase detection and protection circuit includes a U-phase NMOS transistor Q1, a U-phase diode D1, a U-phase NPN transistor Q8, and a U-phase RC filter circuit. The source of the U-phase NMOS transistor Q1 is electrically connected to the U-phase lower transistor PWM output port of the main control chip. The drain of the U-phase NMOS transistor Q1 is connected to the cathode of the U-phase diode D1. The anode of the U-phase diode D1 is electrically connected to the PWM_UL signal input port of the driver chip. The base of the U-phase NPN transistor Q8 is connected to the sampling terminal of the U-phase sampling resistor R4 through the U-phase RC filter circuit. The collector of the U-phase NPN transistor Q8 is electrically connected to the PWM_UL signal input port of the driver chip. The emitter of the U-phase NPN transistor Q8 is connected to the negative terminal of the bus.

[0007] In some embodiments of this application, the U-phase RC filter circuit includes a resistor R5 and a capacitor C1. One end of the resistor R5 is connected to the base of the U-phase NPN transistor Q8, and the other end of the resistor R5 is connected to the sampling terminal of the U-phase sampling resistor R4 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the emitter of the U-phase NPN transistor Q8.

[0008] In some embodiments of this application, the U-phase detection and protection circuit further includes resistors R1, R2, and R3. The two ends of resistor R1 are connected to the IO port level V1 of the main control chip and the source of the U-phase NMOS transistor Q1, respectively. The two ends of resistor R3 are connected to the IO port level V1 and the gate of the U-phase NMOS transistor Q1, respectively. One end of resistor R2 is connected to the anode of the U-phase diode D1 and the collector of the U-phase NPN transistor Q8, respectively. The other end of resistor R2 is connected to the voltage recognition level V2 of the driver chip.

[0009] In some embodiments of this application, the V-phase detection and protection circuit includes a V-phase NMOS transistor Q10, a V-phase diode D2, a V-phase NPN transistor Q9, and a V-phase RC filter circuit. The source of the V-phase NMOS transistor Q10 is electrically connected to the V-phase lower PWM output port of the main control chip. The drain of the V-phase NMOS transistor Q10 is connected to the cathode of the V-phase diode D2. The anode of the V-phase diode D2 is electrically connected to the PWM_VL signal input port of the driver chip. The base of the V-phase NPN transistor Q9 is connected to the sampling terminal of the V-phase sampling resistor R6 through the V-phase RC filter circuit. The collector of the V-phase NPN transistor Q9 is electrically connected to the PWM_VL signal input port of the driver chip. The emitter of the V-phase NPN transistor Q9 is connected to the negative terminal of the bus.

[0010] In some embodiments of this application, the V-phase RC filter circuit includes a resistor R8 and a capacitor C2. One end of the resistor R8 is connected to the base of the V-phase NPN transistor Q9, and the other end of the resistor R8 is connected to the sampling terminal of the V-phase sampling resistor R6 and one end of the capacitor C2. The other end of the capacitor C2 is connected to the emitter of the V-phase NPN transistor Q9.

[0011] In some embodiments of this application, the V-phase detection and protection circuit further includes resistors R11, R10, and R9. The two ends of resistor R11 are respectively connected to the IO port level V1 of the main control chip and the source of the V-phase NMOS transistor Q10. The two ends of resistor R9 are respectively connected to the IO port level V1 and the gate of the V-phase NMOS transistor Q10. One end of resistor R10 is respectively connected to the anode of the V-phase diode D2 and the collector of the V-phase NPN transistor Q9. The other end of resistor R10 is connected to the voltage recognition level V2 of the driver chip.

[0012] In some embodiments of this application, the W-phase detection and protection circuit includes a W-phase NMOS transistor Q12, a W-phase diode D3, a W-phase NPN transistor Q11, and a W-phase RC filter circuit. The source of the W-phase NMOS transistor Q12 is electrically connected to the W-phase lower transistor PWM output port of the main control chip. The drain of the W-phase NMOS transistor Q12 is connected to the cathode of the W-phase diode D3. The anode of the W-phase diode D3 is electrically connected to the PWM_WL signal input port of the driver chip. The base of the W-phase NPN transistor Q11 is connected to the sampling terminal of the W-phase sampling resistor R7 through the W-phase RC filter circuit. The collector of the W-phase NPN transistor Q11 is electrically connected to the PWM_WL signal input port of the driver chip. The emitter of the W-phase NPN transistor Q11 is connected to the negative terminal of the bus.

[0013] In some embodiments of this application, the W-phase RC filter circuit includes a resistor R12 and a capacitor C3. One end of the resistor R12 is connected to the base of the W-phase NPN transistor Q11, and the other end of the resistor R12 is connected to the sampling terminal of the W-phase sampling resistor R7 and one end of the capacitor C3. The other end of the capacitor C3 is connected to the emitter of the W-phase NPN transistor Q11.

[0014] In some embodiments of this application, the W-phase detection and protection circuit further includes resistors R15, R14, and R13. The two ends of resistor R15 are respectively connected to the IO port level V1 of the main control chip and the source of the W-phase NMOS transistor Q12. The two ends of resistor R13 are respectively connected to the IO port level V1 and the gate of the W-phase NMOS transistor Q12. One end of resistor R14 is respectively connected to the anode of the W-phase diode D3 and the collector of the W-phase NPN transistor Q11. The other end of resistor R14 is connected to the voltage recognition level V2 of the driver chip.

[0015] The beneficial effects of the embodiments of this application are as follows:

[0016] By designing U-phase, V-phase, and W-phase detection and protection circuits, three current paths can be detected and controlled independently. Each phase detection and protection circuit employs a combination of diodes, transistors, and MOSFETs. When overcurrent occurs in any phase, causing a voltage rise in the sampling resistor, the lower transistor in that phase's detection and protection circuit can be turned off, thereby controlling the output current and protecting the power supply, inverter bridge circuit, and external load. Simultaneously, the current limiting threshold of each phase detection and protection circuit can be set by adjusting the sampling resistor and base resistor. The capacitor in the RC filter circuit can filter out the effects of sudden spikes during power device switching, preventing false triggering of the protection. Compared to traditional software-based acquisition and control closed-loop systems, this application offers faster response speed, higher reliability, and a simpler, lower-cost protection circuit. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 The circuit diagram is provided for an embodiment of this application of a three-phase hardware current detection and protection circuit. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this utility model.

[0020] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, it may include a series of structures, without being limited to the structures listed, but may optionally include structures not listed, or may optionally include other components inherent to these structures.

[0021] This application discloses a three-phase hardware current detection and protection circuit, mainly used for inverter bridge current protection. It can realize the separate detection and control of three currents, effectively protect the current, and avoid false triggering of the protection. Detailed descriptions follow.

[0022] Figure 1 This paper illustrates a three-phase hardware current detection and protection circuit according to an embodiment of this application. It should be noted that... Figure 1 Only the structure of the sampling circuit is shown; the rest of the main circuitry (such as the inverter bridge circuit) has been simplified. Figure 1As shown, the driver chip in this application includes a PWM_UH signal input port, a PWM_VH signal input port, a PWM_WH signal input port, a PWM_UL signal input port, a PWM_VL signal input port, a PWM_WL signal input port, a G_UH signal output port, a G_VH signal output port, a G_WH signal output port, a G_UL signal output port, a G_VL signal output port, and a G_WL signal output port. The input ports for the PWM_UL, PWM_VL, and PWM_WL signals are the PWM signal input terminals of the driver chip. Among them, the input ports for the PWM_UH, PWM_VH, and PWM_WH signals of the driver chip are directly electrically connected to the main control chip. The output ports for the G_UH, G_VH, G_WH, G_UL, G_VL, and G_WL signals are the pulse signal output terminals of the driver chip. The sampling circuit in this application mainly includes U-phase upper transistor Q2, U-phase lower transistor Q5, U-phase sampling resistor R4, V-phase upper transistor Q3, V-phase lower transistor Q6, V-phase sampling resistor R6, W-phase upper transistor Q4, W-phase lower transistor Q7, and W-phase sampling resistor R7. Among them, U-phase upper transistor Q2 and U-phase lower transistor Q5 constitute U-phase inverter bridge, V-phase upper transistor Q3 and V-phase lower transistor Q6 constitute V-phase inverter bridge, and W-phase upper transistor Q4 and W-phase lower transistor Q7 constitute W-phase inverter bridge. Specifically, the gate of the upper U-phase transistor Q2 of the driver chip is electrically connected to the G_UH signal output port of the driver chip; the gate of the lower U-phase transistor Q5 of the driver chip is electrically connected to the G_UL signal output port of the driver chip; the source of the upper U-phase transistor Q2 is electrically connected to the drain of the lower U-phase transistor Q5; and the source of the lower U-phase transistor Q5 is connected to the sampling terminal of the U-phase sampling resistor R4. Similarly, the gate of the upper V-phase transistor Q3 of the driver chip is electrically connected to the G_VH signal output port of the driver chip; the gate of the lower V-phase transistor Q6 of the driver chip is electrically connected to the G_VL signal output port of the driver chip; the source of the upper V-phase transistor Q3 is electrically connected to the drain of the lower V-phase transistor Q6; and the source of the lower V-phase transistor Q6 is connected to the sampling terminal of the U-phase sampling resistor R4. The sampling terminal of sampling resistor R6 is connected; the gate of the upper W-phase transistor Q4 of the driver chip is electrically connected to the G_WH signal output port of the driver chip, the gate of the lower W-phase transistor Q7 of the driver chip is electrically connected to the G_WL signal output port of the driver chip, the source of the upper W-phase transistor Q4 is electrically connected to the drain of the lower W-phase transistor Q7, and the source of the lower W-phase transistor Q7 is connected to the sampling terminal of the sampling resistor R7 of the W phase; in addition, the drains of the upper U-phase transistor Q2, the upper V-phase transistor Q3, and the upper W-phase transistor Q4 are respectively connected to the positive terminal of the bus, and the other end of the sampling resistor R4 of the U phase, the other end of the sampling resistor R6 of the V phase, and the other end of the sampling resistor R7 of the W phase are respectively connected to the negative terminal of the bus.

[0023] like Figure 1 As shown, the three-phase hardware current detection and protection circuit in this application includes: a U-phase detection and protection circuit 1, a V-phase detection and protection circuit 2, and a W-phase detection and protection circuit 3. Specifically, the PWM_UL signal input port of the driver chip is connected to the main control chip through the U-phase detection and protection circuit 1, and the U-phase detection and protection circuit 1 is connected to the sampling terminal of the U-phase sampling resistor R4; the PWM_VL signal input port of the driver chip is connected to the main control chip through the V-phase detection and protection circuit 2, and the V-phase detection and protection circuit 2 is connected to the sampling terminal of the V-phase sampling resistor R6; the PWM_WL signal input port of the driver chip is connected to the main control chip through the W-phase detection and protection circuit 3, and the W-phase detection and protection circuit 3 is connected to the sampling terminal of the W-phase sampling resistor R7. Thus, through the design of the U-phase detection and protection circuit 1, the V-phase detection and protection circuit 2, and the W-phase detection and protection circuit 3, the three currents are detected and controlled respectively to effectively protect the three-phase hardware current overcurrent, with fast response and low cost.

[0024] In some embodiments, such as Figure 1 As shown, the U-phase detection and protection circuit 1 includes a U-phase NMOS transistor Q1, a U-phase diode D1, a U-phase NPN transistor Q8, and a U-phase RC filter circuit. Specifically, the source of the U-phase NMOS transistor Q1 is electrically connected to the U-phase lower transistor PWM output port of the main control chip; the drain of the U-phase NMOS transistor Q1 is connected to the cathode of the U-phase diode D1; the anode of the U-phase diode D1 is electrically connected to the PWM_UL signal input port of the driver chip; the base of the U-phase NPN transistor Q8 is connected to the sampling terminal of the U-phase sampling resistor R4 through the U-phase RC filter circuit; the collector of the U-phase NPN transistor Q8 is electrically connected to the PWM_UL signal input port of the driver chip; and the emitter of the U-phase NPN transistor Q8 is connected to the negative terminal of the bus. In the specific implementation, the U-phase RC filter circuit includes a resistor R5 and a capacitor C1. One end of the resistor R5 is connected to the base of the U-phase NPN transistor Q8, and the other end of the resistor R5 is connected to the sampling terminal of the U-phase sampling resistor R4 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the emitter of the U-phase NPN transistor Q8. Furthermore, the U-phase detection and protection circuit 1 also includes resistors R1, R2, and R3. The two ends of resistor R1 are connected to the I / O port level V1 of the main control chip and the source of the U-phase NMOS transistor Q1, respectively. The two ends of resistor R3 are connected to the I / O port level V1 and the gate of the U-phase NMOS transistor Q1, respectively. One end of resistor R2 is connected to the anode of the U-phase diode D1 and the collector of the U-phase NPN transistor Q8, respectively. The other end of resistor R2 is connected to the driver chip voltage recognition level V2. It should be noted that in this application, the driver chip voltage recognition level V2 refers to the level adapted to the driver chip's recognition voltage.

[0025] like Figure 1As shown, when the circuit samples, the voltage across the sampling resistor R4 in phase U increases with the increase of the current I. At this time, the base current flowing through the NPN transistor Q8 in phase U... Where R4 is the resistance value of the U-phase sampling resistor R4, and R5 is the resistance value of the resistor R5. This is the voltage between the base and emitter of the U-phase NPN transistor Q8. The collector circuit controls the operating state of the U-phase NPN transistor Q8. When the voltage increases to a certain level, the U-phase NPN transistor Q8 will be in a saturated conduction state, thus pulling its collector voltage low. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the U-phase NMOS transistor Q1 are equal, and Q1 is cut off. However, under the action of the U-phase diode D1, the drain voltage of Q1 remains high. In other words, the cathode of diode D1 is high, while the anode is low under the influence of the U-phase NPN transistor Q8. The U-phase diode D1 prevents the I / O port level V1 of the main control chip from being pulled low when Q8 is conducting, thus avoiding damage to the I / O port. In this situation, the PWM_UL signal input port of the driver chip remains low. If the PWM signal output by the main control chip is low, the source voltage of the U-phase NMOS transistor Q1 is 0, the gate voltage is high, and Q1 is turned on. The drain voltage of Q1 remains high, the same as when the PWM signal is high. Therefore, when an overcurrent occurs causing the U-phase NPN transistor Q8 to operate in saturation, the input signal of the driver chip will be pulled low, setting its gate drive level G_UL low. This controls the U-phase lower transistor Q5 to turn off, reducing the current flowing through the U-phase sampling resistor R4, thereby controlling the output current and protecting the power supply, inverter bridge circuit, and external load.

[0026] when When the current is insufficient, the U-phase NPN transistor Q8 will operate in the off state. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the U-phase NMOS transistor Q1 are equal, and Q1 is off, with its drain voltage at a high potential. The operating state of the U-phase diode D1 depends on the voltage of the driver chip's voltage recognition level V2. Under normal circumstances, the driver chip's voltage recognition level V2 is higher than the IO port level V1. In this case, the off-state U-phase NMOS transistor Q1 prevents current from flowing back into the main control chip's IO port to avoid damage, and PWM_UL is high. If the PWM signal output by the main control chip is low, the U-phase NMOS transistor Q1 is in the conducting state, and the potential of PWM_UL is pulled low through the U-phase diode D1. Therefore, when no overcurrent occurs, the logic level of PWM_UL remains consistent with the PWM output of the main control chip, and the lower U-phase transistor Q5 is normally controlled to switch, completing the inverter operation.

[0027] In addition, the current limiting threshold of the U-phase detection and protection circuit 1 is determined by the U-phase sampling resistor R4 and the base resistor R5, while the capacitor C1 can filter out the influence of sudden spikes when the power device switches, thus avoiding false triggering of the protection.

[0028] In other embodiments, such as Figure 1 As shown, the V-phase detection and protection circuit 2 includes a V-phase NMOS transistor Q10, a V-phase diode D2, a V-phase NPN transistor Q9, and a V-phase RC filter circuit. Specifically, the source of the V-phase NMOS transistor Q10 is electrically connected to the V-phase lower transistor PWM output port of the main control chip; the drain of the V-phase NMOS transistor Q10 is connected to the cathode of the V-phase diode D2; the anode of the V-phase diode D2 is electrically connected to the PWM_VL signal input port of the driver chip; the base of the V-phase NPN transistor Q9 is connected to the sampling terminal of the V-phase sampling resistor R6 through the V-phase RC filter circuit; the collector of the V-phase NPN transistor Q9 is electrically connected to the PWM_VL signal input port of the driver chip; and the emitter of the V-phase NPN transistor Q9 is connected to the negative terminal of the bus. In the specific implementation process, the V-phase RC filter circuit includes a resistor R8 and a capacitor C2. One end of the resistor R8 is connected to the base of the V-phase NPN transistor Q9, and the other end of the resistor R8 is connected to the sampling terminal of the V-phase sampling resistor R6 and one end of the capacitor C2. The other end of the capacitor C2 is connected to the emitter of the V-phase NPN transistor Q9. Furthermore, the V-phase detection and protection circuit 2 also includes resistors R11, R10, and R9. The two ends of the resistor R11 are connected to the I / O port level V1 of the main control chip and the source of the V-phase NMOS transistor Q10, respectively. The two ends of the resistor R9 are connected to the I / O port level V1 and the gate of the V-phase NMOS transistor Q10, respectively. One end of the resistor R10 is connected to the anode of the V-phase diode D2 and the collector of the V-phase NPN transistor Q9, respectively. The other end of the resistor R10 is connected to the voltage recognition level V2 of the driver chip.

[0029] like Figure 1 As shown, when the circuit samples, the voltage across the sampling resistor R6 in phase V increases with the increase of the current I. At this time, the base current flowing through the NPN transistor Q9 in phase V... Where R6 is the resistance value of the V-phase sampling resistor R6, and R8 is the resistance value of the resistor R8. This is the voltage between the base and emitter of the V-phase NPN transistor Q9. The collector circuit controls the operating state of the V-phase NPN transistor Q9. When the voltage increases to a certain level, the V-phase NPN transistor Q9 will be in a saturated conduction state, thus pulling its collector voltage low. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the V-phase NMOS transistor Q10 are equal, and Q10 is cut off. However, under the action of the V-phase diode D2, the drain voltage of Q10 remains high. In other words, the cathode of the V-phase diode D2 is high, while the anode is low under the action of the V-phase NPN transistor Q9. The V-phase diode D2 prevents the I / O port level V1 of the main control chip from being pulled low when the V-phase NPN transistor Q9 is conducting, thus preventing damage to the I / O port. In this situation, the PWM_VL signal input port of the driver chip remains low. If the PWM signal output by the main control chip is low, the source voltage of the V-phase NMOS transistor Q10 is 0, the gate voltage is high, and Q10 is turned on. The drain voltage of Q10 remains high, the same as when the PWM signal is high. Therefore, when an overcurrent occurs causing the V-phase NPN transistor Q9 to operate in saturation, the input signal of the driver chip will be pulled low, setting its gate drive level G_VL low. This controls the V-phase lower transistor Q6 to turn off, reducing the current flowing through the V-phase sampling resistor R6, thereby controlling the output current and protecting the power supply, inverter bridge circuit, and external load.

[0030] when When the current is insufficient, the V-phase NPN transistor Q9 will operate in the off state. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the V-phase NMOS transistor Q10 are equal, and Q10 is off, with its drain voltage at a high potential. The operating state of the V-phase diode D2 depends on the voltage of the driver chip's voltage recognition level V2. Under normal circumstances, the driver chip's voltage recognition level V2 is higher than the IO port level V1. In this case, the off-state V-phase NMOS transistor Q10 prevents current from flowing back into the main control chip's IO port, thus avoiding damage, and PWM_VL is high. If the PWM signal output by the main control chip is low, the V-phase NMOS transistor Q10 is in the conducting state, and the potential of PWM_VL is pulled low through the V-phase diode D2. Therefore, when no overcurrent occurs, the logic level of PWM_VL remains consistent with the PWM output of the main control chip, and the lower V-phase transistor Q6 is normally controlled to switch, completing the inverter operation.

[0031] In addition, the current limiting threshold of the V-phase detection protection circuit 2 is determined by the V-phase sampling resistor R6 and the base resistor R8, while the capacitor C2 can filter out the influence of sudden spikes when the power device switches, thus avoiding false triggering of the protection.

[0032] In other embodiments, such as Figure 1As shown, the W-phase detection and protection circuit 3 includes a W-phase NMOS transistor Q12, a W-phase diode D3, a W-phase NPN transistor Q11, and a W-phase RC filter circuit. Specifically, the source of the W-phase NMOS transistor Q12 is electrically connected to the W-phase lower transistor PWM output port of the main control chip; the drain of the W-phase NMOS transistor Q12 is connected to the cathode of the W-phase diode D3; the anode of the W-phase diode D3 is electrically connected to the PWM_WL signal input port of the driver chip; the base of the W-phase NPN transistor Q11 is connected to the sampling terminal of the W-phase sampling resistor R7 through the W-phase RC filter circuit; the collector of the W-phase NPN transistor Q11 is electrically connected to the PWM_WL signal input port of the driver chip; and the emitter of the W-phase NPN transistor Q11 is connected to the negative terminal of the bus. In the specific implementation process, the W-phase RC filter circuit includes a resistor R12 and a capacitor C3. One end of the resistor R12 is connected to the base of the W-phase NPN transistor Q11, and the other end of the resistor R12 is connected to the sampling terminal of the W-phase sampling resistor R7 and one end of the capacitor C3. The other end of the capacitor C3 is connected to the emitter of the W-phase NPN transistor Q11. Furthermore, the W-phase detection and protection circuit 3 also includes resistors R15, R14, and R13. The two ends of the resistor R15 are connected to the I / O port level V1 of the main control chip and the source of the W-phase NMOS transistor Q12, respectively. The two ends of the resistor R13 are connected to the I / O port level V1 and the gate of the W-phase NMOS transistor Q12, respectively. One end of the resistor R14 is connected to the anode of the W-phase diode D3 and the collector of the W-phase NPN transistor Q11, respectively. The other end of the resistor R14 is connected to the voltage recognition level V2 of the driver chip.

[0033] like Figure 1 As shown, when the circuit samples, the voltage across the sampling resistor R7 in phase W increases with the increase of the current I. At this time, the base current flowing through the NPN transistor Q11 in phase W... Where R7 is the resistance value of the W-phase sampling resistor R7, R 12 The resistance value of resistor R12 is... This is the voltage between the base and emitter of the W-phase NPN transistor Q11. The collector circuit controls the operating state of the W-phase NPN transistor Q11. When the voltage increases to a certain level, the W-phase NPN transistor Q11 will be in a saturated conduction state, thus pulling its collector voltage low. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the W-phase NMOS transistor Q12 will be equal, and Q12 will be cut off. However, under the action of the W-phase diode D3, the drain voltage of Q12 remains high. That is, the cathode of the W-phase diode D3 is high, while the anode is low due to the action of the W-phase NPN transistor Q11. The W-phase diode D3 prevents the I / O port level V1 of the main control chip from being pulled low when the W-phase NPN transistor Q11 is conducting, thus avoiding damage to the I / O port. In this situation, the PWM_WL signal input port of the driver chip remains low. If the PWM signal output by the main control chip is low, the source voltage of the W-phase NMOS transistor Q12 is 0, the gate voltage is high, and the W-phase NMOS transistor Q12 is turned on. The drain voltage of the W-phase NMOS transistor Q12 remains high, the same as when the PWM signal is high. Therefore, when an overcurrent occurs and causes the W-phase NPN transistor Q11 to operate in saturation, the input signal of the driver chip will be pulled low, causing its gate drive level G_WL to go low, controlling the lower W-phase transistor Q7 to turn off, thereby reducing the current flowing through the W-phase sampling resistor R7, thus controlling the output current and protecting the power supply, inverter bridge circuit, and external load.

[0034] when When the current is insufficient, the W-phase NPN transistor Q11 will operate in the off state. At this time, if the PWM signal output by the main control chip is high, the gate and source voltages of the W-phase NMOS transistor Q12 are equal, and Q12 is off, with its drain voltage at a high potential. The operating state of the W-phase diode D3 depends on the voltage of the driver chip's voltage recognition level V2. Under normal circumstances, the driver chip's voltage recognition level V2 is higher than the IO port level V1. In this case, the off-state W-phase NMOS transistor Q12 prevents current from flowing back into the main control chip's IO port, thus avoiding damage; PWM_WL is high. If the PWM signal output by the main control chip is low, the W-phase NMOS transistor Q12 is in the conducting state, and the potential of PWM_WL is pulled low through the W-phase diode D3. Therefore, when no overcurrent occurs, the logic level of PWM_WL remains consistent with the PWM output of the main control chip, and the lower W-phase transistor Q7 is normally controlled to switch, completing the inverter operation.

[0035] In addition, the current limiting threshold of the W-phase detection protection circuit 3 is determined by the W-phase sampling resistor R7 and the base resistor R12, while the capacitor C3 can filter out the influence of sudden spikes when the power device switches, thus avoiding false triggering of the protection.

[0036] In summary, this application discloses a three-phase hardware current detection and protection circuit. Through the design of U-phase, V-phase, and W-phase detection and protection circuits, three currents can be detected and controlled separately. Each phase detection and protection circuit uses a combination of diodes, transistors, and MOSFETs. When an overcurrent occurs in any phase, causing a voltage rise in the sampling resistor, the lower transistor in that phase's detection and protection circuit can be turned off, thereby controlling the output current and protecting the power supply, inverter bridge circuit, and external load. Simultaneously, the current limiting threshold of each phase detection and protection circuit can be set by adjusting the sampling resistor and base resistor. The capacitor in the RC filter circuit can filter out the effects of sudden spikes during power device switching, preventing false triggering of the protection. Compared to traditional software acquisition and control closed-loop systems, this application offers faster response speed, higher reliability, and a simpler protection circuit with lower cost.

[0037] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the components shown in the drawings are not necessarily essential for implementing this utility model. In the description of the embodiments of this application, unless otherwise expressly specified and limited, the terms "connected" or "linked" should be interpreted broadly. For example, it can refer to a fixed connection, a detachable connection, or an integral connection; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; and it can refer to the internal connection of two components.

[0038] Finally, it should be noted that the above-described embodiments are merely specific implementations of this utility model, used to illustrate the technical solution of this utility model, and not to limit it. The protection scope of this utility model is not limited thereto. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this utility model. These modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope described in the claims.

Claims

1. A three-phase hardware current detection protection circuit, characterized by, The PWM_UH, PWM_VH, and PWM_WH signal input ports of the driver chip are electrically connected to the main control chip. The gate of the upper U-phase transistor Q2 of the driver chip is electrically connected to the G_UH signal output port of the driver chip. The gate of the lower U-phase transistor Q5 of the driver chip is electrically connected to the G_UL signal output port of the driver chip. The source of the upper U-phase transistor Q2 is electrically connected to the drain of the lower U-phase transistor Q5. The source of the lower U-phase transistor Q5 is connected to the sampling terminal of the U-phase sampling resistor R4. The gate of the upper V-phase transistor Q3 of the driver chip is electrically connected to the G_VH signal output port of the driver chip. The gate of the lower V-phase transistor Q6 of the driver chip is electrically connected to the G_VL signal output port of the driver chip. The source of the upper V-phase transistor Q3 is electrically connected to the sampling terminal of the sampling resistor R4. The drain of the lower V-phase transistor Q6 is electrically connected, and the source of the lower V-phase transistor Q6 is connected to the sampling terminal of the V-phase sampling resistor R6. The gate of the upper W-phase transistor Q4 of the driver chip is electrically connected to the G_WH signal output port of the driver chip. The gate of the lower W-phase transistor Q7 of the driver chip is electrically connected to the G_WL signal output port of the driver chip. The source of the upper W-phase transistor Q4 is electrically connected to the drain of the lower W-phase transistor Q7. The source of the lower W-phase transistor Q7 is connected to the sampling terminal of the W-phase sampling resistor R7. The drains of the upper U-phase transistor Q2, the upper V-phase transistor Q3, and the upper W-phase transistor Q4 are respectively connected to the positive terminal of the bus. The other ends of the sampling resistors R4, R6, and R7 are respectively connected to the negative terminal of the bus. The three-phase hardware current detection and protection circuit includes: a U-phase detection and protection circuit, a V-phase detection and protection circuit, and a W-phase detection and protection circuit. The PWM_UL signal input port of the driver chip is connected to the main control chip through the U-phase detection and protection circuit, and the U-phase detection and protection circuit is connected to the sampling terminal of the U-phase sampling resistor R4. The PWM_VL signal input port of the driver chip is connected to the main control chip through the V-phase detection and protection circuit, and the V-phase detection and protection circuit is connected to the sampling terminal of the V-phase sampling resistor R6. The PWM_WL signal input port of the driver chip is connected to the main control chip through the W-phase detection and protection circuit, and the W-phase detection and protection circuit is connected to the sampling terminal of the W-phase sampling resistor R7.

2. The three-phase hardware current detection protection circuit of claim 1, wherein, The U-phase detection and protection circuit includes a U-phase NMOS transistor Q1, a U-phase diode D1, a U-phase NPN transistor Q8, and a U-phase RC filter circuit. The source of the U-phase NMOS transistor Q1 is electrically connected to the U-phase lower transistor PWM output port of the main control chip. The drain of the U-phase NMOS transistor Q1 is connected to the cathode of the U-phase diode D1. The anode of the U-phase diode D1 is electrically connected to the PWM_UL signal input port of the driver chip. The base of the U-phase NPN transistor Q8 is connected to the sampling terminal of the U-phase sampling resistor R4 through the U-phase RC filter circuit. The collector of the U-phase NPN transistor Q8 is electrically connected to the PWM_UL signal input port of the driver chip. The emitter of the U-phase NPN transistor Q8 is connected to the negative terminal of the bus.

3. The three-phase hardware current detection protection circuit of claim 2, wherein, The U-phase RC filter circuit includes a resistor R5 and a capacitor C1. One end of the resistor R5 is connected to the base of the U-phase NPN transistor Q8, and the other end of the resistor R5 is connected to the sampling terminal of the U-phase sampling resistor R4 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the emitter of the U-phase NPN transistor Q8.

4. The three-phase hardware current detection protection circuit of claim 2, wherein, The U-phase detection and protection circuit further includes resistors R1, R2, and R3. The two ends of resistor R1 are connected to the IO port level V1 of the main control chip and the source of the U-phase NMOS transistor Q1, respectively. The two ends of resistor R3 are connected to the IO port level V1 and the gate of the U-phase NMOS transistor Q1, respectively. One end of resistor R2 is connected to the anode of the U-phase diode D1 and the collector of the U-phase NPN transistor Q8, respectively. The other end of resistor R2 is connected to the voltage recognition level V2 of the driver chip.

5. The three-phase hardware current detection protection circuit of claim 1, wherein, The V-phase detection and protection circuit includes a V-phase NMOS transistor Q10, a V-phase diode D2, a V-phase NPN transistor Q9, and a V-phase RC filter circuit. The source of the V-phase NMOS transistor Q10 is electrically connected to the V-phase lower PWM output port of the main control chip. The drain of the V-phase NMOS transistor Q10 is connected to the cathode of the V-phase diode D2. The anode of the V-phase diode D2 is electrically connected to the PWM_VL signal input port of the driver chip. The base of the V-phase NPN transistor Q9 is connected to the sampling terminal of the V-phase sampling resistor R6 through the V-phase RC filter circuit. The collector of the V-phase NPN transistor Q9 is electrically connected to the PWM_VL signal input port of the driver chip. The emitter of the V-phase NPN transistor Q9 is connected to the negative terminal of the bus.

6. The three-phase hardware current detection protection circuit of claim 5, wherein, The V-phase RC filter circuit includes a resistor R8 and a capacitor C2. One end of the resistor R8 is connected to the base of the V-phase NPN transistor Q9, and the other end of the resistor R8 is connected to the sampling terminal of the V-phase sampling resistor R6 and one end of the capacitor C2. The other end of the capacitor C2 is connected to the emitter of the V-phase NPN transistor Q9.

7. The three-phase hardware current detection protection circuit of claim 5, wherein, The V-phase detection and protection circuit further includes resistors R11, R10, and R9. The two ends of resistor R11 are connected to the I / O port level V1 of the main control chip and the source of the V-phase NMOS transistor Q10, respectively. The two ends of resistor R9 are connected to the I / O port level V1 and the gate of the V-phase NMOS transistor Q10, respectively. One end of resistor R10 is connected to the anode of the V-phase diode D2 and the collector of the V-phase NPN transistor Q9, respectively. The other end of resistor R10 is connected to the voltage recognition level V2 of the driver chip.

8. The three-phase hardware current detection protection circuit of claim 1, wherein, The W-phase detection and protection circuit includes a W-phase NMOS transistor Q12, a W-phase diode D3, a W-phase NPN transistor Q11, and a W-phase RC filter circuit. The source of the W-phase NMOS transistor Q12 is electrically connected to the W-phase lower transistor PWM output port of the main control chip. The drain of the W-phase NMOS transistor Q12 is connected to the cathode of the W-phase diode D3. The anode of the W-phase diode D3 is electrically connected to the PWM_WL signal input port of the driver chip. The base of the W-phase NPN transistor Q11 is connected to the sampling terminal of the W-phase sampling resistor R7 through the W-phase RC filter circuit. The collector of the W-phase NPN transistor Q11 is electrically connected to the PWM_WL signal input port of the driver chip. The emitter of the W-phase NPN transistor Q11 is connected to the negative terminal of the bus.

9. The three-phase hardware current detection protection circuit of claim 8, wherein, The W-phase RC filter circuit includes a resistor R12 and a capacitor C3. One end of the resistor R12 is connected to the base of the W-phase NPN transistor Q11. The other end of the resistor R12 is connected to the sampling terminal of the W-phase sampling resistor R7 and one end of the capacitor C3. The other end of the capacitor C3 is connected to the emitter of the W-phase NPN transistor Q11.

10. The three-phase hardware current detection protection circuit of claim 8, wherein, The W-phase detection and protection circuit further includes resistors R15, R14, and R13. The two ends of resistor R15 are connected to the IO port level V1 of the main control chip and the source of the W-phase NMOS transistor Q12, respectively. The two ends of resistor R13 are connected to the IO port level V1 and the gate of the W-phase NMOS transistor Q12, respectively. One end of resistor R14 is connected to the anode of the W-phase diode D3 and the collector of the W-phase NPN transistor Q11, respectively. The other end of resistor R14 is connected to the voltage recognition level V2 of the driver chip.

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